-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-- Date        : Wed Jan 28 14:35:06 2026
-- Host        : ixpc5 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -cell top_i/ip -mode synth_stub ../../../../02-ip_src_gen/ip_imp_OWDWE0_stub.vhd
-- Design      : ip_imp_OWDWE0
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xczu7ev-ffvc1156-2-i
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ip_imp_OWDWE0 is
  Port ( 
    clk_50_mhz : out STD_LOGIC;
    clk_250_mhz : out STD_LOGIC_VECTOR ( 0 to 0 );
    m0_bscan_bscanid_en : out STD_LOGIC;
    m0_bscan_capture : out STD_LOGIC;
    m0_bscan_drck : out STD_LOGIC;
    m0_bscan_reset : out STD_LOGIC;
    m0_bscan_runtest : out STD_LOGIC;
    m0_bscan_sel : out STD_LOGIC;
    m0_bscan_shift : out STD_LOGIC;
    m0_bscan_tck : out STD_LOGIC;
    m0_bscan_tdi : out STD_LOGIC;
    m0_bscan_tms : out STD_LOGIC;
    m0_bscan_update : out STD_LOGIC;
    sync_pulse : out STD_LOGIC;
    sampling_pulse : out STD_LOGIC;
    USR_tri_o : out STD_LOGIC_VECTOR ( 35 downto 0 );
    USR_tri_t : out STD_LOGIC_VECTOR ( 35 downto 0 );
    CLOCK_0_clk_en : out STD_LOGIC;
    CLOCK_0_period : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_0_prescaler : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_0_timer : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_1_clk_en : out STD_LOGIC;
    CLOCK_1_period : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_1_prescaler : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_1_timer : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_2_clk_en : out STD_LOGIC;
    CLOCK_2_period : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_2_prescaler : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_2_timer : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_3_clk_en : out STD_LOGIC;
    CLOCK_3_period : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_3_prescaler : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLOCK_3_timer : out STD_LOGIC_VECTOR ( 15 downto 0 );
    data_valid_pulse : out STD_LOGIC;
    cpu_core_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    fault : out STD_LOGIC;
    private_out : out STD_LOGIC_VECTOR ( 54 downto 0 );
    ADC_SANDBOX_32b_reg_00 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_01 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_02 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_03 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_04 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_05 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_06 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_07 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_08 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_09 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_11 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_12 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_14 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_15 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_16 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_20 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_21 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_22 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_SANDBOX_32b_reg_23 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_reg_00 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_01 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_02 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_03 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_04 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_05 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_06 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_07 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_08 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_09 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_12 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_13 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_14 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_15 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_17 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_18 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_19 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_20 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_21 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_22 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_reg_23 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ADC_FLOAT_reg_00 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_01 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_02 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_03 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_04 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_05 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_06 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_07 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_08 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_09 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_11 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_12 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_14 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_15 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_16 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_20 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_21 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_22 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ADC_FLOAT_reg_23 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    adc_done_float_pulse : out STD_LOGIC;
    adc_done_cpu_float_pulse : out STD_LOGIC;
    adc_done_cpu_pulse : out STD_LOGIC;
    adc_done_pulse : out STD_LOGIC;
    gt_refclk : out STD_LOGIC_VECTOR ( 0 to 0 );
    reading : out STD_LOGIC;
    SBIO_BUS_sb_addr : out STD_LOGIC_VECTOR ( 9 downto 0 );
    SBIO_BUS_sb_we : out STD_LOGIC;
    SBIO_BUS_sb_wdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
    dout : out STD_LOGIC_VECTOR ( 47 downto 0 );
    private_io : inout STD_LOGIC;
    m0_bscan_tdo : in STD_LOGIC;
    USR_tri_i : in STD_LOGIC_VECTOR ( 35 downto 0 );
    sb_pwm : in STD_LOGIC_VECTOR ( 47 downto 0 );
    inst_cb_pwm : in STD_LOGIC_VECTOR ( 47 downto 0 );
    inst_pp_pwm : in STD_LOGIC;
    inst_ss_pwm : in STD_LOGIC;
    private_in : in STD_LOGIC_VECTOR ( 97 downto 0 );
    din : in STD_LOGIC_VECTOR ( 23 downto 0 );
    user_fw_id : in STD_LOGIC_VECTOR ( 15 downto 0 );
    SBIO_BUS_sb_rdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );

end ip_imp_OWDWE0;

architecture stub of ip_imp_OWDWE0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_50_mhz,clk_250_mhz[0:0],m0_bscan_bscanid_en,m0_bscan_capture,m0_bscan_drck,m0_bscan_reset,m0_bscan_runtest,m0_bscan_sel,m0_bscan_shift,m0_bscan_tck,m0_bscan_tdi,m0_bscan_tms,m0_bscan_update,sync_pulse,sampling_pulse,USR_tri_o[35:0],USR_tri_t[35:0],CLOCK_0_clk_en,CLOCK_0_period[15:0],CLOCK_0_prescaler[15:0],CLOCK_0_timer[15:0],CLOCK_1_clk_en,CLOCK_1_period[15:0],CLOCK_1_prescaler[15:0],CLOCK_1_timer[15:0],CLOCK_2_clk_en,CLOCK_2_period[15:0],CLOCK_2_prescaler[15:0],CLOCK_2_timer[15:0],CLOCK_3_clk_en,CLOCK_3_period[15:0],CLOCK_3_prescaler[15:0],CLOCK_3_timer[15:0],data_valid_pulse,cpu_core_state[1:0],fault,private_out[54:0],ADC_SANDBOX_32b_reg_00[31:0],ADC_SANDBOX_32b_reg_01[31:0],ADC_SANDBOX_32b_reg_02[31:0],ADC_SANDBOX_32b_reg_03[31:0],ADC_SANDBOX_32b_reg_04[31:0],ADC_SANDBOX_32b_reg_05[31:0],ADC_SANDBOX_32b_reg_06[31:0],ADC_SANDBOX_32b_reg_07[31:0],ADC_SANDBOX_32b_reg_08[31:0],ADC_SANDBOX_32b_reg_09[31:0],ADC_SANDBOX_32b_reg_10[31:0],ADC_SANDBOX_32b_reg_11[31:0],ADC_SANDBOX_32b_reg_12[31:0],ADC_SANDBOX_32b_reg_13[31:0],ADC_SANDBOX_32b_reg_14[31:0],ADC_SANDBOX_32b_reg_15[31:0],ADC_SANDBOX_32b_reg_16[31:0],ADC_SANDBOX_32b_reg_17[31:0],ADC_SANDBOX_32b_reg_18[31:0],ADC_SANDBOX_32b_reg_19[31:0],ADC_SANDBOX_32b_reg_20[31:0],ADC_SANDBOX_32b_reg_21[31:0],ADC_SANDBOX_32b_reg_22[31:0],ADC_SANDBOX_32b_reg_23[31:0],ADC_reg_00[15:0],ADC_reg_01[15:0],ADC_reg_02[15:0],ADC_reg_03[15:0],ADC_reg_04[15:0],ADC_reg_05[15:0],ADC_reg_06[15:0],ADC_reg_07[15:0],ADC_reg_08[15:0],ADC_reg_09[15:0],ADC_reg_10[15:0],ADC_reg_11[15:0],ADC_reg_12[15:0],ADC_reg_13[15:0],ADC_reg_14[15:0],ADC_reg_15[15:0],ADC_reg_16[15:0],ADC_reg_17[15:0],ADC_reg_18[15:0],ADC_reg_19[15:0],ADC_reg_20[15:0],ADC_reg_21[15:0],ADC_reg_22[15:0],ADC_reg_23[15:0],ADC_FLOAT_reg_00[31:0],ADC_FLOAT_reg_01[31:0],ADC_FLOAT_reg_02[31:0],ADC_FLOAT_reg_03[31:0],ADC_FLOAT_reg_04[31:0],ADC_FLOAT_reg_05[31:0],ADC_FLOAT_reg_06[31:0],ADC_FLOAT_reg_07[31:0],ADC_FLOAT_reg_08[31:0],ADC_FLOAT_reg_09[31:0],ADC_FLOAT_reg_10[31:0],ADC_FLOAT_reg_11[31:0],ADC_FLOAT_reg_12[31:0],ADC_FLOAT_reg_13[31:0],ADC_FLOAT_reg_14[31:0],ADC_FLOAT_reg_15[31:0],ADC_FLOAT_reg_16[31:0],ADC_FLOAT_reg_17[31:0],ADC_FLOAT_reg_18[31:0],ADC_FLOAT_reg_19[31:0],ADC_FLOAT_reg_20[31:0],ADC_FLOAT_reg_21[31:0],ADC_FLOAT_reg_22[31:0],ADC_FLOAT_reg_23[31:0],adc_done_float_pulse,adc_done_cpu_float_pulse,adc_done_cpu_pulse,adc_done_pulse,gt_refclk[0:0],reading,SBIO_BUS_sb_addr[9:0],SBIO_BUS_sb_we,SBIO_BUS_sb_wdata[15:0],dout[47:0],private_io,m0_bscan_tdo,USR_tri_i[35:0],sb_pwm[47:0],inst_cb_pwm[47:0],inst_pp_pwm,inst_ss_pwm,private_in[97:0],din[23:0],user_fw_id[15:0],SBIO_BUS_sb_rdata[15:0]";
begin
end;
