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-- Company: 
-- Engineer: 
-- 
-- Create Date: 08/02/2024 01:36:33 PM
-- Design Name: 
-- Module Name: slice - impl
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity slice is
    Generic (
        DIN_FROM  : integer := 15;
        DIN_TO    : integer := 0;
        DIN_WIDTH : integer := 49
    );
    Port ( 
        Din  : in std_logic_vector((DIN_WIDTH - 1) downto 0);
        Dout  : out std_logic_vector(DIN_FROM downto DIN_TO)
    );
end slice;

architecture impl of slice is

begin

    Dout <= Din(DIN_FROM downto DIN_TO);

end impl;
