library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity sbio_registers is

	port (

		SBI_reg_00  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_01  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_02  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_03  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_04  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_05  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_06  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_07  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_08  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_09  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_10  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_11  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_12  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_13  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_14  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_15  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_16  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_17  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_18  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_19  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_20  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_21  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_22  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_23  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_24  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_25  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_26  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_27  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_28  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_29  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_30  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_31  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_32  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_33  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_34  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_35  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_36  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_37  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_38  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_39  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_40  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_41  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_42  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_43  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_44  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_45  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_46  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_47  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_48  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_49  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_50  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_51  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_52  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_53  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_54  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_55  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_56  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_57  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_58  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_59  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_60  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_61  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_62  : in std_logic_vector(15 downto 0) := (others => '0');
		SBI_reg_63  : in std_logic_vector(15 downto 0) := (others => '0');
--		SBI_reg_64  : in std_logic_vector(15 downto 0) := (others => '0');
--		SBI_reg_65  : in std_logic_vector(15 downto 0) := (others => '0');
--		SBI_reg_66  : in std_logic_vector(15 downto 0) := (others => '0');

		SBO_reg_00  : out std_logic_vector(15 downto 0);
		SBO_reg_01  : out std_logic_vector(15 downto 0);
		SBO_reg_02  : out std_logic_vector(15 downto 0);
		SBO_reg_03  : out std_logic_vector(15 downto 0);
		SBO_reg_04  : out std_logic_vector(15 downto 0);
		SBO_reg_05  : out std_logic_vector(15 downto 0);
		SBO_reg_06  : out std_logic_vector(15 downto 0);
		SBO_reg_07  : out std_logic_vector(15 downto 0);
		SBO_reg_08  : out std_logic_vector(15 downto 0);
		SBO_reg_09  : out std_logic_vector(15 downto 0);
		SBO_reg_10  : out std_logic_vector(15 downto 0);
		SBO_reg_11  : out std_logic_vector(15 downto 0);
		SBO_reg_12  : out std_logic_vector(15 downto 0);
		SBO_reg_13  : out std_logic_vector(15 downto 0);
		SBO_reg_14  : out std_logic_vector(15 downto 0);
		SBO_reg_15  : out std_logic_vector(15 downto 0);
		SBO_reg_16  : out std_logic_vector(15 downto 0);
		SBO_reg_17  : out std_logic_vector(15 downto 0);
		SBO_reg_18  : out std_logic_vector(15 downto 0);
		SBO_reg_19  : out std_logic_vector(15 downto 0);
		SBO_reg_20  : out std_logic_vector(15 downto 0);
		SBO_reg_21  : out std_logic_vector(15 downto 0);
		SBO_reg_22  : out std_logic_vector(15 downto 0);
		SBO_reg_23  : out std_logic_vector(15 downto 0);
		SBO_reg_24  : out std_logic_vector(15 downto 0);
		SBO_reg_25  : out std_logic_vector(15 downto 0);
		SBO_reg_26  : out std_logic_vector(15 downto 0);
		SBO_reg_27  : out std_logic_vector(15 downto 0);
		SBO_reg_28  : out std_logic_vector(15 downto 0);
		SBO_reg_29  : out std_logic_vector(15 downto 0);
		SBO_reg_30  : out std_logic_vector(15 downto 0);
		SBO_reg_31  : out std_logic_vector(15 downto 0);
		SBO_reg_32  : out std_logic_vector(15 downto 0);
		SBO_reg_33  : out std_logic_vector(15 downto 0);
		SBO_reg_34  : out std_logic_vector(15 downto 0);
		SBO_reg_35  : out std_logic_vector(15 downto 0);
		SBO_reg_36  : out std_logic_vector(15 downto 0);
		SBO_reg_37  : out std_logic_vector(15 downto 0);
		SBO_reg_38  : out std_logic_vector(15 downto 0);
		SBO_reg_39  : out std_logic_vector(15 downto 0);
		SBO_reg_40  : out std_logic_vector(15 downto 0);
		SBO_reg_41  : out std_logic_vector(15 downto 0);
		SBO_reg_42  : out std_logic_vector(15 downto 0);
		SBO_reg_43  : out std_logic_vector(15 downto 0);
		SBO_reg_44  : out std_logic_vector(15 downto 0);
		SBO_reg_45  : out std_logic_vector(15 downto 0);
		SBO_reg_46  : out std_logic_vector(15 downto 0);
		SBO_reg_47  : out std_logic_vector(15 downto 0);
		SBO_reg_48  : out std_logic_vector(15 downto 0);
		SBO_reg_49  : out std_logic_vector(15 downto 0);
		SBO_reg_50  : out std_logic_vector(15 downto 0);
		SBO_reg_51  : out std_logic_vector(15 downto 0);
		SBO_reg_52  : out std_logic_vector(15 downto 0);
		SBO_reg_53  : out std_logic_vector(15 downto 0);
		SBO_reg_54  : out std_logic_vector(15 downto 0);
		SBO_reg_55  : out std_logic_vector(15 downto 0);
		SBO_reg_56  : out std_logic_vector(15 downto 0);
		SBO_reg_57  : out std_logic_vector(15 downto 0);
		SBO_reg_58  : out std_logic_vector(15 downto 0);
		SBO_reg_59  : out std_logic_vector(15 downto 0);
		SBO_reg_60  : out std_logic_vector(15 downto 0);
		SBO_reg_61  : out std_logic_vector(15 downto 0);
		SBO_reg_62  : out std_logic_vector(15 downto 0);
		SBO_reg_63  : out std_logic_vector(15 downto 0);
--		SBO_reg_64  : out std_logic_vector(15 downto 0);
--		SBO_reg_65  : out std_logic_vector(15 downto 0);
--		SBO_reg_66  : out std_logic_vector(15 downto 0);
		
		SBIO_BUS_addr  : in  std_logic_vector(9 downto 0);
		SBIO_BUS_we    : in  std_logic;
		SBIO_BUS_wdata : in  std_logic_vector(15 downto 0);
		SBIO_BUS_rdata : out std_logic_vector(15 downto 0);

		clk_250_mhz      : in  std_logic
	);
end sbio_registers;

architecture Behavioral of sbio_registers is

    ATTRIBUTE X_INTERFACE_INFO : STRING;
    ATTRIBUTE X_INTERFACE_PARAMETER : STRING;

	ATTRIBUTE X_INTERFACE_INFO of SBIO_BUS_addr:  SIGNAL is "imperix.ch:ix:sbio_bus:1.0 SBIO_BUS sb_addr";
	ATTRIBUTE X_INTERFACE_INFO of SBIO_BUS_we:    SIGNAL is "imperix.ch:ix:sbio_bus:1.0 SBIO_BUS sb_we";
	ATTRIBUTE X_INTERFACE_INFO of SBIO_BUS_wdata: SIGNAL is "imperix.ch:ix:sbio_bus:1.0 SBIO_BUS sb_wdata";
	ATTRIBUTE X_INTERFACE_INFO of SBIO_BUS_rdata: SIGNAL is "imperix.ch:ix:sbio_bus:1.0 SBIO_BUS sb_rdata";

    ATTRIBUTE X_INTERFACE_INFO of clk_250_mhz: SIGNAL is "xilinx.com:signal:clock:1.0 clk_250_mhz CLK";
    ATTRIBUTE X_INTERFACE_PARAMETER of clk_250_mhz: SIGNAL is "ASSOCIATED_BUSIF SBIO_BUS";

    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_00: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_00";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_01: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_01";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_02: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_02";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_03: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_03";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_04: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_04";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_05: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_05";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_06: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_06";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_07: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_07";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_08: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_08";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_09: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_09";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_10: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_10";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_11: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_11";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_12: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_12";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_13: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_13";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_14: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_14";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_15: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_15";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_16: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_16";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_17: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_17";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_18: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_18";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_19: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_19";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_20: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_20";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_21: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_21";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_22: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_22";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_23: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_23";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_24: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_24";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_25: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_25";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_26: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_26";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_27: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_27";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_28: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_28";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_29: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_29";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_30: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_30";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_31: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_31";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_32: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_32";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_33: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_33";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_34: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_34";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_35: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_35";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_36: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_36";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_37: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_37";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_38: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_38";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_39: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_39";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_40: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_40";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_41: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_41";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_42: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_42";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_43: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_43";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_44: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_44";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_45: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_45";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_46: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_46";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_47: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_47";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_48: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_48";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_49: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_49";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_50: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_50";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_51: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_51";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_52: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_52";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_53: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_53";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_54: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_54";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_55: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_55";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_56: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_56";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_57: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_57";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_58: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_58";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_59: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_59";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_60: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_60";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_61: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_61";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_62: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_62";
    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_63: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_63";
--    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_64: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_64";
--    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_65: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_65";
--    ATTRIBUTE X_INTERFACE_INFO of SBI_reg_66: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBI reg_66";

    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_00: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_00";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_01: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_01";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_02: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_02";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_03: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_03";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_04: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_04";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_05: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_05";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_06: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_06";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_07: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_07";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_08: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_08";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_09: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_09";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_10: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_10";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_11: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_11";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_12: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_12";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_13: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_13";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_14: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_14";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_15: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_15";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_16: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_16";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_17: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_17";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_18: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_18";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_19: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_19";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_20: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_20";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_21: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_21";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_22: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_22";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_23: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_23";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_24: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_24";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_25: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_25";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_26: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_26";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_27: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_27";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_28: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_28";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_29: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_29";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_30: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_30";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_31: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_31";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_32: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_32";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_33: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_33";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_34: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_34";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_35: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_35";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_36: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_36";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_37: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_37";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_38: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_38";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_39: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_39";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_40: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_40";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_41: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_41";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_42: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_42";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_43: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_43";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_44: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_44";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_45: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_45";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_46: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_46";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_47: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_47";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_48: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_48";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_49: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_49";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_50: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_50";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_51: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_51";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_52: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_52";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_53: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_53";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_54: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_54";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_55: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_55";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_56: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_56";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_57: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_57";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_58: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_58";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_59: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_59";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_60: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_60";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_61: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_61";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_62: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_62";
    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_63: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_63";
--    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_64: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_64";
--    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_65: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_65";
--    ATTRIBUTE X_INTERFACE_INFO of SBO_reg_66: SIGNAL is "imperix.ch:ix:user_regs_rtl:1.0 SBO reg_66";

    signal r_addr_low_0 : std_logic_vector(3 downto 0);
    signal r_addr_low_1 : std_logic_vector(3 downto 0);
    signal r_addr_low_2 : std_logic_vector(3 downto 0);
    signal r_addr_low_3 : std_logic_vector(3 downto 0);
    signal r_addr_low_4 : std_logic_vector(3 downto 0);
    signal r_addr_low_5 : std_logic_vector(3 downto 0);
    signal r_addr_low_6 : std_logic_vector(3 downto 0);
    signal r_addr_low_7 : std_logic_vector(3 downto 0);
    signal r_addr_low_8 : std_logic_vector(3 downto 0);
    signal r_addr_low_9 : std_logic_vector(3 downto 0);
    signal r_addr_low_10 : std_logic_vector(3 downto 0);
    signal r_addr_low_11 : std_logic_vector(3 downto 0);
    signal r_addr_low_12 : std_logic_vector(3 downto 0);
    signal r_addr_low_13 : std_logic_vector(3 downto 0);
    signal r_addr_low_14 : std_logic_vector(3 downto 0);
    signal r_addr_low_15 : std_logic_vector(3 downto 0);

    signal r_addr_high_0 : std_logic_vector(3 downto 0);
    signal r_addr_high_1 : std_logic_vector(3 downto 0);
    signal r_addr_high_2 : std_logic_vector(3 downto 0);
    signal r_addr_high_3 : std_logic_vector(3 downto 0);
    signal r_addr_high_4 : std_logic_vector(3 downto 0);
    signal r_addr_high_5 : std_logic_vector(3 downto 0);
    signal r_addr_high_6 : std_logic_vector(3 downto 0);
    signal r_addr_high_7 : std_logic_vector(3 downto 0);
    signal r_addr_high_8 : std_logic_vector(3 downto 0);
    signal r_addr_high_9 : std_logic_vector(3 downto 0);
    signal r_addr_high_10 : std_logic_vector(3 downto 0);
    signal r_addr_high_11 : std_logic_vector(3 downto 0);
    signal r_addr_high_12 : std_logic_vector(3 downto 0);
    signal r_addr_high_13 : std_logic_vector(3 downto 0);
    signal r_addr_high_14 : std_logic_vector(3 downto 0);
    signal r_addr_high_15 : std_logic_vector(3 downto 0);

    signal r_addr     : natural range 0 to 255;
    signal r_addr_ff  : natural range 0 to 255;
    signal r_addr_ff2 : natural range 0 to 255;
	
    signal r_we  :	std_logic;

    signal r_wdata_0   :   std_logic_vector(15 downto 0);
    signal r_wdata_1   :   std_logic_vector(15 downto 0);
    signal r_wdata_2   :   std_logic_vector(15 downto 0);
    signal r_wdata_3   :   std_logic_vector(15 downto 0);
    signal r_wdata_4   :   std_logic_vector(15 downto 0);
    signal r_wdata_5   :   std_logic_vector(15 downto 0);
    signal r_wdata_6   :   std_logic_vector(15 downto 0);
    signal r_wdata_7   :   std_logic_vector(15 downto 0);
    signal r_wdata_8   :   std_logic_vector(15 downto 0);
    signal r_wdata_9   :   std_logic_vector(15 downto 0);
    signal r_wdata_10  :   std_logic_vector(15 downto 0);
    signal r_wdata_11  :   std_logic_vector(15 downto 0);
    signal r_wdata_12  :   std_logic_vector(15 downto 0);
    signal r_wdata_13  :   std_logic_vector(15 downto 0);
    signal r_wdata_14  :   std_logic_vector(15 downto 0);
    signal r_wdata_15  :   std_logic_vector(15 downto 0);
	
    signal w_addr_0 : natural range 0 to 15;
    signal w_addr_1 : natural range 0 to 15;
    signal w_addr_2 : natural range 0 to 15;
    signal w_addr_3 : natural range 0 to 15;
    signal w_addr_4 : natural range 0 to 15;
    signal w_addr_5 : natural range 0 to 15;
    signal w_addr_6 : natural range 0 to 15;
    signal w_addr_7 : natural range 0 to 15;
    signal w_addr_8 : natural range 0 to 15;
    signal w_addr_9 : natural range 0 to 15;
    signal w_addr_10: natural range 0 to 15;
    signal w_addr_11: natural range 0 to 15;
    signal w_addr_12: natural range 0 to 15;
    signal w_addr_13: natural range 0 to 15;
    signal w_addr_14: natural range 0 to 15;
    signal w_addr_15: natural range 0 to 15;

    signal w_bank_0 : natural range 0 to 15;
    signal w_bank_1 : natural range 0 to 15;
    signal w_bank_2 : natural range 0 to 15;
    signal w_bank_3 : natural range 0 to 15;
    signal w_bank_4 : natural range 0 to 15;
    signal w_bank_5 : natural range 0 to 15;
    signal w_bank_6 : natural range 0 to 15;
    signal w_bank_7 : natural range 0 to 15;
    signal w_bank_8 : natural range 0 to 15;
    signal w_bank_9 : natural range 0 to 15;
    signal w_bank_10: natural range 0 to 15;
    signal w_bank_11: natural range 0 to 15;
    signal w_bank_12: natural range 0 to 15;
    signal w_bank_13: natural range 0 to 15;
    signal w_bank_14: natural range 0 to 15;
    signal w_bank_15: natural range 0 to 15;

    type type_sbo_bank is array(natural range 0 to 15) of std_logic_vector(15 downto 0);
    signal r_sbo_bank0  : type_sbo_bank;
    signal r_sbo_bank1  : type_sbo_bank;
    signal r_sbo_bank2  : type_sbo_bank;
    signal r_sbo_bank3  : type_sbo_bank;
    signal r_sbo_bank4  : type_sbo_bank;
    signal r_sbo_bank5  : type_sbo_bank;
    signal r_sbo_bank6  : type_sbo_bank;
    signal r_sbo_bank7  : type_sbo_bank;
    signal r_sbo_bank8  : type_sbo_bank;
    signal r_sbo_bank9  : type_sbo_bank;
    signal r_sbo_bank10 : type_sbo_bank;
    signal r_sbo_bank11 : type_sbo_bank;
    signal r_sbo_bank12 : type_sbo_bank;
    signal r_sbo_bank13 : type_sbo_bank;
    signal r_sbo_bank14 : type_sbo_bank;
    signal r_sbo_bank15 : type_sbo_bank;

    type type_sbi is array(natural range 0 to 255) of std_logic_vector(15 downto 0);
    signal r_sbi : type_sbi;

    attribute KEEP : string;
    attribute KEEP of r_addr_low_0   : signal is "true";
    attribute KEEP of r_addr_low_1   : signal is "true";
    attribute KEEP of r_addr_low_2   : signal is "true";
    attribute KEEP of r_addr_low_3   : signal is "true";
    attribute KEEP of r_addr_low_4   : signal is "true";
    attribute KEEP of r_addr_low_5   : signal is "true";
    attribute KEEP of r_addr_low_6   : signal is "true";
    attribute KEEP of r_addr_low_7   : signal is "true";
    attribute KEEP of r_addr_low_8   : signal is "true";
    attribute KEEP of r_addr_low_9   : signal is "true";
    attribute KEEP of r_addr_low_10  : signal is "true";
    attribute KEEP of r_addr_low_11  : signal is "true";
    attribute KEEP of r_addr_low_12  : signal is "true";
    attribute KEEP of r_addr_low_13  : signal is "true";
    attribute KEEP of r_addr_low_14  : signal is "true";
    attribute KEEP of r_addr_low_15  : signal is "true";
    attribute KEEP of r_addr_high_0  : signal is "true";
    attribute KEEP of r_addr_high_1  : signal is "true";
    attribute KEEP of r_addr_high_2  : signal is "true";
    attribute KEEP of r_addr_high_3  : signal is "true";
    attribute KEEP of r_addr_high_4  : signal is "true";
    attribute KEEP of r_addr_high_5  : signal is "true";
    attribute KEEP of r_addr_high_6  : signal is "true";
    attribute KEEP of r_addr_high_7  : signal is "true";
    attribute KEEP of r_addr_high_8  : signal is "true";
    attribute KEEP of r_addr_high_9  : signal is "true";
    attribute KEEP of r_addr_high_10 : signal is "true";
    attribute KEEP of r_addr_high_11 : signal is "true";
    attribute KEEP of r_addr_high_12 : signal is "true";
    attribute KEEP of r_addr_high_13 : signal is "true";
    attribute KEEP of r_addr_high_14 : signal is "true";
    attribute KEEP of r_addr_high_15 : signal is "true";
    attribute KEEP of r_wdata_0      : signal is "true";
    attribute KEEP of r_wdata_1      : signal is "true";
    attribute KEEP of r_wdata_2      : signal is "true";
    attribute KEEP of r_wdata_3      : signal is "true";
    attribute KEEP of r_wdata_4      : signal is "true";
    attribute KEEP of r_wdata_5      : signal is "true";
    attribute KEEP of r_wdata_6      : signal is "true";
    attribute KEEP of r_wdata_7      : signal is "true";
    attribute KEEP of r_wdata_8      : signal is "true";
    attribute KEEP of r_wdata_9      : signal is "true";
    attribute KEEP of r_wdata_10     : signal is "true";
    attribute KEEP of r_wdata_11     : signal is "true";
    attribute KEEP of r_wdata_12     : signal is "true";
    attribute KEEP of r_wdata_13     : signal is "true";
    attribute KEEP of r_wdata_14     : signal is "true";
    attribute KEEP of r_wdata_15     : signal is "true";

    attribute SAVE : string;
    attribute SAVE of r_addr_low_0   : signal is "true";
    attribute SAVE of r_addr_low_1   : signal is "true";
    attribute SAVE of r_addr_low_2   : signal is "true";
    attribute SAVE of r_addr_low_3   : signal is "true";
    attribute SAVE of r_addr_low_4   : signal is "true";
    attribute SAVE of r_addr_low_5   : signal is "true";
    attribute SAVE of r_addr_low_6   : signal is "true";
    attribute SAVE of r_addr_low_7   : signal is "true";
    attribute SAVE of r_addr_low_8   : signal is "true";
    attribute SAVE of r_addr_low_9   : signal is "true";
    attribute SAVE of r_addr_low_10  : signal is "true";
    attribute SAVE of r_addr_low_11  : signal is "true";
    attribute SAVE of r_addr_low_12  : signal is "true";
    attribute SAVE of r_addr_low_13  : signal is "true";
    attribute SAVE of r_addr_low_14  : signal is "true";
    attribute SAVE of r_addr_low_15  : signal is "true";
    attribute SAVE of r_addr_high_0  : signal is "true";
    attribute SAVE of r_addr_high_1  : signal is "true";
    attribute SAVE of r_addr_high_2  : signal is "true";
    attribute SAVE of r_addr_high_3  : signal is "true";
    attribute SAVE of r_addr_high_4  : signal is "true";
    attribute SAVE of r_addr_high_5  : signal is "true";
    attribute SAVE of r_addr_high_6  : signal is "true";
    attribute SAVE of r_addr_high_7  : signal is "true";
    attribute SAVE of r_addr_high_8  : signal is "true";
    attribute SAVE of r_addr_high_9  : signal is "true";
    attribute SAVE of r_addr_high_10 : signal is "true";
    attribute SAVE of r_addr_high_11 : signal is "true";
    attribute SAVE of r_addr_high_12 : signal is "true";
    attribute SAVE of r_addr_high_13 : signal is "true";
    attribute SAVE of r_addr_high_14 : signal is "true";
    attribute SAVE of r_addr_high_15 : signal is "true";
    attribute SAVE of r_wdata_0      : signal is "true";
    attribute SAVE of r_wdata_1      : signal is "true";
    attribute SAVE of r_wdata_2      : signal is "true";
    attribute SAVE of r_wdata_3      : signal is "true";
    attribute SAVE of r_wdata_4      : signal is "true";
    attribute SAVE of r_wdata_5      : signal is "true";
    attribute SAVE of r_wdata_6      : signal is "true";
    attribute SAVE of r_wdata_7      : signal is "true";
    attribute SAVE of r_wdata_8      : signal is "true";
    attribute SAVE of r_wdata_9      : signal is "true";
    attribute SAVE of r_wdata_10     : signal is "true";
    attribute SAVE of r_wdata_11     : signal is "true";
    attribute SAVE of r_wdata_12     : signal is "true";
    attribute SAVE of r_wdata_13     : signal is "true";
    attribute SAVE of r_wdata_14     : signal is "true";
    attribute SAVE of r_wdata_15     : signal is "true";

begin

    w_addr_0 <= to_integer(unsigned(r_addr_low_0));
    w_addr_1 <= to_integer(unsigned(r_addr_low_1));
    w_addr_2 <= to_integer(unsigned(r_addr_low_2));
    w_addr_3 <= to_integer(unsigned(r_addr_low_3));
    w_addr_4 <= to_integer(unsigned(r_addr_low_4));
    w_addr_5 <= to_integer(unsigned(r_addr_low_5));
    w_addr_6 <= to_integer(unsigned(r_addr_low_6));
    w_addr_7 <= to_integer(unsigned(r_addr_low_7));
    w_addr_8 <= to_integer(unsigned(r_addr_low_8));
    w_addr_9 <= to_integer(unsigned(r_addr_low_9));
    w_addr_10 <= to_integer(unsigned(r_addr_low_10));
    w_addr_11 <= to_integer(unsigned(r_addr_low_11));
    w_addr_12 <= to_integer(unsigned(r_addr_low_12));
    w_addr_13 <= to_integer(unsigned(r_addr_low_13));
    w_addr_14 <= to_integer(unsigned(r_addr_low_14));
    w_addr_15 <= to_integer(unsigned(r_addr_low_15));

    w_bank_0 <= to_integer(unsigned(r_addr_high_0));
    w_bank_1 <= to_integer(unsigned(r_addr_high_1));
    w_bank_2 <= to_integer(unsigned(r_addr_high_2));
    w_bank_3 <= to_integer(unsigned(r_addr_high_3));
    w_bank_4 <= to_integer(unsigned(r_addr_high_4));
    w_bank_5 <= to_integer(unsigned(r_addr_high_5));
    w_bank_6 <= to_integer(unsigned(r_addr_high_6));
    w_bank_7 <= to_integer(unsigned(r_addr_high_7));
    w_bank_8 <= to_integer(unsigned(r_addr_high_8));
    w_bank_9 <= to_integer(unsigned(r_addr_high_9));
    w_bank_10 <= to_integer(unsigned(r_addr_high_10));
    w_bank_11 <= to_integer(unsigned(r_addr_high_11));
    w_bank_12 <= to_integer(unsigned(r_addr_high_12));
    w_bank_13 <= to_integer(unsigned(r_addr_high_13));
    w_bank_14 <= to_integer(unsigned(r_addr_high_14));
    w_bank_15 <= to_integer(unsigned(r_addr_high_15));

	A : process(clk_250_mhz)
	begin
		if rising_edge(clk_250_mhz) then
			r_sbi(0)  <= SBI_reg_00;
			r_sbi(1)  <= SBI_reg_01;
			r_sbi(2)  <= SBI_reg_02;
			r_sbi(3)  <= SBI_reg_03;
			r_sbi(4)  <= SBI_reg_04;
			r_sbi(5)  <= SBI_reg_05;
			r_sbi(6)  <= SBI_reg_06;
			r_sbi(7)  <= SBI_reg_07;
			r_sbi(8)  <= SBI_reg_08;
			r_sbi(9)  <= SBI_reg_09;
			r_sbi(10) <= SBI_reg_10;
			r_sbi(11) <= SBI_reg_11;
			r_sbi(12) <= SBI_reg_12;
			r_sbi(13) <= SBI_reg_13;
			r_sbi(14) <= SBI_reg_14;
			r_sbi(15) <= SBI_reg_15;
			r_sbi(16) <= SBI_reg_16;
			r_sbi(17) <= SBI_reg_17;
			r_sbi(18) <= SBI_reg_18;
			r_sbi(19) <= SBI_reg_19;
			r_sbi(20) <= SBI_reg_20;
			r_sbi(21) <= SBI_reg_21;
			r_sbi(22) <= SBI_reg_22;
			r_sbi(23) <= SBI_reg_23;
			r_sbi(24) <= SBI_reg_24;
			r_sbi(25) <= SBI_reg_25;
			r_sbi(26) <= SBI_reg_26;
			r_sbi(27) <= SBI_reg_27;
			r_sbi(28) <= SBI_reg_28;
			r_sbi(29) <= SBI_reg_29;
			r_sbi(30) <= SBI_reg_30;
			r_sbi(31) <= SBI_reg_31;
			r_sbi(32) <= SBI_reg_32;
			r_sbi(33) <= SBI_reg_33;
			r_sbi(34) <= SBI_reg_34;
			r_sbi(35) <= SBI_reg_35;
			r_sbi(36) <= SBI_reg_36;
			r_sbi(37) <= SBI_reg_37;
			r_sbi(38) <= SBI_reg_38;
			r_sbi(39) <= SBI_reg_39;
			r_sbi(40) <= SBI_reg_40;
			r_sbi(41) <= SBI_reg_41;
			r_sbi(42) <= SBI_reg_42;
			r_sbi(43) <= SBI_reg_43;
			r_sbi(44) <= SBI_reg_44;
			r_sbi(45) <= SBI_reg_45;
			r_sbi(46) <= SBI_reg_46;
			r_sbi(47) <= SBI_reg_47;
			r_sbi(48) <= SBI_reg_48;
			r_sbi(49) <= SBI_reg_49;
			r_sbi(50) <= SBI_reg_50;
			r_sbi(51) <= SBI_reg_51;
			r_sbi(52) <= SBI_reg_52;
			r_sbi(53) <= SBI_reg_53;
			r_sbi(54) <= SBI_reg_54;
			r_sbi(55) <= SBI_reg_55;
			r_sbi(56) <= SBI_reg_56;
			r_sbi(57) <= SBI_reg_57;
			r_sbi(58) <= SBI_reg_58;
			r_sbi(59) <= SBI_reg_59;
			r_sbi(60) <= SBI_reg_60;
			r_sbi(61) <= SBI_reg_61;
			r_sbi(62) <= SBI_reg_62;
			r_sbi(63) <= SBI_reg_63;

			r_we    <= SBIO_BUS_we;
			
			r_wdata_0  <= SBIO_BUS_wdata;
			r_wdata_1  <= SBIO_BUS_wdata;
			r_wdata_2  <= SBIO_BUS_wdata;
			r_wdata_3  <= SBIO_BUS_wdata;
			r_wdata_4  <= SBIO_BUS_wdata;
			r_wdata_5  <= SBIO_BUS_wdata;
			r_wdata_6  <= SBIO_BUS_wdata;
			r_wdata_7  <= SBIO_BUS_wdata;
			r_wdata_8  <= SBIO_BUS_wdata;
			r_wdata_9  <= SBIO_BUS_wdata;
			r_wdata_10 <= SBIO_BUS_wdata;
			r_wdata_11 <= SBIO_BUS_wdata;
			r_wdata_12 <= SBIO_BUS_wdata;
			r_wdata_13 <= SBIO_BUS_wdata;
			r_wdata_14 <= SBIO_BUS_wdata;
			r_wdata_15 <= SBIO_BUS_wdata;

			r_addr <= to_integer(unsigned(SBIO_BUS_addr(7 downto 0)));
			r_addr_ff <= r_addr;
			r_addr_ff2 <= r_addr_ff;
			SBIO_BUS_rdata <= r_sbi(r_addr_ff2); -- latency of 4

			r_addr_low_0  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_1  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_2  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_3  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_4  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_5  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_6  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_7  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_8  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_9  <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_10 <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_11 <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_12 <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_13 <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_14 <= SBIO_BUS_addr(3 downto 0);
			r_addr_low_15 <= SBIO_BUS_addr(3 downto 0);

			r_addr_high_0  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_1  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_2  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_3  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_4  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_5  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_6  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_7  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_8  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_9  <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_10 <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_11 <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_12 <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_13 <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_14 <= SBIO_BUS_addr(7 downto 4);
			r_addr_high_15 <= SBIO_BUS_addr(7 downto 4);

			if r_we = '1' then
				if w_bank_0 = 0 then
					r_sbo_bank0(w_addr_0) <= r_wdata_0;
				elsif w_bank_1 = 1 then
					r_sbo_bank1(w_addr_1) <= r_wdata_1;
				elsif w_bank_2 = 2 then
					r_sbo_bank2(w_addr_2) <= r_wdata_2;
			    elsif w_bank_3 = 3 then
					r_sbo_bank3(w_addr_3) <= r_wdata_3;
				elsif w_bank_4 = 4 then
					r_sbo_bank4(w_addr_4) <= r_wdata_4;
				elsif w_bank_5 = 5 then
					r_sbo_bank5(w_addr_5) <= r_wdata_5;
				elsif w_bank_6 = 6 then
					r_sbo_bank6(w_addr_6) <= r_wdata_6;
				elsif w_bank_7 = 7 then
					r_sbo_bank7(w_addr_7) <= r_wdata_7;
				elsif w_bank_8 = 8 then
					r_sbo_bank8(w_addr_8) <= r_wdata_8;
				elsif w_bank_9 = 9 then
					r_sbo_bank9(w_addr_9) <= r_wdata_9;
				elsif w_bank_10 = 10 then
					r_sbo_bank10(w_addr_10) <= r_wdata_10;
				elsif w_bank_11 = 11 then
					r_sbo_bank11(w_addr_11) <= r_wdata_11;
				elsif w_bank_12 = 12 then
					r_sbo_bank12(w_addr_12) <= r_wdata_12;
				elsif w_bank_13 = 13 then
					r_sbo_bank13(w_addr_13) <= r_wdata_13;
				elsif w_bank_14 = 14 then
					r_sbo_bank14(w_addr_14) <= r_wdata_14;
				else
					r_sbo_bank15(w_addr_15) <= r_wdata_15;
				end if;
			end if;
		end if;
	end process A;

    SBO_reg_00  <= r_sbo_bank0(0);
    SBO_reg_01  <= r_sbo_bank0(1);
    SBO_reg_02  <= r_sbo_bank0(2);
    SBO_reg_03  <= r_sbo_bank0(3);
    SBO_reg_04  <= r_sbo_bank0(4);
    SBO_reg_05  <= r_sbo_bank0(5);
    SBO_reg_06  <= r_sbo_bank0(6);
    SBO_reg_07  <= r_sbo_bank0(7);
    SBO_reg_08  <= r_sbo_bank0(8);
    SBO_reg_09  <= r_sbo_bank0(9);
    SBO_reg_10  <= r_sbo_bank0(10);
    SBO_reg_11  <= r_sbo_bank0(11);
    SBO_reg_12  <= r_sbo_bank0(12);
    SBO_reg_13  <= r_sbo_bank0(13);
    SBO_reg_14  <= r_sbo_bank0(14);
    SBO_reg_15  <= r_sbo_bank0(15);
    SBO_reg_16  <= r_sbo_bank1(0);
    SBO_reg_17  <= r_sbo_bank1(1);
    SBO_reg_18  <= r_sbo_bank1(2);
    SBO_reg_19  <= r_sbo_bank1(3);
    SBO_reg_20  <= r_sbo_bank1(4);
    SBO_reg_21  <= r_sbo_bank1(5);
    SBO_reg_22  <= r_sbo_bank1(6);
    SBO_reg_23  <= r_sbo_bank1(7);
    SBO_reg_24  <= r_sbo_bank1(8);
    SBO_reg_25  <= r_sbo_bank1(9);
    SBO_reg_26  <= r_sbo_bank1(10);
    SBO_reg_27  <= r_sbo_bank1(11);
    SBO_reg_28  <= r_sbo_bank1(12);
    SBO_reg_29  <= r_sbo_bank1(13);
    SBO_reg_30  <= r_sbo_bank1(14);
    SBO_reg_31  <= r_sbo_bank1(15);
    SBO_reg_32  <= r_sbo_bank2(0);
    SBO_reg_33  <= r_sbo_bank2(1);
    SBO_reg_34  <= r_sbo_bank2(2);
    SBO_reg_35  <= r_sbo_bank2(3);
    SBO_reg_36  <= r_sbo_bank2(4);
    SBO_reg_37  <= r_sbo_bank2(5);
    SBO_reg_38  <= r_sbo_bank2(6);
    SBO_reg_39  <= r_sbo_bank2(7);
    SBO_reg_40  <= r_sbo_bank2(8);
    SBO_reg_41  <= r_sbo_bank2(9);
    SBO_reg_42  <= r_sbo_bank2(10);
    SBO_reg_43  <= r_sbo_bank2(11);
    SBO_reg_44  <= r_sbo_bank2(12);
    SBO_reg_45  <= r_sbo_bank2(13);
    SBO_reg_46  <= r_sbo_bank2(14);
    SBO_reg_47  <= r_sbo_bank2(15);
    SBO_reg_48  <= r_sbo_bank3(0);
    SBO_reg_49  <= r_sbo_bank3(1);
    SBO_reg_50  <= r_sbo_bank3(2);
    SBO_reg_51  <= r_sbo_bank3(3);
    SBO_reg_52  <= r_sbo_bank3(4);
    SBO_reg_53  <= r_sbo_bank3(5);
    SBO_reg_54  <= r_sbo_bank3(6);
    SBO_reg_55  <= r_sbo_bank3(7);
    SBO_reg_56  <= r_sbo_bank3(8);
    SBO_reg_57  <= r_sbo_bank3(9);
    SBO_reg_58  <= r_sbo_bank3(10);
    SBO_reg_59  <= r_sbo_bank3(11);
    SBO_reg_60  <= r_sbo_bank3(12);
    SBO_reg_61  <= r_sbo_bank3(13);
    SBO_reg_62  <= r_sbo_bank3(14);
    SBO_reg_63  <= r_sbo_bank3(15);
--    SBO_reg_64  <= r_sbo_bank4(0);
--    SBO_reg_65  <= r_sbo_bank4(1);
--    SBO_reg_66  <= r_sbo_bank4(2);

end Behavioral;
