{"id":1547,"date":"2021-04-02T12:28:15","date_gmt":"2021-04-02T12:28:15","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=1547"},"modified":"2025-05-07T12:05:02","modified_gmt":"2025-05-07T12:05:02","slug":"fpga-based-hysteresis-controller-hdl-coder","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder","title":{"rendered":"FPGA-based hysteresis controller for three-phase inverter using HDL Coder"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder\/#Software-resources\" >Software resources<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder\/#FPGA-logic-implementation\" >FPGA logic implementation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder\/#Validation-of-the-FPGA-based-hysteresis-controller-by-simulation\" >Validation of the FPGA-based hysteresis controller by simulation<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder\/#Testbench\" >Testbench<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder\/#Control-loop-simulation\" >Control loop simulation<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder\/#Integration-of-the-HDL-design-in-the-FPGA-firmware\" >Integration of the HDL design in the FPGA firmware<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>This technical note shows how the implementation of an FPGA-based hysteresis controller can be conducted, starting from the modeling stage, following with automated VHDL code generation with HDL Coder, and finishing with its validation in simulation. As an application example, this note uses the hysteresis current control already shown in&nbsp;<a href=\"https:\/\/imperix.com\/doc\/implementation\/hysteresis-current-control\">TN120<\/a>.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\">HDL Coder<\/a> is a MATLAB tool that generates HDL code from Matlab or Simulink models, which can then be integrated into an FPGA. This approach can greatly accelerate rapid prototyping as the design is performed from a higher level of abstraction. The second benefit is the possibility to simulate the FPGA logic in a control loop, directly from within Simulink.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">This example has been written before the release of the newest <em><a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">FPGA control template<\/a><\/em>, as such is does not implement the latest recommendations such as the use of AXI4-Stream interfaces.<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-software-resources\"><span class=\"ez-toc-section\" id=\"Software-resources\"><\/span>Software resources<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<div class=\"wp-block-file\"><a id=\"wp-block-file--media-53a9dcf6-49cc-4ec6-8d03-0e9342f69288\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/hdl_dcc_ctrl_loop_2015a.slx\">hysteresis_current_control_Simulink_HDL_coder<\/a><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/hdl_dcc_ctrl_loop_2015a.slx\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-53a9dcf6-49cc-4ec6-8d03-0e9342f69288\">Download<\/a><\/div>\n\n\n\n<div class=\"wp-block-file\"><a id=\"wp-block-file--media-0fd4adfe-c65e-405a-93fe-74fe0725b128\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/hdl_dcc_testbench_2015a.slx\">hysteresis_current_control_Simulink_testbench<\/a><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/hdl_dcc_testbench_2015a.slx\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-0fd4adfe-c65e-405a-93fe-74fe0725b128\">Download<\/a><\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-fpga-logic-implementation\"><span class=\"ez-toc-section\" id=\"FPGA-logic-implementation\"><\/span>FPGA logic implementation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Below is the hysteresis current controller (also called direct current control [DCC]) logic implementation is taken from&nbsp;<a href=\"https:\/\/imperix.com\/doc\/implementation\/hysteresis-current-control\">TN120<\/a>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"886\" height=\"429\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-108.png\" alt=\"FPGA logic of the hysteresis controller\" class=\"wp-image-2077\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-108.png 886w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-108-300x145.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-108-768x372.png 768w\" sizes=\"auto, (max-width: 886px) 100vw, 886px\" \/><\/figure>\n\n\n\n<p>An equivalent logic can be transcribed in Simulink using HDL Coder-compatible blocks, as shown in the next figure. The <em>Data Type Conversion<\/em> blocks force the input signals to be interpreted as signed integers, the<em> Enabled Subsystems<\/em> infer the flip-flop registers, and the Stateflow\u2019s <em>State Transition Table<\/em> block is used to easily implement the state machine.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"925\" height=\"586\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-114.png\" alt=\"FPGA logic developed with HDL Coder\" class=\"wp-image-2097\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-114.png 925w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-114-300x190.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-114-768x487.png 768w\" sizes=\"auto, (max-width: 925px) 100vw, 925px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\" id=\"h-validation-of-the-fpga-based-hysteresis-controller-by-simulation\"><span class=\"ez-toc-section\" id=\"Validation-of-the-FPGA-based-hysteresis-controller-by-simulation\"><\/span>Validation of the FPGA-based hysteresis controller by simulation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The validation of the FPGA-based hysteresis controller is done in two phases. First, the design is placed in a testbench model and stimulated with various test signals. The second phase is the integration of the design in the control model to simulate its behavior in a closed control loop.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-testbench\"><span class=\"ez-toc-section\" id=\"Testbench\"><\/span>Testbench<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The tests must be as comprehensive as possible to see if the design operates as expected in all conditions. The following figure illustrates one of the validation steps, where the state machine transitions are tested by applying a sinusoidal signal to <code>meas<\/code> and a fixed value to the other inputs. The results are visually inspected using a scope that shows that the PWM signal has the correct state and the transition occurs when the difference between <code>meas<\/code> and <code>ref<\/code> is equal to <code>tol<\/code>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"521\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-115-1024x521.png\" alt=\"Simulink model of testbench used for validation of the FPGA hysteresis current control\" class=\"wp-image-2098\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-115-1024x521.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-115-300x153.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-115-768x391.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-115.png 1160w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h3 class=\"wp-block-heading\" id=\"h-control-loop-simulation\"><span class=\"ez-toc-section\" id=\"Control-loop-simulation\"><\/span>Control loop simulation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The second phase is the integration of this design within the control model already used in&nbsp;<a href=\"https:\/\/imperix.com\/doc\/implementation\/hysteresis-current-control\">TN120<\/a>. The objective is to simulate its behavior in a closed control loop. The <em>simulated FPGA logic<\/em> block takes as input the ADC values, scaled to match the actual 16-bit ADC output provided by the imperix firmware IP, as well as the values applied to the SBO blocks. The PWM output is conveyed to the plant model.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"706\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-116-1024x706.png\" alt=\"Simulink model of the CPU-side implementation for hysteresis current control\" class=\"wp-image-2099\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-116-1024x706.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-116-300x207.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-116-768x530.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-116.png 1388w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p>The content of the <em>simulated FPGA logic<\/em> block is shown in the next figure. It contains three instances of the DCC subsystem and a complementary PWM signal generation system. Due to the time scale of a control simulation, it is impractical to simulate the behavior of <code>adc_done<\/code> and the <code>delay<\/code>. To ignore them, they have been set to 1 and 0, respectively.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"784\" height=\"368\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-117.png\" alt=\"FPGA logic simulation blocks\" class=\"wp-image-2100\" style=\"width:549px;height:258px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-117.png 784w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-117-300x141.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-117-768x360.png 768w\" sizes=\"auto, (max-width: 784px) 100vw, 784px\" \/><\/figure>\n<\/div>\n\n\n<p>The sampling frequency (CLOCK_0) has been set to 400 kHz but the postscaler has been kept to 0 to simulate the \u201cfast\u201d FPGA logic. To emulate the \u201cslow\u201d logic reference generation (40kHz), the <em>angle <\/em>block has been configured to have a sample time of ten times the sampling frequency. Further details regarding this configuration can be found in&nbsp;<a href=\"https:\/\/imperix.com\/doc\/implementation\/hysteresis-current-control\">TN120<\/a>.<\/p>\n\n\n\n<p>The following graphs show the simulation results for a current reference of 4 A and a hysteresis tolerance of \u00b10.3 A and \u00b10.1 A, which are very close to the experimental measurements of&nbsp;<a href=\"https:\/\/imperix.com\/doc\/implementation\/hysteresis-current-control\">TN120<\/a>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"349\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-118-1024x349.png\" alt=\"Simulation results of the FPGA-based hysteresis current control\" class=\"wp-image-2101\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-118-1024x349.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-118-300x102.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-118-768x261.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-118-1536x523.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-118.png 1780w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\" id=\"h-integration-of-the-hdl-design-in-the-fpga-firmware\"><span class=\"ez-toc-section\" id=\"Integration-of-the-HDL-design-in-the-FPGA-firmware\"><\/span>Integration of the HDL design in the FPGA firmware<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Once the implementation has been validated in simulation, the VHDL sources can be generated and integrated into the sandbox environment, as shown in the next figure. Step-by-step instructions, as well as general design recommendations regarding the implementation of custom FPGA firmware, can be found in <a href=\"https:\/\/imperix.com\/doc\/help\/editing-the-fpga-firmware-using-the-sandbox\">PN116<\/a>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"820\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-119-1024x820.png\" alt=\"Interfacing between the hysteresis current controller and imperix IP\" class=\"wp-image-2102\" title=\"Technical notes &gt; TN121: FPGA-based hysteresis control using HDL Coder &gt; image-20200409-134551.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-119-1024x820.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-119-300x240.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-119-768x615.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/04\/image-119.png 1273w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>This technical note shows how the implementation of an FPGA-based hysteresis controller can be conducted, starting from the modeling stage, following with automated VHDL code&#8230;<\/p>\n","protected":false},"author":4,"featured_media":3044,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[4],"tags":[17],"software-environments":[106,103],"provided-results":[108,107],"related-products":[50,31,32,92,166,51,110],"guidedreadings":[],"tutorials":[],"user-manuals":[],"coauthors":[70],"class_list":["post-1547","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-implementation","tag-fpga-programming","software-environments-fpga","software-environments-matlab","provided-results-experimental","provided-results-simulation","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-cpp-sdk","related-products-tpi"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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