{"id":30982,"date":"2024-11-11T10:18:14","date_gmt":"2024-11-11T10:18:14","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=30982"},"modified":"2026-02-11T08:08:11","modified_gmt":"2026-02-11T08:08:11","slug":"example-of-fpga-based-aurora-8b-10b-communication","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication","title":{"rendered":"Example of FPGA-based Aurora communication"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#What-is-Aurora\" >What is Aurora ?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#Aurora-8B10B-loopback-example\" >Aurora 8B\/10B loopback example<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#Vivado-project\" >Vivado project<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#MATLAB-model\" >MATLAB model<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#Experimental-results\" >Experimental results<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#Step-by-step-procedure-to-create-the-Aurora-8B10B-loopback-example\" >Step-by-step procedure to create the Aurora 8B\/10B loopback example<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#Aurora-64B66B-loopback-example\" >Aurora 64B\/66B loopback example<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\/#Going-further\" >Going further<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>The SFP ports on imperix controllers are typically used for interconnecting devices in a <a href=\"https:\/\/imperix.com\/technology\/low-latency-communication\/\">RealSync network<\/a>. However, when customizing the FPGA firmware, imperix designed the system to allow these SFP ports to be repurposed for other communication protocols. Aurora 8B\/10B or Aurora 64B\/66B can be used to communicate with hardware-in-the-loop (HIL) simulators that support the Aurora protocol, such as <a href=\"https:\/\/opal-rt.atlassian.net\/wiki\/spaces\/PRUH\/pages\/144527838\/FPGA_IO_Aurora_8b10b_5G_250M\">OPAL-RT<\/a>, <a href=\"https:\/\/www.typhoon-hil.com\/documentation\/typhoon-hil-software-manual\/References\/sfp_link.html\">TYPHOON HIL<\/a>, <a href=\"https:\/\/www.speedgoat.com\/products\/simulink-programmable-fpgas-fpga-code-module-aurora\">SPEEDGOAT<\/a> and <a href=\"https:\/\/knowledge.rtds.com\/hc\/en-us\/articles\/4415386203927-Aurora-Protocol\">RTDS<\/a>.<\/p>\n\n\n\n<p>This note provides an example of loopback communication using the Aurora 8B\/10B protocol over a fiber optic link. It provides a step-by-step guide demonstrating how the Aurora 8B\/10B protocol can be seamlessly integrated into the imperix controller FPGA. An example of Aurora 64B\/66B is also provided.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Examples of SFP communication with third-party hardware-in-the-loop (HIL) simulators are introduced in <a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\" type=\"link\" id=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\">SFP communication with third-party devices<\/a>. Specific pages with ready-to-use scripts are available for <a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-opal-rt-via-sfp\">OPAL-RT<\/a>, <a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-plexim-via-sfp\">Plexim<\/a> and <a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\">RTDS<\/a>.<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p>Required hardware to follow this example:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>1x imperix controller with SFP ports<br>(<a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a> or <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">TPI8032<\/a>)<\/li>\n\n\n\n<li>1x <a href=\"https:\/\/imperix.com\/products\/control\/accessories\/\">10G SFP cable<\/a><\/li>\n<\/ul>\n\n\n\n<p>Required software:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Xilinx Vivado 2022.1<\/strong> or later.<br>Installation guide available <a href=\"https:\/\/imperix.com\/doc\/help\/vivado-design-suite-installation\">here<\/a>.<\/li>\n\n\n\n<li><strong>FPGA<\/strong> <strong>sandbox template 3.10<\/strong> or later.<br>Available on the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox\">FPGA download<\/a> page.<\/li>\n\n\n\n<li><strong>C++ or ACG SDK version 2024.3<\/strong> or later.<br>Available on the <a href=\"https:\/\/imperix.com\/downloads\/\">SDK download<\/a> page.<\/li>\n<\/ul>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"768\" height=\"1024\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/IMG_20241030_163117750-768x1024.jpg\" alt=\"\" class=\"wp-image-31127\" style=\"width:296px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/IMG_20241030_163117750-768x1024.jpg 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/IMG_20241030_163117750-225x300.jpg 225w\" sizes=\"auto, (max-width: 768px) 100vw, 768px\" \/><figcaption class=\"wp-element-caption\">Hardware used in this Aurora 8B\/10B example: a B-Board with a loopback connection between SFP 0 and SFP 1<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">FPGA-based Aurora communication is available for SDK version 2024.3 or later. Latest SDK version is available on the <a href=\"https:\/\/imperix.com\/downloads\/\">download page<\/a>.<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, please visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"What-is-Aurora\"><\/span>What is Aurora ?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Aurora is a serial link layer communication protocol developed by Xilinx\/AMD. The protocol is open and provides lightweight, high-speed point-to-point communication between devices. Implementing Aurora communication is particularly useful for establishing high-throughput, low-latency communication with other power controllers or HIL simulators. The protocol is available in two versions: Aurora 8B\/10B and Aurora 64\/66B. Aurora 8B\/10B provides lower latency while Aurora 64B\/66B provides higher bandwidth.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Aurora-8B10B-loopback-example\"><\/span>Aurora 8B\/10B loopback example<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>For demonstration purposes, a loopback connection is established between two ports on the same controller, as shown in the diagram below:<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"527\" height=\"323\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Aurora-8B10B-loopback.png\" alt=\"\" class=\"wp-image-31537\" style=\"width:527px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Aurora-8B10B-loopback.png 527w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Aurora-8B10B-loopback-300x184.png 300w\" sizes=\"auto, (max-width: 527px) 100vw, 527px\" \/><figcaption class=\"wp-element-caption\">Diagram of the architecture of the system implemented in the loopback example<\/figcaption><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> and <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> blocks are used to move data between the CPU and the FPGA.<\/li>\n\n\n\n<li>FIFOs are used to move data between the IXIP clock domain (250 MHz) and the Aurora communication clock domain (78.125 MHz in this example).<\/li>\n\n\n\n<li><a href=\"https:\/\/docs.amd.com\/r\/en-US\/pg046-aurora-8b10b\/Aurora-8B\/10B-v11.1-LogiCORE-IP-Product-Guide\" target=\"_blank\" rel=\"noreferrer noopener\">Aurora 8B10B IPs<\/a>&nbsp;encode\/decode data.<\/li>\n\n\n\n<li>TX\/RX serial links are connected to physical SFP ports to transmit data over the optical fiber.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"vivado-project\"><span class=\"ez-toc-section\" id=\"Vivado-project\"><\/span>Vivado project<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The Vivado block design of the Aurora 8B\/10B loopback example is provided below.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"387\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-3-1024x387.png\" alt=\"\" class=\"wp-image-31153\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-3-1024x387.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-3-300x113.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-3-768x290.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-3-1536x580.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-3.png 1858w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Example-of-FPGA-based-Aurora-8B10B-communication.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Click here<\/a> to open as PDF<\/figcaption><\/figure>\n\n\n\n<p>The following zip file contains scripts to automatically generate this design.<\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a id=\"wp-block-file--media-691dcb5c-c90f-4d82-9426-1e9365e5a5f3\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/create_aurora_8b10b_example.zip\">create_aurora_8b10b_example<\/a><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/create_aurora_8b10b_example.zip\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-691dcb5c-c90f-4d82-9426-1e9365e5a5f3\">Download <strong>Aurora_8b10b_example_gen_scripts.zip<\/strong><\/a><\/div>\n\n\n\n<p>To generate the design using the script, please do the following:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Download the <strong>FPGA<\/strong> <strong>sandbox template 3.10<\/strong> or later, available on the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox\">FPGA download<\/a> page<\/li>\n\n\n\n<li>Unzip it and save the content somewhere on the PC<\/li>\n\n\n\n<li>Rename the folder to something more explicit<\/li>\n<\/ul>\n\n\n\n<p class=\"has-text-align-center\"><br><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"115\" class=\"wp-image-32153\" style=\"width: 800px;\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/ss_aurora_8b10_example-2.png\" alt=\"\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/ss_aurora_8b10_example-2.png 606w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/ss_aurora_8b10_example-2-300x43.png 300w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Download <strong>Aurora_8b10b_example_gen_scripts.zip<\/strong> using the button above<\/li>\n\n\n\n<li>Unzip it and copy the content to the scripts folder of the FPGA sandbox template<\/li>\n<\/ul>\n\n\n\n<p class=\"has-text-align-center\"><br><img loading=\"lazy\" decoding=\"async\" width=\"609\" height=\"245\" class=\"wp-image-31191\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-5.png\" alt=\"\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-5.png 609w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-5-300x121.png 300w\" sizes=\"auto, (max-width: 609px) 100vw, 609px\" \/><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Set the <em>vivado_path <\/em>variable to match the Vivado version installed on the PC<\/li>\n<\/ul>\n\n\n\n<p class=\"has-text-align-center\"><br><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"245\" class=\"wp-image-32155\" style=\"width: 800px;\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/ss_create_aurora_8b10b_example.png\" alt=\"\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/ss_create_aurora_8b10b_example.png 471w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/ss_create_aurora_8b10b_example-300x92.png 300w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Double-click on create_aurora_8b10b_example.bat<br>Windows Defender SmartScreen may display a warning pop-up. Simply click&nbsp;More info,&nbsp;then&nbsp;<em>Run anyway.<\/em><\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"610\" height=\"166\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-6.png\" alt=\"\" class=\"wp-image-31192\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-6.png 610w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-6-300x82.png 300w\" sizes=\"auto, (max-width: 610px) 100vw, 610px\" \/><\/figure>\n<\/div>\n\n\n<p>The Vivado Aurora 8B\/10B project will be created and configured. The step-by-step section below explains how to recreate it manually.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"MATLAB-model\"><\/span>MATLAB model<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The model below is used to test the design. It generates a sinusoidal waveform and sends it to the FPGA using SBI 0 and 1. It reads the received on SBO 2 and 3. <a href=\"https:\/\/imperix.com\/doc\/software\/probe-variable\">Probe variables<\/a> are used to observe the sent and received signals on Cockpit.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"287\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_matlab-1024x287.png\" alt=\"\" class=\"wp-image-31134\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_matlab-1024x287.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_matlab-300x84.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_matlab-768x215.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_matlab-1536x431.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_matlab.png 1768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/SFP_communication_loopback.slx\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>SFP_communication_loopback.slx<\/strong><\/a><\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Experimental-results\"><\/span>Experimental results<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p><span style=\"box-sizing: border-box; margin: 0px; padding: 0px;\">Observing the signals on&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/cockpit-user-guide\" target=\"_blank\" rel=\"noopener\">Cockpit<\/a>&nbsp;validates that the data sent on port SFP 0 using Aurora 8B\/10B is properly received on port SFP 1.<\/span><\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"745\" height=\"403\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_cockpit.png\" alt=\"\" class=\"wp-image-31136\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_cockpit.png 745w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_cockpit-300x162.png 300w\" sizes=\"auto, (max-width: 745px) 100vw, 745px\" \/><\/figure>\n\n\n\n<p>Thanks to the Aurora 8B\/10B low latency, there is a delay of 2 control task periods between sending and receiving data.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"746\" height=\"378\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_cockpit_2.png\" alt=\"\" class=\"wp-image-31139\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_cockpit_2.png 746w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_cockpit_2-300x152.png 300w\" sizes=\"auto, (max-width: 746px) 100vw, 746px\" \/><\/figure>\n\n\n\n<p>Using the Integrated Logic Analyzer (ILA) in Vivado, the propagation delays of the data in the FPGA can be measured. With a lane rate of <strong>3.125 Gbps<\/strong>, the total measured delay is <strong>560 ns<\/strong>. It consists in:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>84 ns<\/strong> for the TX FIFO data<\/li>\n\n\n\n<li><strong>424 ns<\/strong> for the Aurora communication<\/li>\n\n\n\n<li><strong>52 ns<\/strong> for the RX FIFO<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"309\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_ila-1-1024x309.png\" alt=\"\" class=\"wp-image-31141\" style=\"width:787px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_ila-1-1024x309.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_ila-1-300x91.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_ila-1-768x232.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_ila-1.png 1092w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Propagation delay of the data in the FPGA. The acquisition was done with a clock of 250 MHz.<\/figcaption><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Step-by-step-procedure-to-create-the-Aurora-8B10B-loopback-example\"><\/span>Step-by-step procedure to create the Aurora 8B\/10B loopback example<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h4 class=\"wp-block-heading\">Instantiating the Aurora 8B\/10B IP<\/h4>\n\n\n\n<p>The first step is to instantiate 2 Aurora IPs. The Aurora 8B\/10B IP is available for free from the Vivado IP Catalog.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"822\" height=\"341\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-1.png\" alt=\"\" class=\"wp-image-31151\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-1.png 822w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-1-300x124.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-1-768x319.png 768w\" sizes=\"auto, (max-width: 822px) 100vw, 822px\" \/><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Configuring the Aurora 8B\/10B IP<\/h4>\n\n\n\n<p>The screenshots below show the settings used in this example. The two following parameters must be set to specific values to work on imperix hardware:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>GT Reflck<\/strong> must be set to 250 MHz, because the clock is generated outside of the FPGA<\/li>\n\n\n\n<li>&#8220;<strong>include Shared Logic in example design<\/strong>\u201d must be checked, because the Shared Logic is already instantiated inside imperix firmware<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"532\" height=\"549\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/aurora_core_options.png\" alt=\"\" class=\"wp-image-31102\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/aurora_core_options.png 532w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/aurora_core_options-291x300.png 291w\" sizes=\"auto, (max-width: 532px) 100vw, 532px\" \/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"614\" height=\"747\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/aurora_shared_logic_option.png\" alt=\"\" class=\"wp-image-31103\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/aurora_shared_logic_option.png 614w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/aurora_shared_logic_option-247x300.png 247w\" sizes=\"auto, (max-width: 614px) 100vw, 614px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>The other Core Options settings can be modified freely. Below are the settings used in this example:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>A <strong>lane width of 4 Bytes<\/strong> was chosen to be easily interfaced to the AXI-Stream interface.<\/li>\n\n\n\n<li>The default <strong>line rate of 3.125 Gbps<\/strong> was kept. This will result in a data clock of <br>line_rate * 0.8 \/ lane_width_in_bits = (3.125 Gbps * 0.8) \/ (32 bits) = 78.125 MHz<\/li>\n\n\n\n<li><span style=\"box-sizing: border-box; margin: 0px; padding: 0px;\">In this example, making packets is unnecessary, so the interface is set to<strong>&nbsp;streaming mode.<\/strong><\/span><\/li>\n<\/ul>\n\n\n\n<p>Other Core Options settings are not detailed in this note and are left as defaults.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"configuring-ix-ip\">Configuring the imperix IP<\/h4>\n\n\n\n<p>The second step is to configure the imperix firmware IP to make the SFP ports available from the sandbox. In this example, SFP 0 and 1 are used.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"829\" height=\"612\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/sfp_config_loopback.png\" alt=\"\" class=\"wp-image-31115\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/sfp_config_loopback.png 829w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/sfp_config_loopback-300x221.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/sfp_config_loopback-768x567.png 768w\" sizes=\"auto, (max-width: 829px) 100vw, 829px\" \/><figcaption class=\"wp-element-caption\">SFP settings of the imperix IP<\/figcaption><\/figure>\n<\/div>\n\n\n<p>This makes the following ports visible on the imperix IP.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>TX and RX signals are the differential serial signals connected between the transceiver and the physical SFP ports.<\/li>\n\n\n\n<li>The GT interface gives access to the shared logic instantiated in the imperix IP.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"576\" height=\"714\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-2.png\" alt=\"\" class=\"wp-image-31152\" style=\"width:460px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-2.png 576w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-2-242x300.png 242w\" sizes=\"auto, (max-width: 576px) 100vw, 576px\" \/><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\">Connecting the clocks of the Aurora 8B\/10B IP<\/h4>\n\n\n\n<p>The Aurora IP provides a <strong>tx_out_clk<\/strong> (78.125 MHz in this example), which is used as the user_clock. A <a href=\"https:\/\/docs.amd.com\/r\/en-US\/ug953-vivado-7series-libraries\/BUFG\">BUFG buffer<\/a> is required between tx_out_clk and the clock inputs. The init clocks and DRP clocks are connected to <strong>clk_50_mhz<\/strong> provided by the imperix firmware IP.<\/p>\n\n\n\n<p>To learn more about the different clocks, please refer to the <a href=\"https:\/\/docs.amd.com\/r\/en-US\/pg046-aurora-8b10b\/Aurora-8B\/10B-v11.1-LogiCORE-IP-Product-Guide\" target=\"_blank\" rel=\"noreferrer noopener\">Aurora 8B10B IP<\/a> and the <a href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ug476_7Series_Transceivers\">GTX transceiver<\/a> user guides.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"949\" height=\"626\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_clock_interface.png\" alt=\"\" class=\"wp-image-31116\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_clock_interface.png 949w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_clock_interface-300x198.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_clock_interface-768x507.png 768w\" sizes=\"auto, (max-width: 949px) 100vw, 949px\" \/><figcaption class=\"wp-element-caption\">Aurora IP clock connections<\/figcaption><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\">Connecting the data interfaces of the Aurora 8B\/10B IP<\/h4>\n\n\n\n<p>The <em>AXI-Stream interface<\/em>&nbsp;module (ix_axis_interface) is used to exchange data with the Aurora IPs. As the AXI-Stream interface module and the Aurora IPs are not in the same clock domain, <a href=\"https:\/\/docs.amd.com\/r\/en-US\/pg085-axi4stream-infrastructure\/AXI4-Stream-Data-FIFO\">AXI4-Stream Data FIFO<\/a> with independent clocks are used to manage the clock domain crossing. The figure below shows how the FIFOs are connected in the system.<\/p>\n\n\n\n<p>To learn more about the AXI-Stream interface module, please refer to the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">getting started<\/a> page.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"645\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_data_interface-2-1024x645.png\" alt=\"\" class=\"wp-image-31121\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_data_interface-2-1024x645.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_data_interface-2-300x189.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_data_interface-2-768x484.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_data_interface-2.png 1466w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\">Connecting the shared logic interface of the Aurora 8B\/10B IP<\/h4>\n\n\n\n<p>The following signals, connected to the <em>shared logic<\/em> of Aurora, must be connected between the GT interface of the imperix firmware IP and each Aurora IP:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>gt0_qplllock<\/li>\n\n\n\n<li>gt0_qpllrefclklost<\/li>\n\n\n\n<li>gt_qpllclk_quad1<\/li>\n\n\n\n<li>gt_qpllrefclk_quad1<\/li>\n\n\n\n<li>gt_refclk1<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"852\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_shared_logic-1024x852.png\" alt=\"\" class=\"wp-image-31123\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_shared_logic-1024x852.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_shared_logic-300x250.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_shared_logic-768x639.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/loopback_shared_logic.png 1172w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\"> Connecting the TX\/RX signals of the Aurora 8B\/10B IP<\/h4>\n\n\n\n<p>Finally, the <strong>rxn<\/strong>, <strong>rxp<\/strong>, <strong>txn<\/strong>, and <strong>txp <\/strong>signals of each Aurora IP must be connected to the corresponding pins of the imperix firmware IP to map each Aurora IP to a physical SFP port on the board.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"836\" height=\"730\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/image.png\" alt=\"\" class=\"wp-image-31124\" style=\"width:674px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/image.png 836w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/image-300x262.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/10\/image-768x671.png 768w\" sizes=\"auto, (max-width: 836px) 100vw, 836px\" \/><\/figure>\n<\/div>\n\n\n<p>Finally, the bitstream can be generated and loaded in an imperix controller, as explained on the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">getting started<\/a> page.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Aurora-64B66B-loopback-example\"><\/span>Aurora 64B\/66B loopback example<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>In a similar manner to the Aurora 8B\/10B example, it is possible to configure an Aurora 64B\/66B communication on SFP ports. This section details the steps to adapt the Aurora 8B\/10B example described in the previous section to use an Aurora 64B\/66B communication.<\/p>\n\n\n\n<p>The Vivado block design of the Aurora 64B\/66B loopback example is shown below.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"348\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/image-1024x348.png\" alt=\"\" class=\"wp-image-32196\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/image-1024x348.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/image-300x102.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/image-768x261.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/image-1536x522.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/image.png 1904w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/aurora_64b_66b.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Click here<\/a> to open as PDF<\/figcaption><\/figure>\n\n\n\n<p>The following zip file contains scripts to automatically generate this design.<\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a id=\"wp-block-file--media-dbee8e82-4753-4992-96b9-b4fead008481\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/aurora_64b66b_example.zip\">aurora_64b66b_example<\/a><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/aurora_64b66b_example.zip\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-dbee8e82-4753-4992-96b9-b4fead008481\">Download <strong>aurora_64b66b_example.zip<\/strong><\/a><\/div>\n\n\n\n<p>To use the script , please follow the <a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication#vivado-project\">same instructions<\/a> as for the 8B\/10B  example. Since this example has the same behavior as the 8B\/10B example, it is possible to reuse the <a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication#matlab\">MATLAB model<\/a> above  to test the design.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Instantiating the Aurora 64B\/66B IPs<\/h4>\n\n\n\n<p>The two Aurora 8B\/10B IPs are replaced by Aurora 64B\/66B IPs.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"412\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_aurora-1024x412.png\" alt=\"\" class=\"wp-image-32205\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_aurora-1024x412.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_aurora-300x121.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_aurora-768x309.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_aurora.png 1049w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>The connections of the following signals are the same as for the Aurora 8B\/10B IP:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>init and DRP clocks<\/strong> are connected to&nbsp;<strong>clk_50_mhz<\/strong>, which is&nbsp;provided by the imperix firmware IP.<\/li>\n\n\n\n<li>The shared logic signals (<strong>refclk1_in<\/strong>, <strong>gt_qpllclk_quad1<\/strong>,<strong>gt_qpllrefclk_quad1<\/strong>) are connected to&nbsp;the <strong>GT interface <\/strong>of the imperix firmware IP.<\/li>\n\n\n\n<li>The&nbsp;<strong>rxn<\/strong>,&nbsp;<strong>rxp<\/strong>,&nbsp;<strong>txn<\/strong> and&nbsp;<strong>txp&nbsp;<\/strong>signals are connected to the imperix firmware IP.<\/li>\n<\/ul>\n\n\n\n<p>The configuration of the Aurora 64B\/66B IP follows the same rules as the Aurora 8B\/10B IP:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>GT Reflck<\/strong>&nbsp;must be set to <strong>250 MHz<\/strong> as the clock is generated outside the FPGA.<\/li>\n\n\n\n<li>&#8220;<strong>Include Shared Logic in example design<\/strong>&#8221; must be checked, because the shared logic is already instantiated inside the imperix firmware.<\/li>\n\n\n\n<li>The &nbsp;other settings can be changed freely.&nbsp;<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\">Connecting the Aurora 64B\/66B IP clocks <\/h4>\n\n\n\n<p>A <strong>Clocking Wizard<\/strong> is instantiated for each Aurora 64B\/66B IP to generate the user clock and the sync clock from the tx_out clock. The <strong>Clocking Wizard<\/strong> is configured as follows:<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"967\" height=\"685\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_1.png\" alt=\"\" class=\"wp-image-32226\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_1.png 967w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_1-300x213.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_1-768x544.png 768w\" sizes=\"auto, (max-width: 967px) 100vw, 967px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The primitive is set to <strong>MMCM<\/strong>.<\/li>\n\n\n\n<li>The <strong>input frequency<\/strong> is set to the tx_out_clk frequency of the Aurora 64B\/66B IP. This frequency can be calculated from the line rate: <em>tx_out_clk_freq = line_rate \/ 32<\/em>. With a line rate of 5 Gbps we get a <strong>tx_out_clk<\/strong> of <strong>156.25 MHz<\/strong>.<\/li>\n\n\n\n<li>The <strong>source <\/strong>is set to <strong>Global buffer<\/strong>.<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"699\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_2-1024x699.png\" alt=\"\" class=\"wp-image-32227\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_2-1024x699.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_2-300x205.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_2-768x524.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_2.png 1133w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The<strong> frequency of output 1<\/strong> is set to half the frequency of <strong>tx_out_clk<\/strong>, in this example <strong>78.125 MHz<\/strong>.<\/li>\n\n\n\n<li>The <strong>frequency of output 2<\/strong> is set to the same frequency as <strong>tx_out_clk<\/strong>, in this example <strong>156.25 MHz<\/strong>.<\/li>\n\n\n\n<li>The <strong>drive <\/strong>buffer for both outputs is set to <strong>BUFG <\/strong>.<\/li>\n<\/ul>\n\n\n\n<p>The <strong>Clocking Wizards<\/strong> are connected  to the Aurora 64B\/66B IP as follows:<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"428\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_3-1024x428.png\" alt=\"\" class=\"wp-image-32247\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_3-1024x428.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_3-300x125.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_3-768x321.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_clk_wiz_3.png 1387w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>input<\/strong> of the Clocking Wizard is connected to <strong>tx_out_clk<\/strong> on the Aurora 64B\/66B IP.<\/li>\n\n\n\n<li><strong>Output 1<\/strong> of the Clocking Wizard is connected to <strong>user_clk<\/strong> on the Aurora 64B\/66B IP.<\/li>\n\n\n\n<li><strong>Output 2<\/strong> of the Clocking Wizard is connected to <strong>sync_clk<\/strong> on the Aurora 64B\/66B IP.<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\">Connecting the Aurora 64B\/66B IP reset signals<\/h4>\n\n\n\n<p>Unlike the Aurora 8B\/10B IP, the Aurora 64B\/66B must be properly reset during initialisation to function properly. In this example, the reset is handled by the Processor System Reset IP provided by Xilinx\/AMD. The IP is used with default settings and connected as follows:<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"655\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_rst-1024x655.png\" alt=\"\" class=\"wp-image-32250\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_rst-1024x655.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_rst-300x192.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_rst-768x491.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2025\/01\/64b_66b_rst.png 1086w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>slowest_syn_clk <\/strong>input of the Processor System Reset IP is connected to the <strong>init_clk <\/strong>of the Aurora 64B\/66B IP.<\/li>\n\n\n\n<li>The <strong>ext_reset_in<\/strong>, <strong>aux_reset_in<\/strong> and <strong>dcm_locked<\/strong> inputs are connected to a <strong>constant set to 1<\/strong>.<\/li>\n\n\n\n<li>The <strong>pma_init<\/strong> signal of the Aurora 64B\/66B IP is connected to the <strong>bus_struct_reset<\/strong>.<\/li>\n\n\n\n<li>The <strong>reset_pb<\/strong> signal of the Aurora 64B\/66B IP is connected to the <strong>peripheral_reset<\/strong>.<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\">Connecting the data interfaces of the Aurora 64B\/66B IP<\/h4>\n\n\n\n<p>Since the Aurora 64B\/66B provides a 64-bit data interface, 64-bit FIFOs are used and the data from the AXI stream interface is padded with 32 additional zeros to comply with the FIFOs&#8217; width. Additional zeros are then removed in the incoming stream before being fed back to the AXI stream interface.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"261\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_1-1024x261.png\" alt=\"\" class=\"wp-image-32271\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_1-1024x261.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_1-300x76.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_1-768x196.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_1.png 1275w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"210\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_2-1024x210.png\" alt=\"\" class=\"wp-image-32272\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_2-1024x210.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_2-300x62.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_2-768x158.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/64b_66b_clk_fifo_2.png 1311w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>Finally, the bitstream can be generated&nbsp;and used in the same way as in the Aurora 8B\/10B example.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-going-further\"><span class=\"ez-toc-section\" id=\"Going-further\"><\/span>Going further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The page&nbsp;<a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">high-level synthesis for FPGA<\/a>&nbsp;developments shows how automated code generation tools such as <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> and <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a> can be used to facilitate the development of FPGA modules. Like the Aurora 8B\/10B IP, they use AXI4-Streams to move data around. <\/p>\n\n\n\n<p>The <a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development on imperix controllers<\/a> summarizes all the other FPGA-related pages.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The SFP ports on imperix controllers are typically used for interconnecting devices in a RealSync network. However, when customizing the FPGA firmware, imperix designed the&#8230;<\/p>\n","protected":false},"author":26,"featured_media":31250,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106,103],"provided-results":[108],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[142],"coauthors":[102,82],"class_list":["post-30982","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","software-environments-matlab","provided-results-experimental","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","user-manuals-going-further-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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