{"id":31245,"date":"2024-12-18T11:15:36","date_gmt":"2024-12-18T11:15:36","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=31245"},"modified":"2026-01-23T13:28:05","modified_gmt":"2026-01-23T13:28:05","slug":"sfp-communication-with-an-rtds-mmc-simulator","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator","title":{"rendered":"SFP communication with an RTDS MMC simulator"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Communication-chain\" >Communication chain<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Required-software\" >Required software<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Downloads\" >Downloads<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Results\" >Results<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Provided-files\" >Provided files<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Simulink-model\" >Simulink model<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Vivado-project\" >Vivado project<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\/#Going-further\" >Going further<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>As introduced in <a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">PN118<\/a>, SFP communication constitutes a convenient way to interconnect devices. Widely used, it offers an efficient layer on which protocols such as Aurora can be implemented to exchange data.<\/p>\n\n\n\n<p>In this example, the SFP communication connects a <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a> (or <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a>) to a HIL simulator from <a href=\"https:\/\/www.rtds.com\/\">RTDS<\/a>. It makes the bridge between the control \u2013 executed in the <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a> (or <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a>) \u2013 and a simulation model of an MMC converter running on the GTSOC board.<\/p>\n\n\n\n<p>Following the configuration of the <a href=\"https:\/\/imperix.com\/products\/modular-multilevel-converter\/\">MMC bundle<\/a>, the simulated MMC contains 6 arms and 4 submodules per arm, as shown in Fig. 1. The closed-loop model provided to show proper communication and control of the MMC is also directly adapted from the <a href=\"https:\/\/imperix.com\/doc\/implementation\/mmc-converter\">AN009<\/a>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1928\" height=\"1032\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/kb_illustration_resized.png\" alt=\"B-Box with RTDS MMC Simulator Setup\" class=\"wp-image-35838\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/kb_illustration_resized.png 1928w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/kb_illustration_resized-300x161.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/kb_illustration_resized-1024x548.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/kb_illustration_resized-768x411.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/kb_illustration_resized-1536x822.png 1536w\" sizes=\"auto, (max-width: 1928px) 100vw, 1928px\" \/><figcaption class=\"wp-element-caption\">Fig. 1 &#8211; Illustration of the considered setup<\/figcaption><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Communication-chain\"><\/span>Communication chain<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The control and communication chain is depicted in Fig. 2. The closed-loop control running in the CPU of the B-Box controller generates duty cycles, which are converted to PWM signals by the carrier-based modulator (CB-PWM). These PWM signals are directly available in the FPGA, where they are packed into frames by the RTDS MMC driver and transferred to the MMC simulation model via Aurora 8B\/10B.<\/p>\n\n\n\n<p>The simulation model outputs computed voltages and currents, as well as additional real-time data (e.g. submodules status), and sends them back as Aurora frames to the B-Box (or B-Board). Once received, the frames are decoded by the driver and their content is made available to the B-Box CPU through SBI registers.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"788\" height=\"235\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/overall-structure_v2.png\" alt=\"Overall communication chain, including the SFP communication.\" class=\"wp-image-31553\" style=\"width:684px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/overall-structure_v2.png 788w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/overall-structure_v2-300x89.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/overall-structure_v2-768x229.png 768w\" sizes=\"auto, (max-width: 788px) 100vw, 788px\" \/><figcaption class=\"wp-element-caption\">Fig. 2 &#8211; Overall communication chain, including the SFP communication.<\/figcaption><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Required-software\"><\/span>Required software<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Xilinx Vivado 2022.1<\/strong> or later (previous versions may work but have not been tested).<br>Installation guide available <a href=\"https:\/\/imperix.com\/doc\/help\/vivado-design-suite-installation\">here<\/a>.<\/li>\n\n\n\n<li><strong>FPGA<\/strong> <strong>sandbox template 3.10<\/strong> or later.<br>Available on the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox\">FPGA download<\/a> page.<\/li>\n\n\n\n<li><strong>C++ or ACG SDK version 2024.3<\/strong> or later.<br>Available on the <a href=\"https:\/\/imperix.com\/downloads\/\">SDK download<\/a> page.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">FPGA-based Aurora communication is only available for SDK version 2024.3 or later. Latest SDK version is available on the <a href=\"https:\/\/imperix.com\/downloads\/\">download page<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"downloads\"><span class=\"ez-toc-section\" id=\"Downloads\"><\/span>Downloads<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The Simulink model running in the CPU and the Vivado project to generate the FPGA bitstream are available below.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p class=\"has-text-align-center\">Simulink model<\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/RTDS_MMC_SFP_Simulink.zip\" class=\"wp-block-file__button wp-element-button\" download>RTDS_MMC_SFP_Simulink.zip<\/a><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p class=\"has-text-align-center\">Vivado project generation scripts<\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/RTDS_MMC_SFP_gen_script.zip\" class=\"wp-block-file__button wp-element-button\" download>RTDS_MMC_SFP_gen_script.zip<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">As dead-times are not introduced in the gating signals and relays are not considered, the provided closed-loop control is <strong>not meant to run with real power modules<\/strong>. To control power modules, please refer to the original control model from the <a href=\"https:\/\/imperix.com\/doc\/example\/mmc-converter\">AN009<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Results\"><\/span>Results<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>As shown in Fig. 3, the closed-loop control generates a three-phase output current, while controlling the bus current and the submodule voltages. The submodule voltages are limited to 63.5V (or kV, if configured in kV\/kA on the RTDS side) in the RTDS, explaining why the bus voltage has been intentionally reduced to 100V.<\/p>\n\n\n\n<p>All measurements and real-time data are available to the user in the CPU and the FPGA. The section <a href=\"#simulink-model\">Simulink model<\/a> describes which SBI registers to consider for accessing the received quantities. In the FPGA, dedicated registers can be directly accessed at the output of the RTDS MMC driver.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"613\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Cockpit_RTDS_MMC-1024x613.png\" alt=\"Cockpit interface when controlling a 4-SM MMC through an SFP communication.\" class=\"wp-image-31684\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Cockpit_RTDS_MMC-1024x613.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Cockpit_RTDS_MMC-300x180.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Cockpit_RTDS_MMC-768x460.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Cockpit_RTDS_MMC-1536x920.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Cockpit_RTDS_MMC-2048x1227.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Fig. 3 &#8211; Cockpit interface when controlling a 4-SM MMC.<\/figcaption><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Provided-files\"><\/span>Provided files<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"simulink-model\"><span class=\"ez-toc-section\" id=\"Simulink-model\"><\/span>Simulink model<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>In order to validate the proper communication between the MMC model running on the RTDS GTSOC V2, a simple closed-loop control model \u2013 depicted in Fig. 4 \u2013 is provided. This model is largely inspired by the <a href=\"https:\/\/imperix.com\/doc\/example\/mmc-converter\">AN009<\/a>, where more information about the operation principles of the MMC converter and controller is available.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"582\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Screenshot-2024-12-12-170732-1024x582.png\" alt=\"Simulink model running in the B-Box RCP (or B-Board PRO), based on the SFP communication.\" class=\"wp-image-31613\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Screenshot-2024-12-12-170732-1024x582.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Screenshot-2024-12-12-170732-300x170.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Screenshot-2024-12-12-170732-768x436.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/Screenshot-2024-12-12-170732.png 1477w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Fig. 4 &#8211; Simulink model running in the <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a> (or <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a>).<\/figcaption><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\">From ADC to SBI<\/h4>\n\n\n\n<p>Unlike the model from the <a href=\"https:\/\/imperix.com\/doc\/example\/mmc-converter\">AN009<\/a>, measured quantities are not accessed via classical ADC, but rather received from the RTDS simulator through the SFP communication. To achieve a high rate and reduce the CPU load, the reception mechanism is fully handled by the FPGA.<\/p>\n\n\n\n<p>Imperix provides an easy way to transfer data between the CPU and the FPGA: the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> and <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> registers. As explained in <a href=\"#vivado-project\">Vivado project<\/a> section, <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> correspond to FPGA registers that can be read from the CPU, while <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> correspond to FPGA registers that can be written from the CPU.<\/p>\n\n\n\n<p>Once a frame is received, the data is extracted by the driver and automatically routed to SBI registers. To access it from the Simulink model, <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> blocks are instantiated, as shown in Fig. 5. The mapping between the SBI and the received quantities can be found in the <a href=\"#sbi-mapping\">SBI mapping<\/a> section. Also, as quantities are assumed to be received as 16.16 fixed-point data (i.e. it  can be configured from the RTDS GTSOC V2), an additional gain of (0.5)^16 is inserted after they are interpreted as integers.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"293\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/adc_to_sbi-1024x293.png\" alt=\"\" class=\"wp-image-31861\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/adc_to_sbi-1024x293.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/adc_to_sbi-300x86.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/adc_to_sbi-768x220.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/adc_to_sbi-1536x440.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/12\/adc_to_sbi-2048x586.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Fig. 5 &#8211; Parallel between the acquisition mechanism of the <a href=\"https:\/\/imperix.com\/doc\/example\/mmc-converter\">AN009<\/a> model and the current model using SBI.<\/figcaption><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"sbi-mapping\">SBI mapping<\/h4>\n\n\n\n<p>Data received from the RTDS GTSOC V2 through the SFP communication can be accessed via the following SBI registers. The mapping of the SBI to the received quantities is available here below:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><\/tr><tr><td>0:1<\/td><td>Arm 1, voltage<\/td><td>18:19<\/td><td>Arm 4, voltage<\/td><\/tr><tr><td>2:3<\/td><td>Arm 1, current<\/td><td>20:21<\/td><td>Arm 4, current<\/td><\/tr><tr><td>4:5<\/td><td>Arm 1, valves voltage<\/td><td>22:23<\/td><td>Arm 4, valves voltage<\/td><\/tr><tr><td>6:7<\/td><td>Arm 2, voltage<\/td><td>24:25<\/td><td>Arm 5, voltage<\/td><\/tr><tr><td>8:9<\/td><td>Arm 2, current<\/td><td>26:27<\/td><td>Arm 5, current<\/td><\/tr><tr><td>10:11<\/td><td>Arm 2, valves voltage<\/td><td>28:29<\/td><td>Arm 5, valves voltage<\/td><\/tr><tr><td>12:13<\/td><td>Arm 3, voltage<\/td><td>30:31<\/td><td>Arm 6, voltage<\/td><\/tr><tr><td>14:15<\/td><td>Arm 3, current<\/td><td>32:33<\/td><td>Arm 6, current<\/td><\/tr><tr><td>16:17<\/td><td>Arm 3, valves voltage<\/td><td>34:35<\/td><td>Arm 6, valves voltage<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><\/tr><tr><td>36:47<\/td><td>Passthroughs 1-3<\/td><td>48:59<\/td><td>Passthroughs 4-6<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><\/tr><tr><td>60:61, 62:63, 64:65, 66:67<\/td><td>Arm 1, SM voltage: Vsm_A0, Vsm_A1, Vsm_A2, Vsm_A3<\/td><td>84:85, 86:87, 88:89, 90:91<\/td><td>Arm 4, SM voltage:<br>Vsm_B4, Vsm_B5, Vsm_B6, Vsm_B7<\/td><\/tr><tr><td>68:69, 70:71, 72:73, 74:75<\/td><td>Arm 2, SM voltage:<br>Vsm_A4, Vsm_A5, Vsm_A6, Vsm_A7<\/td><td>92:93, 94:95, 96:97, 98:99<\/td><td>Arm 5, SM voltage:<br>Vsm_C0, Vsm_C1, Vsm_C2, Vsm_C3<\/td><\/tr><tr><td>76:77, 78:79, 80:81, 82:83<\/td><td>Arm 3, SM voltage:<br>Vsm_B0, Vsm_B1, Vsm_B2, Vsm_B3<\/td><td>100:101, 102:103, 104:105, 106:107<\/td><td>Arm 6, SM voltage:<br>Vsm_C4, Vsm_C5, Vsm_C6, Vsm_C7<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><td><strong>SBI<\/strong><\/td><td><strong>Quantity<\/strong><\/td><\/tr><tr><td>108:111<\/td><td>Arm 1, SM1-4 status<\/td><td>120:123<\/td><td>Arm 4, SM1-4 status<\/td><\/tr><tr><td>112:115<\/td><td>Arm 2, SM1-4 status<\/td><td>124:127<\/td><td>Arm 5, SM1-4 status<\/td><\/tr><tr><td>116:119<\/td><td>Arm 3, SM1-4 status<\/td><td>128:131<\/td><td>Arm 6, SM1-4 status<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>Note that most of the received quantities are 32-bit wide, which explains why they extend over two 16-bit registers. In particular, voltages and currents are assumed to be encoded as fixed-point 16.16 data. Status are 16-bit words, so each 16-bit SBI register corresponds to one submodule status.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"vivado-project\"><span class=\"ez-toc-section\" id=\"Vivado-project\"><\/span>Vivado project<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The Vivado block design of the current example is provided below, in Fig. 6. Next sections briefly introduce the main parts of the design, and how to generate the bitstream \u2013 running in the B-Box FPGA \u2013 from the RTDS_MMC_SFP_gen_script.zip file provided in the <a href=\"#downloads\">Downloads<\/a> section.<\/p>\n\n\n\n<p>A detailed description of the RTDS MMC driver ports can be found in the driver source file (cf. RTDS_MMC_SFP_gen_script.zip &gt; usr_repo\/RTDS_MMC.vhd).<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"656\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/vivado-project-1024x656.png\" alt=\"Vivado block design.\" class=\"wp-image-31505\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/vivado-project-1024x656.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/vivado-project-300x192.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/vivado-project-768x492.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/vivado-project-1536x984.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/vivado-project.png 1935w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Fig. 6 &#8211; Vivado block design. <br><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/PN122_vivado-project.pdf\">Click here<\/a> to open as a PDF.<\/figcaption><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">VHDL modules description<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td class=\"has-text-align-center\" data-align=\"center\">core_state_decoder<\/td><td>Reads the core state and detects if the PWM are enabled by the user in Cockpit.<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">gen_complementary<\/td><td>Spies the PWM signals transmitted to the optical outputs and generates the complementary PWM signals for the RTDS MMC driver. This block can be discarded if the modulators already output complementary PWM signals (configured as &#8216;dual&#8217; in Simulink\/PLECS). Produces a 0-vector if PWM are not enabled.<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">RTDS_MMC<\/td><td>Main driver. Takes the PWM signals as input (along with the optional fast discharge and deactivate signals), builds the 8-bit submodule firing words and transmits them to the RTDS GTSOC V2. It also receives frames from the RTDS GTSOC V2, unpacks them and updates the corresponding registers of the RTDS_data interface. The RTDS_data interface can be extended to directly access any data of interest from the FPGA. Please refer to the RTDS datasheet for more details about the exchanged data.<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">AXI4-Stream FIFO<\/td><td>Used for the clock domain crossing between the main FPGA clock (250MHz) and the Aurora clock domain (50MHz).<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">Aurora 8B\/10B<\/td><td>Xilinx Aurora 8B\/10B IP. The user manual is available <a href=\"https:\/\/docs.amd.com\/viewer\/book-attachment\/9rdQMdIWQda4Ze2zkHXhmg\/mUYbTLC7Un05ekuU2G7cig\">here<\/a>.<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">reg_32b_to_16b_66<\/td><td>Splits each 32-bit input (here, 66 inputs) into two 16-bit outputs (here, 132 outputs), to comply with the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development#sbio-modules\">SBIO registers block<\/a> 16-bit registers.<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">sbio_256_registers<\/td><td>Extended version (up to 256 registers) of the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development#sbio-modules\">SBIO registers block<\/a>. This block contains input registers that can be read from the CPU (<a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a>), and output registers that can be written from the CPU (<a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a>). It is therefore used to make the data received from the RTDS available to the CPU.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">How to generate the design and bitstream<\/h4>\n\n\n\n<p>The RTDS_MMC_SFP_gen_script.zip folder, provided in the <a href=\"#downloads\">Downloads<\/a> section above, contains all the necessary files to reproduce the design and generate the bitstream locally. It contains:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>the generation scripts (Batch file, TCL script)<\/li>\n\n\n\n<li>the source files (VHDL files)<\/li>\n<\/ul>\n\n\n\n<p>To generate the design using the script, download the RTDS_MMC_SFP_gen_script.zip file and follow the steps described in <a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication#vivado-project\">PN118\/Vivado project<\/a>. Before executing the <em>.bat<\/em> file, additionally copy the <em>usr_repo<\/em> folder within the project directory, as shown below:<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter\"><img loading=\"lazy\" decoding=\"async\" width=\"616\" height=\"198\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-12.png\" alt=\"usr_repo folder must be copied within the project directory.\" class=\"wp-image-31518\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-12.png 616w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-12-300x96.png 300w\" sizes=\"auto, (max-width: 616px) 100vw, 616px\" \/><figcaption class=\"wp-element-caption\">Fig. 7 &#8211; <em>usr_repo<\/em> folder within the project directory.<\/figcaption><\/figure>\n<\/div>\n\n\n<p>In Vivado, once the project is ready, click on &#8216;Generate Bitstream&#8217; to launch the bitstream generation. The warning about the signal size mismatchs can be ignored.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">How to assign a different SFP port<\/h4>\n\n\n\n<p>In the provided Vivado project, the SFP communication uses port SFP2 (DOWN 1). To use SFP0 (UP) and\/or SFP1 (DOWN 0) instead:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>In the Vivado block design, double-click on the IX IP.<\/li>\n\n\n\n<li>In the IX IP configuration panel, select options to reflect the desired configuration, as depicted in Fig. 8. Click &#8216;OK&#8217; to apply the changes. As unconnected tx{p,n} and rx{p,n} IX IP ports could lead to Vivado warnings or issues, note that <em>only<\/em> the required SFP port(s) must be checked.<\/li>\n\n\n\n<li>Connect the tx{p,n} and rx{p,n} IX IP port to the corresponding ports of the Aurora IP.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"828\" height=\"617\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-14.png\" alt=\"\" class=\"wp-image-31578\" style=\"width:437px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-14.png 828w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-14-300x224.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/11\/image-14-768x572.png 768w\" sizes=\"auto, (max-width: 828px) 100vw, 828px\" \/><figcaption class=\"wp-element-caption\"><br>Fig. 8 &#8211; IX IP configuration panel with RealSync disabled on SFP0 (UP).<\/figcaption><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\">How to change the number of submodules<\/h4>\n\n\n\n<p>The RTDS MMC driver provided in the Vivado project is meant to be easily extendable. It however requires minimal experience in FPGA design, typically with Vivado and VHDL basics.<\/p>\n\n\n\n<p>To increase the number of submodules per arm, e.g. to N=12, the following steps are recommended:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Make sure that the modulator(s) in the controller can produce the Nx6 PWM signals.<\/li>\n\n\n\n<li>In the following VHDL files, set the N generic to the desired value: <em>RTDS_MMC.vhd<\/em>, <em>RTDS<\/em>_<em>rtds_firing_words.vhd<\/em>, <em>RTDS_emitter.vhd<\/em>, <em>gen_complementary.vhd<\/em>. The latter can be discarded if the modulator already outputs the complementary signals.<\/li>\n\n\n\n<li>Route the PWM signals generated by the modulator to the &#8216;pwm&#8217; input of the RTDS MMC driver.<\/li>\n<\/ul>\n\n\n\n<p>If the capacitor voltages and submodule status must be accessed, the following steps are recommended:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>In <em>RTDS_MMC.vhd<\/em>, add the missing outputs to the RTDS MMC driver (typically,  add <em>B_cap_v_sm_XX_leg_X <\/em>and <em>C_sm_XX_XX_leg_X <\/em>outputs). Make sure that they are connected to the right serial-to-parallel module.<\/li>\n\n\n\n<li>In <em>reg_32b_to_16b_66.vhd<\/em>, extend the module inputs and outputs to match the desired number.<\/li>\n\n\n\n<li>If necessary, use an SBIO interconnect to instantiate up to 4 SBIO registers blocks and therefore increase the number of available SBIO registers to 1024. The <em>sbio_interconnect.vhd<\/em> is available in the <em>hdl <\/em>folder. Add it to the project sources to be able to insert it in the design.<\/li>\n\n\n\n<li>Do not forget to add the corresponding SBI blocks in the CPU model accordingly.<\/li>\n<\/ul>\n\n\n\n<p>Additional modifications in the reception mechanism (typ. in <em>RTDS_serial_to_parallel_{B,C}.vhd<\/em> and <em>RTDS_MMC_router.vhd<\/em>) are required if the targeted number of submodules exceeds 20.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Going-further\"><\/span>Going further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>As mentioned, this <a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">introduction to FPGA-based Aurora communication<\/a> presents the Aurora 8B\/10B protocol and implements an Aurora 8B\/10B loopback example.<\/p>\n\n\n\n<p>The page <a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">high-level synthesis for FPGA<\/a>&nbsp;developments shows how automated code generation tools such as&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a>&nbsp;and&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a>&nbsp;can be used to facilitate the development of FPGA modules. Like the Aurora 8B\/10B IP, they use AXI4-Streams to move data around.<\/p>\n\n\n\n<p>The <a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development on imperix controllers<\/a>&nbsp;summarizes all the other FPGA-related pages.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>As introduced in PN118, SFP communication constitutes a convenient way to interconnect devices. Widely used, it offers an efficient layer on which protocols such as&#8230;<\/p>\n","protected":false},"author":17,"featured_media":31948,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[],"software-environments":[106,103],"provided-results":[108,109],"related-products":[50,31,32,166,110],"guidedreadings":[],"tutorials":[174],"user-manuals":[],"coauthors":[82],"class_list":["post-31245","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","software-environments-fpga","software-environments-matlab","provided-results-experimental","provided-results-hil","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-rcp-3-0","related-products-tpi","tutorials-sfp-communication-with-third-party-devices"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - 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