{"id":3152,"date":"2021-06-02T11:37:17","date_gmt":"2021-06-02T11:37:17","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3152"},"modified":"2026-04-16T08:48:43","modified_gmt":"2026-04-16T08:48:43","slug":"getting-started-with-fpga-control-development","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development","title":{"rendered":"Getting started with FPGA programming"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Getting-started-with-FPGA-programming\" >Getting started with FPGA programming<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Installing-Vivado\" >Installing Vivado<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Creating-the-Vivado-FPGA-sandbox-template\" >Creating the Vivado FPGA sandbox template<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Generating-the-bitstream-and-loading-it-to-the-target\" >Generating the bitstream and loading it to the target<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Opening-a-project-provided-by-imperix\" >Opening a project provided by imperix<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Going-further-with-FPGA-programming\" >Going further with FPGA programming<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Advanced-topics\" >Advanced topics<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Automated-code-generation-tools\" >Automated code generation tools<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\/#Examples\" >Examples<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p>While the standard imperix workflow utilises the <a href=\"https:\/\/imperix.com\/software\/acg-sdk\/\">ACG SDK<\/a> (for Simulink or PLECS ) or the <a href=\"https:\/\/imperix.com\/software\/cpp-sdk\/\">CPP SDK<\/a> (for C\/C++) to program the controller&#8217;s CPU, advanced applications may require more flexibility. To that end, imperix offers the possibility to directly <strong>program the controller&#8217;s FPGA<\/strong>, which extends the range of implementable functions.<\/p>\n\n\n\n<p>Programming the FPGA of imperix controllers involves instantiating the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">imperix firmware IP<\/a> (which contains the imperix proprietary FPGA logic) within AMD Vivado. The surrounding programmable logic, known as the <strong>FPGA sandbox<\/strong>, can then be edited to suit the application.<\/p>\n\n\n\n<p>This getting started guide covers:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The configuration of the AMD Vivado environment<\/li>\n\n\n\n<li>The creation of the Vivado FPGA sandbox template.<\/li>\n\n\n\n<li>The generation and deployment of a bitstream to the target controller, via an &#8220;Hello World&#8221; example.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-success\" role=\"alert\">On imperix devices with a valid ACG or CPP SDK license, FPGA programmability comes at <strong>no additional cost<\/strong>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Getting-started-with-FPGA-programming\"><\/span>Getting started with FPGA programming<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Installing-Vivado\"><\/span>Installing Vivado<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The first step to start editing the FPGA consists in installing Vivado, which is available for free as the ML Standard edition. The recommended version is <strong>Vivado 2023.2<\/strong>, matching the internal development environment at imperix, although newer releases are also supported. It can be acquired through the <em>AMD Unified Installer<\/em> available on the <a href=\"https:\/\/www.xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/vitis.html\">AMD download page<\/a>.<\/p>\n\n\n\n<p>During installation, the correct device support must be selected depending on the target:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Zynq-7000<\/strong> support for Gen 3 devices (<a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<sup>3.0<\/sup><\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/power-inverter-controller\/\">B-Box Micro<\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a>, <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">TPI8032<\/a>)<\/li>\n\n\n\n<li><strong>Zynq UltraScale+ MPSoC<\/strong> support for Gen 4 devices (<a href=\"https:\/\/imperix.com\/products\/control\/rcp-controller\/\">B-Box 4<\/a>)<\/li>\n<\/ul>\n\n\n\n<p>The detailed Vivado installation procedure is available in <a href=\"https:\/\/imperix.com\/doc\/help\/vivado-design-suite-installation?currentThread=getting-started-with-fpga-programming\">PN168<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Unless explicitly stated otherwise, the FPGA development documentation and procedures apply to both controller generations.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Creating-the-Vivado-FPGA-sandbox-template\"><\/span>Creating the Vivado FPGA sandbox template<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The FPGA sandbox template source files are available on the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox?currentThread=getting-started-with-fpga-programming\">FPGA sandbox download page<\/a>. Provided as a ZIP archive, they include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>imperix firmware IP<\/strong>, documented in <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">PN116<\/a>.<\/li>\n\n\n\n<li>The <strong>create_project.bat<\/strong> script automates the creation of the ready-to-use Vivado sandbox template project.<\/li>\n\n\n\n<li><strong>VHDL helper modules<\/strong> to make FPGA development easier (AXI4-stream interfaces, carrier-based modulator, etc.)<\/li>\n<\/ul>\n\n\n\n<p>The FPGA sandbox template project creation procedure is the following:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Download the source files <strong>FPGA_Sandbox_template_*.zip<\/strong> archive.<\/li>\n\n\n\n<li>Unzip it and save the content somewhere on the PC.<\/li>\n\n\n\n<li>Rename the folder to something more explicit.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"666\" height=\"207\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-31.png\" alt=\"\" class=\"wp-image-39929\" style=\"aspect-ratio:3.2174102285092494;width:624px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-31.png 666w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-31-300x93.png 300w\" sizes=\"auto, (max-width: 666px) 100vw, 666px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"4\" class=\"wp-block-list\">\n<li>Open <strong>scripts\/create_project.bat<\/strong> using a text editor.<\/li>\n\n\n\n<li>Set the <code>vivado_path<\/code> variable to match the Vivado version installed on the PC.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"451\" height=\"141\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-32.png\" alt=\"\" class=\"wp-image-39930\" style=\"width:477px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-32.png 451w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-32-300x94.png 300w\" sizes=\"auto, (max-width: 451px) 100vw, 451px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"6\" class=\"wp-block-list\">\n<li>Double-click on <strong>scripts\/create_project.bat<\/strong>.<br>If a Windows Defender SmartScreen warning appears, click <strong>More info<\/strong> and select <strong>Run anyway<\/strong> to proceed.<\/li>\n\n\n\n<li>Enter a project name and click Enter.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"655\" height=\"229\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-33.png\" alt=\"\" class=\"wp-image-39931\" style=\"aspect-ratio:2.860421886365473;width:529px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-33.png 655w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-33-300x105.png 300w\" sizes=\"auto, (max-width: 655px) 100vw, 655px\" \/><\/figure>\n<\/div>\n\n\n<p>A new instance of Vivado will launch and execute the Tcl script to reconstruct the sandbox template project environment from scratch. The project contains the mandatory <strong>imperix firmware IP<\/strong> <strong>(IXIP)<\/strong> and the optional <strong>AXI4-Stream interface<\/strong>&nbsp;(<strong>ix_axis_interface<\/strong>). They are described below.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"632\" height=\"494\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-298.png\" alt=\"\" class=\"wp-image-43720\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-298.png 632w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-298-300x234.png 300w\" sizes=\"auto, (max-width: 632px) 100vw, 632px\" \/><figcaption class=\"wp-element-caption\">imperix firmware IP (IXIP)<\/figcaption><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\">\n<p>The <strong>imperix firmware IP<\/strong> contains the imperix proprietary FPGA logic and provides various interfaces enabling the user to retrieve ADC measurement results, exchange data with the CPU through the SBIO_BUS, drive the PWM from the sb_pwm port, etc.<\/p>\n\n\n\n<p>Further documentation is available in the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">product guide<\/a> of the imperix firmware IP.<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"731\" height=\"798\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-307.png\" alt=\"\" class=\"wp-image-43734\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-307.png 731w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-307-275x300.png 275w\" sizes=\"auto, (max-width: 731px) 100vw, 731px\" \/><figcaption class=\"wp-element-caption\">AXI4-Stream interface (ix_axis_interface)<\/figcaption><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\">\n<p>The template includes a <strong>AXI4-Stream interface<\/strong> to enable interconnection with a broad range of Xilinx provided IPs&nbsp;or to user-made algorithms developed using High-Level Synthesis (HLS) tools such as&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a> or&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a>.<\/p>\n\n\n\n<p>This optional interface was made specifically to facilitate implementing <strong>control algorithm in FPGA<\/strong>. It can be deleted from the project without impacting the core functionality of the imperix firmware IP.<\/p>\n\n\n\n<p>Documentation regarding the AXI4-Stream interface is available in <a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga?currentThread=getting-started-with-fpga-programming\">PN126<\/a> (retrieving ADC measurements) and in <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga?currentThread=getting-started-with-fpga-programming\">PN128<\/a> (exchanging data between CPU and FPGA).<\/p>\n<\/div>\n<\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Generating-the-bitstream-and-loading-it-to-the-target\"><\/span>Generating the bitstream and loading it to the target<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>An Hello World example is used to illustrate how to add logic to the template, generate a bitstream and deploy it to the target controller. In this example, the raw 16-bit ADC measurement is retrieved from the FPGA and transferred to the CPU using an SBI register:<\/p>\n\n\n\n<p>First, create the sandbox template.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>Download the sandbox sources<\/strong> from the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox?currentThread=getting-started-with-fpga-programming\">FPGA sandbox download page<\/a>.<\/li>\n\n\n\n<li>Follow the procedure above to <strong>create the Vivado sandbox template project<\/strong>.<\/li>\n<\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"734\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-309-1024x734.png\" alt=\"\" class=\"wp-image-43739\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-309-1024x734.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-309-300x215.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-309-768x551.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-309.png 1252w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">The imperix FPGA sandbox template<\/figcaption><\/figure>\n\n\n\n<p>Then, remove the AXI4-Stream interface since it is not used in this example.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Click on <strong>ix_axis_interface<\/strong>.<\/li>\n\n\n\n<li>Press <strong>Delete<\/strong>.<\/li>\n<\/ol>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"874\" height=\"537\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-310.png\" alt=\"\" class=\"wp-image-43740\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-310.png 874w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-310-300x184.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-310-768x472.png 768w\" sizes=\"auto, (max-width: 874px) 100vw, 874px\" \/><figcaption class=\"wp-element-caption\">The FPGA sandbox template with the AXI4-Stream interface removed<\/figcaption><\/figure>\n\n\n\n<p>Add an <strong>sbio_registers<\/strong> module to the design. This helper module allows exchanging 16-bit registers with the CPU using the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> (SandBox Input) and <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> (SandBox Output) blocks. It is further documented in <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga?currentThread=getting-started-with-fpga-programming\">PN128<\/a> (exchanging data between CPU and FPGA).<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Navigate to <strong>File<\/strong> \u2192 <strong>Add Sources&#8230;<\/strong><\/li>\n\n\n\n<li>Select <strong>Add or create design sources<\/strong>. Click <strong>Next<\/strong>.<\/li>\n\n\n\n<li>Click <strong>Add Files<\/strong>, select <strong>sbio_registers.vhd<\/strong> from the <code>hdl<\/code> folder and click <strong>Finish<\/strong>.<\/li>\n\n\n\n<li>Drag and drop <strong>sbio_registers<\/strong> from the Design Sources folder to the block design.<\/li>\n\n\n\n<li>Connect it to the IXIP as shown on the image below.<\/li>\n<\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"510\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-313-1024x510.png\" alt=\"\" class=\"wp-image-43743\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-313-1024x510.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-313-300x149.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-313-768x383.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-313.png 1114w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Connecting the sbio_registers module to the imperix IP<\/figcaption><\/figure>\n\n\n\n<p>Connect the ADC measurement of channel 0 to the SBI register 0.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Expand the <strong>ADC <\/strong>and <strong>SBI <\/strong>interfaces.<\/li>\n\n\n\n<li>Connect <strong>ADC_reg_00<\/strong> to <strong>SBI_reg_00<\/strong>.<\/li>\n<\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"537\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-314-1024x537.png\" alt=\"\" class=\"wp-image-43744\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-314-1024x537.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-314-300x157.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-314-768x403.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-314.png 1107w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Connecting the ADC measurement to a SBI register<\/figcaption><\/figure>\n\n\n\n<p>Generate the <strong>bitstream<\/strong>, which is the &#8220;compiled&#8221; result of the FPGA design. It contains the configuration mapping that will be loaded onto the target controller to define its hardware logic.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li> Navigate to <strong>Flow navigator<\/strong> (left bar)\u2192 <strong>PROGRAM AND DEBUG<\/strong>.<\/li>\n\n\n\n<li>Click <strong>Generate Bitstream<\/strong>.<\/li>\n<\/ol>\n\n\n\n<p>This will launch the synthesis, implementation, and bitstream generation processes. Depending on the complexity of the design and the computer&#8217;s performance, this may take anywhere from a few minutes to over half an hour.<\/p>\n\n\n\n<p>Once the bitstream is generated, verify that it meets the timing requirements.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Navigate <strong>Window<\/strong> \u2192 <strong>Project Summary<\/strong>.<\/li>\n\n\n\n<li>Verify that the <strong>Timing<\/strong> numbers are all positive.<\/li>\n<\/ol>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"266\" height=\"157\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-325.png\" alt=\"\" class=\"wp-image-44710\"\/><figcaption class=\"wp-element-caption\">Timing requirements are met \u2705<\/figcaption><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"291\" height=\"157\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-326.png\" alt=\"\" class=\"wp-image-44711\"\/><figcaption class=\"wp-element-caption\">Timing requirements are violated \u274c<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\"><strong>Always verify that the generated bitstream meets all timing requirements.<\/strong><br>Failure to achieve timing closure may result in unpredictable FPGA firmware behavior. For best practices, refer to the <a href=\"https:\/\/docs.xilinx.com\/r\/en-US\/ug949-vivado-design-methodology\/Timing-Closure\" target=\"_blank\" rel=\"noreferrer noopener\">AMD Xilinx design methodology guide<\/a>.<\/div>\n\n\n\n<p>If the timing requirements are met, load the customized bitstream onto the target.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Click on&nbsp;<strong>File&nbsp;<\/strong>\u2192&nbsp;<strong>Export&nbsp;<\/strong>\u2192&nbsp;<strong>Export Bitstream File<\/strong>&nbsp;to save the bitstream on the computer.<\/li>\n\n\n\n<li>From <a href=\"https:\/\/imperix.com\/software\/cockpit\">Cockpit<\/a>, navigate to <strong>TARGETS<\/strong> \u2192 <strong>Target configuration<\/strong>.<\/li>\n\n\n\n<li>In the&nbsp;<strong>FPGA bitstream<\/strong>&nbsp;area, click on&nbsp;<strong>Browse&nbsp;<\/strong>and load the new bitstream on the target.<\/li>\n\n\n\n<li>Power cycle the target for the customized bitstream to be loaded.<\/li>\n<\/ol>\n\n\n\n<figure class=\"wp-block-image\"><a class=\"firelight-lightbox fancybox image\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-8-1024x488.png\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"488\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-8-1024x488.png\" alt=\"\" class=\"wp-image-39944\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-8-1024x488.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-8-300x143.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-8-768x366.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-8.png 1296w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><figcaption class=\"wp-element-caption\">Cockpit target configuration<\/figcaption><\/figure>\n\n\n\n<p>As illustrated below, the bitstream is tested by comparing the result from an <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC<\/a> block (configured with a sensitivity of 1.0 and and offset of 0.0) with the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> block. Observing both signals in the Cockpit Scope module confirms that both waveforms have the same shape, but their amplitude differs. The difference exists because the scaling required to convert the <strong>int16<\/strong> data into physical units has not yet been applied. This conversion is documented in <a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga?currentThread=getting-started-with-fpga-programming\">PN126<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"228\" height=\"160\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-319.png\" alt=\"\" class=\"wp-image-43749\"\/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"469\" height=\"348\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-317.png\" alt=\"\" class=\"wp-image-43747\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-317.png 469w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-317-300x223.png 300w\" sizes=\"auto, (max-width: 469px) 100vw, 469px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"starting-from-generation-scripts\"><span class=\"ez-toc-section\" id=\"Opening-a-project-provided-by-imperix\"><\/span>Opening a project provided by imperix<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Sharing Vivado projects often leads to issues like missing file references or version mismatches. To prevent these errors, imperix provides examples as Tcl scripts. These scripts contain the necessary commands to automatically reconstruct the project on any machine. This section shows the process of open and reconstructing Vivado projects provided by imperix.<\/p>\n\n\n\n<p>The <strong>aurora_ix_plexim_gen_scripts.zip<\/strong> archive from the page <a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-plexim-via-sfp\">Aurora link with Plexim via SFP<\/a> is used as an example for the following procedure. It contains two folders:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>hdl <\/strong>folder contains the source files specific to the example.<\/li>\n\n\n\n<li>The <strong>scripts<\/strong> folder contains the project creation scripts.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"371\" height=\"217\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-323.png\" alt=\"\" class=\"wp-image-43811\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-323.png 371w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-323-300x175.png 300w\" sizes=\"auto, (max-width: 371px) 100vw, 371px\" \/><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"369\" height=\"217\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-324.png\" alt=\"\" class=\"wp-image-43812\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-324.png 369w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-324-300x176.png 300w\" sizes=\"auto, (max-width: 369px) 100vw, 369px\" \/><\/figure>\n<\/div>\n<\/div>\n\n\n\n<p>The procedure to reconstruct the Vivado project is the following:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Download the source files <strong>FPGA_Sandbox_template_*.zip <\/strong>archive from the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox?currentThread=getting-started-with-fpga-programming\">download page<\/a>. <\/li>\n\n\n\n<li>Unzip it and save the content somewhere on the PC.<\/li>\n\n\n\n<li>Rename the folder to something more explicit.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"666\" height=\"207\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-31.png\" alt=\"\" class=\"wp-image-39929\" style=\"width:462px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-31.png 666w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-31-300x93.png 300w\" sizes=\"auto, (max-width: 666px) 100vw, 666px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"4\" class=\"wp-block-list\">\n<li>Download the project-specific generation scripts on the page of interest in the Knowledge Base (e.g., <strong>aurora_ix_plexim_gen_scripts.zip<\/strong> mentioned above).<\/li>\n\n\n\n<li>Unzip it and open it.<\/li>\n\n\n\n<li>Copy-paste the content of each subfolder into the corresponding subfolder of the source files.<br>In this example:\n<ul class=\"wp-block-list\">\n<li>copy the content of <code>...\/hdl\/<\/code> into <code>My_project\/hdl\/<\/code><\/li>\n\n\n\n<li>copy the content of <code>...\/scripts\/<\/code> into <code>My_project\/scripts\/<\/code><\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"297\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-29-1024x297.png\" alt=\"\" class=\"wp-image-39925\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-29-1024x297.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-29-300x87.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-29-768x223.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-29-1536x446.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-29.png 1854w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"7\" class=\"wp-block-list\">\n<li>Open <strong>&lt;source files&gt;\/scripts\/&lt;script_name&gt;.bat<\/strong> using a text editor. Ensure the <code>vivado_path<\/code> variable matches the Vivado version installed on the PC.<\/li>\n<\/ol>\n\n\n\n<p class=\"has-text-align-center\"><br><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-32.png\" alt=\"\"><\/p>\n\n\n\n<ol start=\"7\" class=\"wp-block-list\">\n<li>Double-click on the newly copied <strong>&lt;source files&gt;\/scripts\/&lt;script_name&gt;.bat<\/strong> file. If a Windows Defender SmartScreen warning appears, click <strong>More info<\/strong> and select <strong>Run anyway<\/strong> to proceed.<\/li>\n\n\n\n<li>Enter a project name and click Enter.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"664\" height=\"229\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-30.png\" alt=\"\" class=\"wp-image-39926\" style=\"width:486px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-30.png 664w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/09\/image-30-300x103.png 300w\" sizes=\"auto, (max-width: 664px) 100vw, 664px\" \/><\/figure>\n<\/div>\n\n\n<p>A new instance of Vivado will launch automatically and execute the Tcl scripts to import the HDL sources, configure the IP cores, and reconstruct the project environment from scratch.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Going-further-with-FPGA-programming\"><\/span>Going further with FPGA programming<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The following pages detail essential aspects of FPGA developments on imperix controllers. These include <strong>retrieving ADC conversion results<\/strong> as soon as they are available, directly from within the FPGA, <strong>exchanging data <\/strong>between the application control code running in the CPU and the logic in the FPGA and <strong>driving the PWM output chain<\/strong>, composed of a dead-time generation system and the hardware protection mechanisms.<a href=\"https:\/\/imperix.com\/doc\/help\/simulation-essentials-simulink\"><\/a><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126: Retrieving <strong>ADC measurements<\/strong> from the FPGA<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128: Exchanging data between the <strong>CPU and the FPGA<\/strong><\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127: Driving the<strong> PWM output chain<\/strong><\/a><\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Advanced-topics\"><\/span>Advanced topics<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The following pages cover more advanced topics such as <strong>observing internal FPGA signals <\/strong>during runtime using ILA (Internal Logic Analyzer) for debugging purposes, accessing the <strong>36 user-configurable 3V3 I\/O pins<\/strong>, or the <strong>Gigabit transceivers<\/strong> to implement Aurora communication on the SFP ports.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\">PN129: Using an <strong>ILA<\/strong> to debug an FPGA design<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\">PN179: Accessing the <strong>USR pins<\/strong> in the FPGA sandbox<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">PN118: Example of FPGA-based <strong>Aurora communication<\/strong><\/a><\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Automated-code-generation-tools\"><\/span>Automated code generation tools<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Traditionally, FPGA designs are implemented using HDL languages such as VHDL or Verilog. However, the user can use\u00a0<strong>automated code generation tools<\/strong>\u00a0to design FPGA modules without writing a single line of HDL code.<\/p>\n\n\n\n<p>These tools can be separated into two main categories:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>HDL-level tools<\/strong>, such as<em>\u00a0<\/em><a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\">AMD Vitis Model Composer HDL<\/a> (formerly System Generator, or SysGen) and\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\">MATLAB HDL Coder<\/a>, in which the user can describe their design down to the flip-flop level. These tools are much closer to HDL languages (VHDL or Verilog) and are recommended to implement peripherals such as custom PWM modulators or communication interfaces.<\/li>\n\n\n\n<li><strong>High-Level Synthesis (HLS)<\/strong>\u00a0tools, such as\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">AMD Vitis Model Composer HLS<\/a> (paid Simulink blockset) and\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">AMD Vitis HLS<\/a> (free C++ alternative), are particularly adapted to describe control algorithms using complex data types and math functions.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Only Vitis HLS is free of cost<\/strong>, the other tools require a paid license.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Examples\"><\/span>Examples<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Examples of <strong>FPGA-based control algorithms<\/strong> implemented using <strong>HLS tools<\/strong>:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">TN142:&nbsp;<strong>PI-based current controller<\/strong>&nbsp;for a buck converter<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">TN147: FPGA-based control of a<strong>&nbsp;grid-tied inverter<\/strong><\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-direct-torque-control\">TN133: FPGA-based <strong>Direct Torque Control<\/strong> using Vivado HLS<\/a><\/li>\n<\/ul>\n\n\n\n<p>Examples of <strong>SFP communication<\/strong> with third-party devices using the <strong>Aurora protocol<\/strong>:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-opal-rt-via-sfp?currentThread=sfp-communication-with-third-party-devices\">PN110:&nbsp;<strong>Aurora link with OPAL-RT<\/strong>&nbsp;via SFP<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-plexim-via-sfp?currentThread=sfp-communication-with-third-party-devices\">PN111:&nbsp;<strong>Aurora link with Plexim<\/strong>&nbsp;via SFP<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\">PN122:&nbsp;<strong>SFP communication with an RTDS<\/strong>&nbsp;MMC simulator<\/a><\/li>\n<\/ul>\n\n\n\n<p>Example of <strong>interfaces with external peripherals<\/strong> through the <strong>3V3 USR pins<\/strong>:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-spi-communication-ip\">TN130: FPGA-based <strong>SPI communication<\/strong> IP for A\/D converter<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-delta-sigma-modulator\">TN149: FPGA-based decoder for a <strong>Delta-Sigma modulator<\/strong><\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>While the standard imperix workflow utilises the ACG SDK (for Simulink or PLECS ) or the CPP SDK (for C\/C++) to program the controller&#8217;s CPU,&#8230;<\/p>\n","protected":false},"author":4,"featured_media":39878,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[105,106,103,104],"provided-results":[108],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[141],"coauthors":[70,82],"class_list":["post-3152","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-c-plus-plus","software-environments-fpga","software-environments-matlab","software-environments-plecs","provided-results-experimental","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","user-manuals-getting-started-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - 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