{"id":3160,"date":"2021-06-01T14:18:52","date_gmt":"2021-06-01T14:18:52","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3160"},"modified":"2025-05-07T09:29:21","modified_gmt":"2025-05-07T09:29:21","slug":"xilinx-model-composer","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer","title":{"rendered":"Xilinx Model Composer introduction"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#What-is-the-difference-between-Model-Composer-and-System-Generator\" >What is the difference between Model Composer and System Generator?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Downloading-and-installing-Xilinx-Model-Composer\" >Downloading and installing Xilinx Model Composer<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Typical-workflow-example-for-Xilinx-Model-Composer\" >Typical workflow example for Xilinx Model Composer<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#How-to-launch-Model-Composer\" >How to launch Model Composer?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Design-example-of-a-PI-controller-using-Model-Composer\" >Design example of a PI controller using Model Composer<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Adding-the-Model-Composer-Hub\" >Adding the Model Composer Hub<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Defining-the-IP-input-and-output-ports\" >Defining the IP input and output ports<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Implementing-the-algorithm\" >Implementing the algorithm<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Verifying-the-design-in-simulation\" >Verifying the design in simulation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\/#Generating-an-IP-core-using-Model-Composer\" >Generating an IP core using Model Composer<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p>Model Composer is a Simulink add-on software developed by Xilinx. It is a high-level synthesis (HLS) tool that allows the user to program an FPGA-based algorithm without the need to write code. Thanks to this approach, behavioral simulations can be run prior to code generation, enabling engineers to validate the correctness of their FPGA design very early in the design process.<\/p>\n\n\n\n<p>Since it is directly integrated within the Matlab Simulink environment, Model Composer is fairly easy to use for regular Simulink users. The provided blockset offers numerous elementary blocks and functions that strongly resemble existing Simulink blocks.  Therefore, if users already have a CPU-based model available in Simulink, they can easily build an FPGA model by replacing the Simulink blocks with corresponding Model Composer blocks.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:50%\">\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-178.png\" alt=\"\" class=\"wp-image-3634\" width=\"197\" height=\"190\"\/><figcaption>Simulink blocks<\/figcaption><\/figure><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:50%\">\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-180.png\" alt=\"\" class=\"wp-image-3636\" width=\"180\" height=\"187\"\/><figcaption>Model Composer blocks<\/figcaption><\/figure><\/div>\n<\/div>\n<\/div>\n\n\n\n<p>An alternative to Model Composer is <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Xilinx Vitis HLS<\/a>, a tool that provides the same features but for C++ developers and that is free of charge. As a matter of fact, Model Composer uses Vitis HLS under the hood. Indeed, it first generates C++ code as an intermediary step and then uses Vitis HLS to generate the Vivado IP. Despite this process, the user does not need to be familiar with C++ since everything is handled automatically by Model Composer.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-what-is-the-difference-between-model-composer-and-system-generator\"><span class=\"ez-toc-section\" id=\"What-is-the-difference-between-Model-Composer-and-System-Generator\"><\/span>What is the difference between Model Composer and System Generator?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Model Composer is bundled with <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\">System Generator<\/a>, another FPGA development blockset. System Generator blocks are \u201clower-level\u201d and better suited for architecture-level designs. Typical examples are the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">FPGA-based PWM modulator design<\/a> or the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-spi-communication-ip\">SPI communication controller<\/a>.<\/p>\n\n\n\n<p>Model Composer, however, is an HLS tool. It is therefore tailored for higher-level designs such as control algorithms. It supports AXI4-Stream interfaces (which allow to easily interconnect multiple IP blocks), complex data types, and math functions. The behavior of HLS tools is basically the following: 1) receive input data, 2) execute the algorithm, and 3) outputs results. It means that, unlike <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\">System Generator<\/a>, it is not well suited to fine signal manipulation (such as peripheral signals).<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-downloading-and-installing-xilinx-model-composer\"><span class=\"ez-toc-section\" id=\"Downloading-and-installing-Xilinx-Model-Composer\"><\/span>Downloading and installing Xilinx Model Composer<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Model Composer, along with System Generator, is part of the <strong>Xilinx Add-on for MATLAB &amp; Simulink<\/strong>, which can be bought as an add-on license to Vivado or Vitis. At the time of writing this page, the price is set at $500 for a node-locked license and $700 for a floating license (a free 90 days license is available).<\/p>\n\n\n\n<p>To install the Xilinx Add-on for MATLAB &amp; Simulink, an option must be selected during the installation of Xilinx Vivado System Edition. If Vivado is already installed,  the <em>Vivado Add Design Tools<\/em> program should be used to install the add-on.<\/p>\n\n\n\n<p>Installation instructions are available on the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-blockset-for-simulink\">Installing Xilinx Blockset Add-on for MATLAB &amp; Simulink<\/a> page.<br>More information on the <em>Xilinx Add-on for MATLAB &amp; Simulink<\/em> is available on <a href=\"https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/addon-matlab-simulink.html#buy\">this Xilinx page<\/a>.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-typical-workflow-example-for-xilinx-model-composer\"><span class=\"ez-toc-section\" id=\"Typical-workflow-example-for-Xilinx-Model-Composer\"><\/span>Typical workflow example for Xilinx Model Composer<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This section broadly outlines the main steps required to generate a Vivado IP using Model Composer. It is not its purpose to be exhaustive but rather serves as a guideline. It also provides tips for designs targetting imperix controllers. For more detailed information, the user should refer to the official <a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2020_2\/ug1262-model-composer-user-guide.pdf\">Model Composer User Guide<\/a>.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-how-to-launch-model-composer\"><span class=\"ez-toc-section\" id=\"How-to-launch-Model-Composer\"><\/span>How to launch Model Composer?<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>If <em>Xilinx Add-on for MATLAB &amp; Simulink<\/em> has been successfully installed, a &#8220;Model Composer and System Generator&#8221; shortcut should have been created on the desktop. This program will open a new MATLAB session and load the Model Composer blockset library for Simulink.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">If multiple concurrent MATLAB Simulink installations are present on the computer, Model Composer will launch the latest version of MATLAB Simulink available by default. It can cause problems if the latest version of Simulink is not compatible with System Generator (for instance Model Composer 2020.2 is not compatible with MATLAB R2021a). However, it is possible to manually change which version of MATLAB Simulink System Generator will use as explained in the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-blockset-for-simulink\">installing Xilinx Add-on for Simulink<\/a> page.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-design-example-of-a-pi-controller-using-model-composer\"><span class=\"ez-toc-section\" id=\"Design-example-of-a-PI-controller-using-Model-Composer\"><\/span>Design example of a PI controller using Model Composer<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The sources of the Model Composer example used in this tutorial can be downloaded below. It is a PI-based current controller for a buck converter, based on the algorithm presented on the&nbsp;<a href=\"https:\/\/imperix.com\/doc\/implementation\/basic-pi-control\">PI controller implementation for current control<\/a>&nbsp;technical note. This example will be used as support to illustrate the key points of the Model Composer workflow. <\/p>\n\n\n\n<p>It is highly recommended to read through the <a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">high-level synthesis for FPGA developements<\/a> page first to see how this IP integrates into a complete design. It will help understand some of the choices made, notably regarding the input and output ports.<\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/PN163_Model_Composer_PI.zip\" class=\"wp-block-file__button\" download>Click to download <strong>PN163_Model_Composer_PI<\/strong>.zip<\/a><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-adding-the-model-composer-hub\"><span class=\"ez-toc-section\" id=\"Adding-the-Model-Composer-Hub\"><\/span>Adding the Model Composer Hub<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The first step of any Model Composer design is to add a <em>Model Composer Hub<\/em> which serves to configure the compilation of the design and the IP core generation. From this block, the following should be configured:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>The <strong>Subsystem name<\/strong> specifies the name of the top-level subsystem that will be used to generated the IP<\/li><li>The <strong>Code directory<\/strong> defines where the IP sources will be generated<\/li><li>The <strong>Target <\/strong>should be <em>HLS C++ code<\/em>.  The reason is that Model Composer uses the <em>HLS PIPELINE<\/em> directive which cause problems in a control application such as our. Unfortunately, we have to go through Vitis HLS C++ to disable this directive. This issue is further explained in a section below.<\/li><li>The <strong>Project device<\/strong> should be <em>xc7z030fbg676-3<\/em><\/li><li>The <strong>FPGA clock frequency<\/strong> should be <em>250 MHz<\/em><\/li><li>The <strong>Throughput factor<\/strong> should be <em>1<\/em><\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"484\" height=\"419\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-12.png\" alt=\"\" class=\"wp-image-4530\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-12.png 484w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-12-300x260.png 300w\" sizes=\"auto, (max-width: 484px) 100vw, 484px\" \/><\/figure><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-defining-the-ip-input-and-output-ports\"><span class=\"ez-toc-section\" id=\"Defining-the-IP-input-and-output-ports\"><\/span>Defining the IP input and output ports<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The user can then create a subsystem. In this example, the subsystem is called <em>XMC_PI_floating<\/em> (for Xilinx Model Composer PI using floating-point arithmetic). We&#8217;ll begin by specifying all the input and outputs of the IP. As shown in the screenshot below, the port data types are specified directly in the signal attributes of the <em>Inports <\/em>and <em>Outports<\/em>. We&#8217;ll use the following:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>The parameters coming from the CPU (<code>Il_ref<\/code>, <code>Kp <\/code>and <code>Ki<\/code>) are set to <em>single<\/em>.<\/li><li>The inputs <code>Il_raw<\/code>, <code>Vin_raw <\/code>and <code>Vout_raw<\/code> will be directly connected to the ADC interfaces and therefore must be set as <em>int16<\/em>.<\/li><li>The input <code>Ts <\/code>is a <em>uint32 <\/em>value holding the sampling time in nanoseconds.<\/li><li>The input <code>CLOCK_period <\/code>is a <em>uint16 <\/em>value representing the PWM period in ticks.<\/li><li>The output <code>duty_cycle_ticks <\/code>is a <em>uint16 <\/em>value that will be connected to the PWM IP.<\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-16.png\" alt=\"\" class=\"wp-image-4534\" width=\"565\" height=\"574\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-16.png 565w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-16-295x300.png 295w\" sizes=\"auto, (max-width: 565px) 100vw, 565px\" \/><\/figure><\/div>\n\n\n\n<p>We then add an Interface Spec block that specifies the IP core interface protocols. We use the following configuration:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li><strong>Function Protocol<\/strong><ul><li>We set the Function Protocol Mode to <em>No block-level I\/O protocol<\/em>. We&#8217;ll use port-level protocol instead to tell the IP when it has to process data.<\/li><\/ul><\/li><li><strong>Input ports<\/strong><ul><li>After the user CPU code start, the <code>CLOCK_period <\/code>input is constant. Thus, its mode is set to <em>No protocol<\/em>.<\/li><li>All the other inputs use the <em>AXI4-Stream<\/em> protocol.<\/li><\/ul><\/li><li><strong>Output ports<\/strong><ul><li>The <code>duty_cycle_ticks<\/code> output uses the <em>Valid Port<\/em> mode. As shown on the very last image of this page, it will generate an additionnal &#8220;valid&#8221; port <code>duty_cycle_ticks_ap_vld<\/code> indicating when the <code>duty_cycle_ticks <\/code>can be read.<\/li><\/ul><\/li><\/ul>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\">\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"242\" height=\"345\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-17.png\" alt=\"\" class=\"wp-image-4536\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-17.png 242w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-17-210x300.png 210w\" sizes=\"auto, (max-width: 242px) 100vw, 242px\" \/><\/figure><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"412\" height=\"448\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-22.png\" alt=\"\" class=\"wp-image-4768\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-22.png 412w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-22-276x300.png 276w\" sizes=\"auto, (max-width: 412px) 100vw, 412px\" \/><\/figure><\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">Model Composer only supports up to 8 inputs and 8 outputs per IP.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-implementing-the-algorithm\"><span class=\"ez-toc-section\" id=\"Implementing-the-algorithm\"><\/span>Implementing the algorithm<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Below is shown the <em>XMC_PI_floating <\/em>subsystem. It shows that a Model Composer design is very similar to a standard Simulink design.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"445\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_algo-1024x445.png\" alt=\"\" class=\"wp-image-3869\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_algo-1024x445.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_algo-300x130.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_algo-768x334.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_algo.png 1139w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>PI-based FPGA current control using Xilinx Model Composer (XMC_PI_floating subsystem)<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"963\" height=\"344\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_pi.png\" alt=\"\" class=\"wp-image-3870\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_pi.png 963w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_pi-300x107.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_pi-768x274.png 768w\" sizes=\"auto, (max-width: 963px) 100vw, 963px\" \/><figcaption>PI subsystem implementation using Xilinx Model Composer<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"620\" height=\"231\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_sat.png\" alt=\"\" class=\"wp-image-3871\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_sat.png 620w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_sat-300x112.png 300w\" sizes=\"auto, (max-width: 620px) 100vw, 620px\" \/><figcaption>Saturation subsystem implementation using Xilinx Model Composer<\/figcaption><\/figure><\/div>\n\n\n\n<p>Here are some comments regarding this design:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>All the inputs except CLOCK_period are converted to the <em>single<\/em> data type using data type conversion (DTC) blocks. When developing a new design, we recommend using single-precision floating-point as much as possible, as this makes the design much less prone to errors. Once the design has been validated, its latency and resource usage can be further optimized by converting parts of it to fixed-point arithmetic.<br><\/li><li>The ADC values provided by the starter template (<code>Il_raw<\/code>, <code>Vin_raw <\/code>and <code>Vout_raw<\/code>) are the raw results from the ADC chips. They are multiplied by a <em>gain <\/em>inside the IP to obtain physical values. An example of <em>gain<\/em> computation is available on the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC block<\/a> help page. To simplify the model, the ADC gains are defined as constants, and offsets are simply ignored. The user could choose to use tunable parameters coming from the CPU so that the ADC can be tuned in real-time.<br><\/li><li>The Ts input provided a value in nanoseconds. It is multiplied by 1e-9 to obtain a value in seconds.<br><\/li><li>A DTC block is used to transform the <em>single<\/em> output of the <em>saturation<\/em> block into a fixed point value. Indeed, the output of the <em>saturation<\/em> block is a duty cycle ranging from 0.0 to 1.0. Such a narrow range is particularly well-suited for a fixed-point algorithm, as we know beforehand that only a single bit is required for the integer part.  We arbitrarily choose a fractional length of 15 bits so we obtain a <em>fix16_1<\/em>5 value. This value is then multiplied by the CLOCK_period, which is a uint16 value, resulting in a <em>fix32_15<\/em> (32-bit, 17-bit integer part, and 15-bit fractional part). Since the output is a number of <em>ticks<\/em>, it must be an integer value, and the fractional part is removed by simply transforming the result into a <em>uint16<\/em> using a DTC block.<br><\/li><li>In the <em>PI<\/em> subsystem, a comparison is done between the sign of the error and the sign of the integrator. Below are shown two possible implementations for such a comparison. The left option use the <em>signum<\/em> block which outputs a <em>single<\/em> value. On the right is shown a much more FPGA-optimized implementation in which the sign bits are directly compared. The <em>reinterpret<\/em> blocks are required because the <em>bit slice<\/em> does not support floating point inputs.<\/li><\/ul>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-18.png\" alt=\"\" class=\"wp-image-4537\" width=\"166\" height=\"155\"\/><figcaption>Straightforward but poorly optimized sign comparison<\/figcaption><\/figure><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"217\" height=\"167\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-20.png\" alt=\"\" class=\"wp-image-4539\"\/><figcaption>Highly optimized sign comparison by directly comparing the sign bit<\/figcaption><\/figure><\/div>\n<\/div>\n<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-verifying-the-design-in-simulation\"><span class=\"ez-toc-section\" id=\"Verifying-the-design-in-simulation\"><\/span>Verifying the design in simulation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>A Model Composer model can be verified using standard Simulink simulation. It allows to easily generate stimulus inputs and observe the results. Below is shown the test bench that is used to validate the proper functioning of the Model Composer implementation of the FPGA current control. It compares the result of the already-tested Simulink implementation of the <a href=\"https:\/\/imperix.com\/doc\/implementation\/basic-pi-control\">basic PI-control<\/a> technical note with the Model Composer design.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"691\" height=\"735\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-38.png\" alt=\"\" class=\"wp-image-4900\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-38.png 691w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-38-282x300.png 282w\" sizes=\"auto, (max-width: 691px) 100vw, 691px\" \/><figcaption>Validation of the Xilinx Model Composer (XMC) design<\/figcaption><\/figure><\/div>\n\n\n\n<p>The screenshot below shows the buck converter model used to validate the current control algorithm. It also simulates the PWM generation. The outputs of this model are continuous values in volts or amperes. The <em>ADC sample<\/em> subsystem models the ADC chips behavior by transforming the continuous physical values into sampled int16 values.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"927\" height=\"333\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-21.png\" alt=\"\" class=\"wp-image-4540\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-21.png 927w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-21-300x108.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-21-768x276.png 768w\" sizes=\"auto, (max-width: 927px) 100vw, 927px\" \/><figcaption>Buck Converter Model using<br>Simscape Electrical Specialized Power Systems library<\/figcaption><\/figure>\n\n\n\n<p>The Simulink-based current control algorithm that serves as the reference implementation is shown below.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"587\" height=\"367\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-39.png\" alt=\"\" class=\"wp-image-4902\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-39.png 587w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-39-300x188.png 300w\" sizes=\"auto, (max-width: 587px) 100vw, 587px\" \/><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"682\" height=\"389\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-41.png\" alt=\"\" class=\"wp-image-4904\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-41.png 682w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-41-300x171.png 300w\" sizes=\"auto, (max-width: 682px) 100vw, 682px\" \/><figcaption>Simulink-based current control algorithm<\/figcaption><\/figure><\/div>\n\n\n\n<p>The reference current input is stepped from 3 A to 5 A. It can be observed that both implementations are behaving very similarly.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"612\" height=\"447\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_model_simu_scope.png\" alt=\"\" class=\"wp-image-3890\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_model_simu_scope.png 612w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/model_composer_model_simu_scope-300x219.png 300w\" sizes=\"auto, (max-width: 612px) 100vw, 612px\" \/><figcaption>Comparison of  Simulink-based vs Xilinx Model Composer (XMC) algorithm<\/figcaption><\/figure><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-generating-an-ip-core-using-model-composer\"><span class=\"ez-toc-section\" id=\"Generating-an-IP-core-using-Model-Composer\"><\/span>Generating an IP core using Model Composer<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>As mentioned earlier, Model Composer is an automated generation code tool based on Vivado HLS C++. Unfortunately, Model Composer uses the <em>#pragma HLS PIPELINE<\/em> directive by default which causes issues in our use case.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-why-is-the-hls-pipeline-pragma-an-issue\">Why is the <em>HLS PIPELINE pragma<\/em> an issue?<\/h4>\n\n\n\n<p>The PIPELINE primitive reduces the initiation interval (II). In other words, it increases the maximal throughput of the IP by reducing the number of clock cycles between each input. The side effect is that the data is &#8220;stuck&#8221; in the IP until new data is fed to the input. For instance, if the IP latency is 10, then the result for the 1st data will be available only after the 10th data has been loaded into the IP. This is suitable for applications such as video processing where the data stream is constant and throughput optimization is most important. However, in a closed-loop control system such as ours, this behavior is not adequate, so we need to remove the HLS PIPELINE directive.<\/p>\n\n\n\n<p>For more information on the PIPELINE directive, please refer to the <a href=\"https:\/\/www.xilinx.com\/html_docs\/xilinx2021_1\/vitis_doc\/hls_pragmas.html#fde1504034360078\">Xilinx HLS pragmas documentation<\/a>.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-ip-core-generation-step-by-step-procedure\">IP core generation step-by-step procedure<\/h4>\n\n\n\n<ul class=\"wp-block-list\"><li>Open the <strong>Model Composer Hub<\/strong><ul><li>make sure the <strong>target <\/strong>is <em>HLS C++ code<\/em><\/li><li>select a <strong>code directory<\/strong>, for instance <code>C:\/KnowledgeBase\/XMC\/PiCtrl\/Code<\/code><\/li><li>click <strong>Generate<\/strong><\/li><\/ul><\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"424\" height=\"417\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-42.png\" alt=\"\" class=\"wp-image-4906\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-42.png 424w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-42-300x295.png 300w\" sizes=\"auto, (max-width: 424px) 100vw, 424px\" \/><\/figure><\/div>\n\n\n\n<ul class=\"wp-block-list\"><li>Launch the <strong>Vitis HLS Command Prompt<\/strong> program<\/li><li>Change the directory to the parent folder of the <em>code directory<\/em> specified above<\/li><\/ul>\n\n\n<pre class=\"wp-block-code\"><span><code class=\"hljs\">cd C:\/KB\/PN163\/Generated<\/code><\/span><\/pre>\n\n\n<ul class=\"wp-block-list\"><li>Launch the run_hls.tcl script, which creates a Vitis HLS project<\/li><\/ul>\n\n\n<pre class=\"wp-block-code\"><span><code class=\"hljs\">vitis_hls -f .\/Code\/run_hls.tcl<\/code><\/span><\/pre>\n\n\n<ul class=\"wp-block-list\"><li>Open the freshly created project with Vitis HLS by running the command below. (Alternatively, the project can be manually opened from Vitis HLS.)<\/li><\/ul>\n\n\n<pre class=\"wp-block-code\"><span><code class=\"hljs\">vitis_hls -p .\/Code\/XMC_CurrentControl_prj<\/code><\/span><\/pre>\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"643\" height=\"259\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-44.png\" alt=\"\" class=\"wp-image-4908\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-44.png 643w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-44-300x121.png 300w\" sizes=\"auto, (max-width: 643px) 100vw, 643px\" \/><\/figure><\/div>\n\n\n\n<ul class=\"wp-block-list\"><li>To remove the HLS pipeline directive: <ul><li>Open the source file <code>XMC_CurrentControl.cpp<\/code>.<\/li><li>Open the tab <em>Directive<\/em> on the right.<\/li><li>Find the <em>HLS pipeline<\/em> directive, right click and hit &#8220;Remove directive&#8221;. Alternatively, the line e<code> #pragma HLS pipeline<\/code> can be manually removed from the C++ code.<\/li><li>Save the project (Ctrl+S).<\/li><\/ul><\/li><\/ul>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"750\" height=\"585\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-46.png\" alt=\"\" class=\"wp-image-4910\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-46.png 750w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-46-300x234.png 300w\" sizes=\"auto, (max-width: 750px) 100vw, 750px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\"><li>Launch the C Synthesis by going to Solution -&gt; Run C Synthesis -&gt; Active Solution<\/li><\/ul>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"727\" height=\"470\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-49.png\" alt=\"\" class=\"wp-image-4913\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-49.png 727w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-49-300x194.png 300w\" sizes=\"auto, (max-width: 727px) 100vw, 727px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\"><li>Once the synthesis is done, export the RTL using the Vivado IP format<ul><li>Click Solution -&gt; Export RTL,<\/li><li>Select the <em>Vivado IP (.zip)<\/em> format,<\/li><li>The generated RTL can be VHDL or Verilog, it does not matter.<\/li><li>Choose an output location, for instance <code><code>C:\/KB\/PN163\/Generated\/IP<\/code><\/code>,<\/li><\/ul><ul><li>Click OK.<\/li><\/ul><\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"499\" height=\"377\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-48.png\" alt=\"\" class=\"wp-image-4912\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-48.png 499w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-48-300x227.png 300w\" sizes=\"auto, (max-width: 499px) 100vw, 499px\" \/><\/figure><\/div>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-performance-and-resource-estimates\">Performance and resource estimates<\/h4>\n\n\n\n<p>The FPGA of imperix controllers (part: xc7z030fbg676-3) possesses 78600 LUT, 157200 FF and 400 DSP, from which around ~30% is used by the imperix firmware IP.&nbsp; By clicking on Solution -&gt; Open Report -&gt; Synthesis, the user has access to the <strong>synthesis summary report<\/strong> which estimates the IP latency and resource usage. Make sure that the <strong>Pipelined<\/strong> option is set to <em>no<\/em>.<\/p>\n\n\n\n<p>Our IP shows the following estimation: 3460 LUT (4.4% of total), 2988 FF (1.9%), and 9 DSP (2.3%).<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"875\" height=\"348\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-50.png\" alt=\"\" class=\"wp-image-4914\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-50.png 875w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-50-300x119.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-50-768x305.png 768w\" sizes=\"auto, (max-width: 875px) 100vw, 875px\" \/><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The tool generates a warning if it thinks a timing violation may occur. However, this is only an estimation. We observe that Vitis HLS always generates a timing violation warning when using an integer to floating-point conversion (<em>uitofp <\/em>operation) and a target period of 4 ns. However, when implementing the full FPGA design, Vivado still reaches successful timing closure.<\/div>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-adding-the-ip-core-to-a-vivado-project\">Adding the IP core to a Vivado project<\/h4>\n\n\n\n<p>To interconnect the generated IP with other IPs, it needs to be added to a Vivado project. To do, in Vivado:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Unzip the file generated by Vitis HLS (XMC_CurrentControl.zip),<\/li><li>Go to the IP Catalog,<\/li><li>Right-click and select Add Repository&#8230;<\/li><li>Select the folder containing your unzipped IP (e.g. <code>C:\\imperix\\sandbox_sources\\my_IPs<\/code>). This folder can cotain multiple IPs.<\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-75.png\" alt=\"\" class=\"wp-image-5017\" width=\"365\" height=\"247\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-75.png 486w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-75-300x203.png 300w\" sizes=\"auto, (max-width: 365px) 100vw, 365px\" \/><\/figure><\/div>\n\n\n\n<ul class=\"wp-block-list\"><li>And finally the IP can be added to a block design like any other Xilinx IP.<\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-64.png\" alt=\"\" class=\"wp-image-4937\" width=\"375\" height=\"278\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-64.png 485w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-64-300x222.png 300w\" sizes=\"auto, (max-width: 375px) 100vw, 375px\" \/><\/figure><\/div>\n\n\n\n<p>To see this IP in action please refer to the <a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">FPGA current control using high-level synthesis<\/a> page.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>Model Composer is a Simulink add-on software developed by Xilinx. It is a high-level synthesis (HLS) tool that allows the user to program an FPGA-based&#8230;<\/p>\n","protected":false},"author":4,"featured_media":7243,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"default","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106,103],"provided-results":[107],"related-products":[31,32,92,166,110],"guidedreadings":[],"tutorials":[179,130],"user-manuals":[],"coauthors":[70],"class_list":["post-3160","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","software-environments-matlab","provided-results-simulation","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","tutorials-automated-tools-for-fpga-developments","tutorials-custom-fpga-pwm-modulator-implementation"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Xilinx Model Composer introduction - imperix<\/title>\n<meta name=\"description\" content=\"Xilinx Model Composer is a Simulink add-on. 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