{"id":3182,"date":"2021-06-02T11:17:31","date_gmt":"2021-06-02T11:17:31","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3182"},"modified":"2025-05-07T09:23:40","modified_gmt":"2025-05-07T09:23:40","slug":"xilinx-system-generator","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator","title":{"rendered":"Xilinx System Generator introduction"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#Alternatives-to-Xilinx-System-Generator\" >Alternatives to Xilinx System Generator<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#What-is-the-difference-between-System-Generator-and-Model-Composer\" >What is the difference between System Generator and Model Composer?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#Downloading-and-installing-Xilinx-System-Generator\" >Downloading and installing Xilinx System Generator<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#Typical-workflow\" >Typical workflow<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#How-to-launch-System-Generator\" >How to launch System Generator?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#Implement-a-design-using-System-Generator\" >Implement a design using System Generator<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#Testing-the-design-in-simulation\" >Testing the design in simulation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\/#Generating-a-Vivado-IP-Core-using-System-Generator\" >Generating a Vivado IP Core using System Generator<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p><strong>Xilinx System Generator for DSP<\/strong> (SysGen) is a MATLAB Simulink add-on that enables the development of architecture-level FPGA designs using graphical blocks programming.  Users can validate their designs through simulation in Simulink and the design can be packaged into a Vivado IP and easily imported into a Vivado project.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">This page was created with a previous version of System Generator. Minor changes may have occurred since. <\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-alternatives-to-xilinx-system-generator\"><span class=\"ez-toc-section\" id=\"Alternatives-to-Xilinx-System-Generator\"><\/span>Alternatives to Xilinx System Generator<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>An alternative to System Generator is MATLAB&#8217;s <a href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\">HDL Coder<\/a>, another MATLAB Simulink add-on that works very similarly. The main difference between System Generator and HDL Coder is that System Generator targets exclusively Xilinx FPGA devices. As such, it generates pre-packaged core IPs that can easily be imported in Vivado. Moreover, System Generator is bundled with <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a>, another FPGA development blockset that provides additional features that HDL Coder does not have.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-what-is-the-difference-between-system-generator-and-model-composer\"><span class=\"ez-toc-section\" id=\"What-is-the-difference-between-System-Generator-and-Model-Composer\"><\/span>What is the difference between System Generator and Model Composer?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Compared to high-level synthesis tools such as<strong> <\/strong>Xilinx Model Composer, System Generator is a &#8220;lower-level&#8221; design tool intended for architecture-level FPGA designs, down to the flip-flop register. System Generator allows for finer control over the resulting HDL code and is more adapted for FPGA peripheral designs such as PWM modulators or SPI controllers. Unlike Model Composer and Vitis HLS, System Generator does not support AXI4-Stream interfaces.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-downloading-and-installing-xilinx-system-generator\"><span class=\"ez-toc-section\" id=\"Downloading-and-installing-Xilinx-System-Generator\"><\/span>Downloading and installing Xilinx System Generator<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>System Generator, along with Model Composer is part of the <strong>Xilinx Add-on for MATLAB &amp; Simulink<\/strong> which can be bought as an add-on license to Vivado or Vitis. At the time of writing this page, the price is set at $500 for a node-locked license and $700 for a floating license (a free 90 days license is available).<\/p>\n\n\n\n<p>To install the Xilinx Add-on for MATLAB &amp; Simulink, an option must be selected during the installation of Xilinx Vivado System Edition. If Vivado is already installed,  the <em>Vivado Add Design Tools<\/em> program should be used to install the add-on.<\/p>\n\n\n\n<p>More information on the <em>Xilinx Add-on for MATLAB &amp; Simulink<\/em> is available on <a href=\"https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/addon-matlab-simulink.html#buy\">this Xilinx page<\/a>.<br>Installation instructions are available on the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-blockset-for-simulink\">Xilinx Blockset for Simulink<\/a> page.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-typical-workflow\"><span class=\"ez-toc-section\" id=\"Typical-workflow\"><\/span>Typical workflow<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This section broadly outlines the main steps required to generate a Vivado IP using System Generator. For more detailed information, the user should refer to the official documentation of which some are listed below:<\/p>\n\n\n\n<ul class=\"wp-block-list\" id=\"block-b69c4084-efab-4a11-ae2d-6d6b2d586d8f\"><li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2020_2\/ug897-vivado-sysgen-user.pdf\">Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (xilinx.com)<\/a><\/li><li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2020_2\/ug948-vivado-sysgen-tutorial.pdf\">Vivado Design Suite Tutorial: Model-Based DSP Design Using System Generator (xilinx.com)<\/a><\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-how-to-launch-system-generator\"><span class=\"ez-toc-section\" id=\"How-to-launch-System-Generator\"><\/span>How to launch System Generator?<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>If <em>Xilinx Add-on for MATLAB &amp; Simulink<\/em> has been successfully installed, a &#8220;Model Composer and System Generator&#8221; shortcut should have been created on the desktop. This program will open a new MATLAB session and load the Xilinx System Generator library for Simulink.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">If multiple concurrent MATLAB Simulink installations are present on the computer, Model Composer will launch the latest version of MATLAB Simulink available by default. It can cause problems if the latest version of Simulink is not compatible with System Generator (for instance Model Composer 2020.2 is not compatible with MATLAB R2021a). However, it is possible to manually change which version of MATLAB Simulink System Generator will use, as explained in the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-blockset-for-simulink\">installing Xilinx blockset for Simulink<\/a> page.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-implement-a-design-using-system-generator\"><span class=\"ez-toc-section\" id=\"Implement-a-design-using-System-Generator\"><\/span>Implement a design using System Generator<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The image below shows an example of a System Generator design taken from the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">custom FPGA PWM modulator<\/a> page. This example will be used as support to illustrate the key points of the System Generator workflow. The sources are available in the zip below.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"406\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_pwm_impl-1024x406.png\" alt=\"FPGA PWM modulator designed using Xilinx System Generator\" class=\"wp-image-3764\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_pwm_impl-1024x406.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_pwm_impl-300x119.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_pwm_impl-768x305.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_pwm_impl-1536x609.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_pwm_impl.png 1686w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>FPGA PWM modulator designed using Xilinx System Generator<\/figcaption><\/figure>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/PN161_System_Generator.zip\" class=\"wp-block-file__button\" download>Click to download <strong>PN161_System_Generator.zip<\/strong><\/a><\/div>\n\n\n\n<p>The design should use System Generator blocks (available in the Simulink library browser, under <em>Xilinx Toolbox<\/em> -&gt; <em>HDL<\/em>, or more recently under <em>AMD Toolbox -&gt; HDL<\/em>) and the following points should be observed:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>The logic has to be placed in a <em>subsystem<\/em><\/li><li>The <em>Gateway in<\/em> and <em>Gateway out<\/em> blocks have to be used to represent the input\/output ports of the generated IP<\/li><li>Between the <em>Gateway<\/em> blocks, only blocks from the <em>Xilinx Toolbox<\/em>\/<em>HDL<\/em> library should be used<\/li><li>A <em>System Generator<\/em> block has to be added as a control panel for simulation and IP generation.<\/li><\/ul>\n\n\n\n<p>The sample period must be set to match the clock frequency that will be used in the FPGA. In the imperix controller FPGA design, the <em>clk_250_mhz <\/em>output is used most of the time. It corresponds to a period of 4 ns. <\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p>The following configuration is used:<\/p>\n\n\n\n<ul class=\"wp-block-list\" id=\"block-63f80e5a-313b-44ff-b119-55c614ab7b46\"><li><em><strong>Sampled period<\/strong><\/em> of all <em>Gateway In <\/em>blocks is set to <strong>4e-9<\/strong><\/li><li><strong><em>Simulink system period (sec)<\/em><\/strong> under the <em>Clocking<\/em> tab of the <em>System Generator<\/em> block is set to <strong>4e-9<\/strong><\/li><li><strong><em>FPGA clock period (ns)<\/em> <\/strong>under the <em>Clocking<\/em> tab of the <em>System Generator<\/em> block is set to <strong>4<\/strong><\/li><\/ul>\n\n\n\n<p>The input and output types are set as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li><strong><em>i_nextDutyCycle<\/em><\/strong>, <strong><em>CLOCK_period<\/em><\/strong>, <strong><em>CLOCK_prescaler <\/em><\/strong>: 16-bit unsigned integer (Fixed-point, Unsigned, Number of bits: 16, Binary point: 0)<\/li><li><em><strong>CLOCK_clk_en<\/strong><\/em>, <strong><em>i_UpdateRate<\/em><\/strong>: 1-bit (Boolean)<\/li><\/ul>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_gatewayin-2.png\" alt=\"\" class=\"wp-image-3777\" width=\"357\" height=\"545\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_gatewayin-2.png 357w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_gatewayin-2-197x300.png 197w\" sizes=\"auto, (max-width: 357px) 100vw, 357px\" \/><\/figure><\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_clocking.png\" alt=\"\" class=\"wp-image-3780\" width=\"350\" height=\"358\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_clocking.png 466w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_clocking-293x300.png 293w\" sizes=\"auto, (max-width: 350px) 100vw, 350px\" \/><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_compilation.png\" alt=\"\" class=\"wp-image-3781\" width=\"350\" height=\"358\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_compilation.png 466w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_compilation-293x300.png 293w\" sizes=\"auto, (max-width: 350px) 100vw, 350px\" \/><\/figure>\n<\/div>\n<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-testing-the-design-in-simulation\"><span class=\"ez-toc-section\" id=\"Testing-the-design-in-simulation\"><\/span>Testing the design in simulation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>A Xilinx System Generator design can be validated by building a test bench that uses standard Simulink blocks. Below is shown an example of a testbench, which is further documented in the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">FPGA PWM modulator example<\/a>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"360\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-181-1024x360.png\" alt=\"FPGA PWM simulation in Xilinx System Generator\" class=\"wp-image-3641\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-181-1024x360.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-181-300x105.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-181-768x270.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-181-1536x539.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-181.png 1683w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>FPGA PWM simulation model<\/figcaption><\/figure>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"604\" height=\"409\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-5.png\" alt=\"FPGA PWM simulation result in Xilinx System Generator\" class=\"wp-image-4330\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-5.png 604w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-5-300x203.png 300w\" sizes=\"auto, (max-width: 604px) 100vw, 604px\" \/><figcaption>FPGA PWM simulation result<\/figcaption><\/figure><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-generating-a-vivado-ip-core-using-system-generator\"><span class=\"ez-toc-section\" id=\"Generating-a-Vivado-IP-Core-using-System-Generator\"><\/span>Generating a Vivado IP Core using System Generator<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The Vivado IP generation is launched from the <em>System Generator <\/em>block. The user defines a <strong>target directory<\/strong> and then clicks on <strong>Generate<\/strong>, as shown below. The compilation and generation take approximately 5 minutes for the provided FPGA PWM modulator example.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"466\" height=\"477\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-36.png\" alt=\"\" class=\"wp-image-4889\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-36.png 466w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-36-293x300.png 293w\" sizes=\"auto, (max-width: 466px) 100vw, 466px\" \/><\/figure><\/div>\n\n\n\n<p>To use this IP in a Vivado project, the user has to:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Open the <strong>IP Catalog<\/strong><\/li><li>Right-click and select <strong>Add repository<\/strong>&#8230;<\/li><li>Select the path to the generated IP (for instance <code>C:\\KB\\PN161\\Generated\\ip<\/code>)<\/li><li>The generated IP (shown below) can then be added to a block design like any other IP<\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_ip_vivado-1.png\" alt=\"FPGA PWM IP generated by Xilinx System Generator\" class=\"wp-image-3790\" width=\"361\" height=\"236\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_ip_vivado-1.png 426w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/sysgen_ip_vivado-1-300x196.png 300w\" sizes=\"auto, (max-width: 361px) 100vw, 361px\" \/><figcaption>FPGA PWM IP generated by Xilinx System Generator<\/figcaption><\/figure><\/div>\n\n\n\n<p>A step-by-step example explaining how to integrate the PWM modulator IP in a Vivado project is available on the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">FPGA PWM modulator<\/a> example page.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>Xilinx System Generator for DSP (SysGen) is a MATLAB Simulink add-on that enables the development of architecture-level FPGA designs using graphical blocks programming. Users can&#8230;<\/p>\n","protected":false},"author":4,"featured_media":7237,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106,103],"provided-results":[107],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[130],"user-manuals":[],"coauthors":[70],"class_list":["post-3182","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","software-environments-matlab","provided-results-simulation","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","tutorials-custom-fpga-pwm-modulator-implementation"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Xilinx System Generator (SysGen) for DSP introduction - imperix<\/title>\n<meta name=\"description\" content=\"Xilinx System Generator (SysGen) for DSP is a Simulink add-on that enables the development of FPGA designs using graphical blocks programming.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Xilinx System Generator (SysGen) for DSP introduction - imperix\" \/>\n<meta property=\"og:description\" content=\"Xilinx System Generator (SysGen) for DSP is a Simulink add-on that enables the development of FPGA designs using graphical blocks programming.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\" \/>\n<meta property=\"og:site_name\" content=\"imperix\" \/>\n<meta property=\"article:published_time\" content=\"2021-06-02T11:17:31+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2025-05-07T09:23:40+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/xilinx-system-generator.png\" \/>\n\t<meta property=\"og:image:width\" content=\"450\" \/>\n\t<meta property=\"og:image:height\" content=\"300\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"Beno\u00eet Steinmann\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Beno\u00eet Steinmann\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"6 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator\"},\"author\":{\"name\":\"Beno\u00eet Steinmann\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#\\\/schema\\\/person\\\/a69a3bda75b05d0923cc76d7268cc94f\"},\"headline\":\"Xilinx System Generator introduction\",\"datePublished\":\"2021-06-02T11:17:31+00:00\",\"dateModified\":\"2025-05-07T09:23:40+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator\"},\"wordCount\":1012,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#organization\"},\"image\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/06\\\/xilinx-system-generator.png\",\"keywords\":[\"FPGA programming\"],\"articleSection\":[\"Product notes\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator\",\"name\":\"Xilinx System Generator (SysGen) for DSP introduction - imperix\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/06\\\/xilinx-system-generator.png\",\"datePublished\":\"2021-06-02T11:17:31+00:00\",\"dateModified\":\"2025-05-07T09:23:40+00:00\",\"description\":\"Xilinx System Generator (SysGen) for DSP is a Simulink add-on that enables the development of FPGA designs using graphical blocks programming.\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#primaryimage\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/06\\\/xilinx-system-generator.png\",\"contentUrl\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/06\\\/xilinx-system-generator.png\",\"width\":450,\"height\":300,\"caption\":\"xilinx system generator\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/xilinx-system-generator#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Knowledge base\",\"item\":\"https:\\\/\\\/imperix.com\\\/doc\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Product notes\",\"item\":\"https:\\\/\\\/imperix.com\\\/doc\\\/category\\\/help\"},{\"@type\":\"ListItem\",\"position\":3,\"name\":\"Xilinx System Generator introduction\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#website\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/\",\"name\":\"imperix\",\"description\":\"power electronics\",\"publisher\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/imperix.com\\\/doc\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#organization\",\"name\":\"imperix\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#\\\/schema\\\/logo\\\/image\\\/\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/03\\\/imperix_logo.png\",\"contentUrl\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/03\\\/imperix_logo.png\",\"width\":350,\"height\":120,\"caption\":\"imperix\"},\"image\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#\\\/schema\\\/logo\\\/image\\\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#\\\/schema\\\/person\\\/a69a3bda75b05d0923cc76d7268cc94f\",\"name\":\"Beno\u00eet Steinmann\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g3b3f3d8e66019ebcb2848094940b98c0\",\"url\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g\",\"contentUrl\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g\",\"caption\":\"Beno\u00eet Steinmann\"},\"description\":\"Benoit is an embedded systems expert and the leader of software and firmware developments at imperix. On the knowledge base, he is the author of numerous software reference documents.\",\"sameAs\":[\"https:\\\/\\\/www.linkedin.com\\\/in\\\/benoit-steinmann\\\/\"],\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/author\\\/steinmann\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Xilinx System Generator (SysGen) for DSP introduction - imperix","description":"Xilinx System Generator (SysGen) for DSP is a Simulink add-on that enables the development of FPGA designs using graphical blocks programming.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator","og_locale":"en_US","og_type":"article","og_title":"Xilinx System Generator (SysGen) for DSP introduction - imperix","og_description":"Xilinx System Generator (SysGen) for DSP is a Simulink add-on that enables the development of FPGA designs using graphical blocks programming.","og_url":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator","og_site_name":"imperix","article_published_time":"2021-06-02T11:17:31+00:00","article_modified_time":"2025-05-07T09:23:40+00:00","og_image":[{"width":450,"height":300,"url":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/xilinx-system-generator.png","type":"image\/png"}],"author":"Beno\u00eet Steinmann","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Beno\u00eet Steinmann","Est. reading time":"6 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#article","isPartOf":{"@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator"},"author":{"name":"Beno\u00eet Steinmann","@id":"https:\/\/imperix.com\/doc\/#\/schema\/person\/a69a3bda75b05d0923cc76d7268cc94f"},"headline":"Xilinx System Generator introduction","datePublished":"2021-06-02T11:17:31+00:00","dateModified":"2025-05-07T09:23:40+00:00","mainEntityOfPage":{"@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator"},"wordCount":1012,"commentCount":0,"publisher":{"@id":"https:\/\/imperix.com\/doc\/#organization"},"image":{"@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#primaryimage"},"thumbnailUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/xilinx-system-generator.png","keywords":["FPGA programming"],"articleSection":["Product notes"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#respond"]}]},{"@type":"WebPage","@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator","url":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator","name":"Xilinx System Generator (SysGen) for DSP introduction - imperix","isPartOf":{"@id":"https:\/\/imperix.com\/doc\/#website"},"primaryImageOfPage":{"@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#primaryimage"},"image":{"@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#primaryimage"},"thumbnailUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/xilinx-system-generator.png","datePublished":"2021-06-02T11:17:31+00:00","dateModified":"2025-05-07T09:23:40+00:00","description":"Xilinx System Generator (SysGen) for DSP is a Simulink add-on that enables the development of FPGA designs using graphical blocks programming.","breadcrumb":{"@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/imperix.com\/doc\/help\/xilinx-system-generator"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#primaryimage","url":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/xilinx-system-generator.png","contentUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/xilinx-system-generator.png","width":450,"height":300,"caption":"xilinx system generator"},{"@type":"BreadcrumbList","@id":"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Knowledge base","item":"https:\/\/imperix.com\/doc\/"},{"@type":"ListItem","position":2,"name":"Product notes","item":"https:\/\/imperix.com\/doc\/category\/help"},{"@type":"ListItem","position":3,"name":"Xilinx System Generator introduction"}]},{"@type":"WebSite","@id":"https:\/\/imperix.com\/doc\/#website","url":"https:\/\/imperix.com\/doc\/","name":"imperix","description":"power electronics","publisher":{"@id":"https:\/\/imperix.com\/doc\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/imperix.com\/doc\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/imperix.com\/doc\/#organization","name":"imperix","url":"https:\/\/imperix.com\/doc\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/imperix.com\/doc\/#\/schema\/logo\/image\/","url":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/imperix_logo.png","contentUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/imperix_logo.png","width":350,"height":120,"caption":"imperix"},"image":{"@id":"https:\/\/imperix.com\/doc\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/imperix.com\/doc\/#\/schema\/person\/a69a3bda75b05d0923cc76d7268cc94f","name":"Beno\u00eet Steinmann","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/secure.gravatar.com\/avatar\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g3b3f3d8e66019ebcb2848094940b98c0","url":"https:\/\/secure.gravatar.com\/avatar\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g","caption":"Beno\u00eet Steinmann"},"description":"Benoit is an embedded systems expert and the leader of software and firmware developments at imperix. On the knowledge base, he is the author of numerous software reference documents.","sameAs":["https:\/\/www.linkedin.com\/in\/benoit-steinmann\/"],"url":"https:\/\/imperix.com\/doc\/author\/steinmann"}]}},"_links":{"self":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts\/3182","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/comments?post=3182"}],"version-history":[{"count":92,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts\/3182\/revisions"}],"predecessor-version":[{"id":37254,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts\/3182\/revisions\/37254"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/media\/7237"}],"wp:attachment":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/media?parent=3182"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/categories?post=3182"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/tags?post=3182"},{"taxonomy":"software-environments","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/software-environments?post=3182"},{"taxonomy":"provided-results","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/provided-results?post=3182"},{"taxonomy":"related-products","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/related-products?post=3182"},{"taxonomy":"guidedreadings","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/guidedreadings?post=3182"},{"taxonomy":"tutorials","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/tutorials?post=3182"},{"taxonomy":"user-manuals","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/user-manuals?post=3182"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/coauthors?post=3182"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}