{"id":3184,"date":"2021-06-02T11:18:05","date_gmt":"2021-06-02T11:18:05","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3184"},"modified":"2025-05-07T09:30:53","modified_gmt":"2025-05-07T09:30:53","slug":"xilinx-vitis-hls","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls","title":{"rendered":"Xilinx Vitis HLS introduction"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\/#Alternative-to-Xilinx-Vitis-HLS\" >Alternative to Xilinx Vitis HLS<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\/#Downloading-and-installing-Xilinx-Vitis-HLS\" >Downloading and installing Xilinx Vitis HLS<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\/#Xilinx-Vitis-HLS-example-workflow\" >Xilinx Vitis HLS example workflow<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\/#Creating-a-xilinx-Vitis-HLS-project\" >Creating a xilinx Vitis HLS project<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\/#Defining-the-IP-input-and-output-ports\" >Defining the IP input and output ports<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\/#Implementing-the-algorithm\" >Implementing the algorithm<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\/#Generating-an-IP-core-using-Vitis-HLS\" >Generating an IP core using Vitis HLS<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p><strong>Xilinx Vitis HLS<\/strong> (formerly Xilinx Vivado HLS) is a High-Level Synthesis (HLS) tool developed by Xilinx and available at no cost. Vitis HLS allows the user to easily create complex FPGA-based algorithms using C\/C++ code. It supports complex data types (floating-points, fixed-points,&#8230;) and math functions (sine, arctan, sqrt,&#8230;). It also supports AXI4-Stream to easily exchange data with other IPs.<\/p>\n\n\n\n<p>This tools is particularly useful when porting a control algorithm from the CPU to the FPGA of a power converter controller such as the <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a>, the\u00a0<a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-alternative-to-xilinx-vitis-hls\"><span class=\"ez-toc-section\" id=\"Alternative-to-Xilinx-Vitis-HLS\"><\/span>Alternative to Xilinx Vitis HLS<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>An alternative to Vitis HLS is <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a>, which provides the same features in a MATLAB Simulink environment. For &#8220;lower-level&#8221; designs such as PWM modulators, tools such as <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\">System Generator<\/a> or <a href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\">HDL Coder<\/a> are more appropriate.<\/p>\n\n\n\n<p>Compared to Model Composer, Vitis HLS presents the advantage of being standalone and free of cost. However, Vitis HLS may be more difficult to use, as it requires some C++ skills. Moreover, it is much more tedious to write testbenches for Vivado HLS designs.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-downloading-and-installing-xilinx-vitis-hls\"><span class=\"ez-toc-section\" id=\"Downloading-and-installing-Xilinx-Vitis-HLS\"><\/span>Downloading and installing Xilinx Vitis HLS<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Xilinx Vitis HLS is installed alongside Vivado, as details in the <a href=\"https:\/\/imperix.com\/doc\/help\/vivado-design-suite-installation\">installing Vivado Design Suite<\/a> page.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-xilinx-vitis-hls-example-workflow\"><span class=\"ez-toc-section\" id=\"Xilinx-Vitis-HLS-example-workflow\"><\/span>Xilinx Vitis HLS example workflow<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This tutorial broadly outlines the main steps required to generate a Vivado IP using Vitis HLS. It is not its purpose to be exhaustive but rather serves as a guideline. It also provides tips for designs targetting imperix controllers. For more detailed information, the user should refer to the Xilinx documentation, such as:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2020_2\/ug871-vivado-high-level-synthesis-tutorial.pdf\">The High-Level Synthesis Tutorial<\/a> (xilinx.com)<\/li><li><a href=\"https:\/\/github.com\/Xilinx\/HLS-Tiny-Tutorials\/tree\/master\"><\/a><a href=\"https:\/\/github.com\/Xilinx\/Vitis-Tutorials\/tree\/master\/Getting_Started\/Vitis_HLS\">Getting Started with Vitis HLS<\/a> (github.com)<\/li><li><a href=\"https:\/\/github.com\/Xilinx\/HLS-Tiny-Tutorials\/tree\/master\">Xilinx HLS basic examples<\/a> (github.com)<\/li><\/ul>\n\n\n\n<p>The sources of this Xilinx Vitis HLS example can be downloaded below.<\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/PN164_Xilinx_Vitis_HLS.zip\" class=\"wp-block-file__button\" download>Click to download <strong>PN164_Xilinx_Vitis_HLS.zip<\/strong><\/a><\/div>\n\n\n\n<p>The tutorial uses a PI-based current control implementation as an example to illustrate the key points of the Xilinx Vitis HLS workflow. It is based on the Forward Euler method, which is presented on the <a href=\"https:\/\/imperix.com\/doc\/implementation\/basic-pi-control\">PI controller implementation for current control<\/a> technical note.<\/p>\n\n\n\n<p>It is highly recommended to read through the <a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">high-Level synthesis for FPGA developments<\/a> page to see how this IP integrates into a complete design. It will help to understand some of the choices made, notably concerning the input and output ports.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-creating-a-xilinx-vitis-hls-project\"><span class=\"ez-toc-section\" id=\"Creating-a-xilinx-Vitis-HLS-project\"><\/span>Creating a xilinx Vitis HLS project<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>1. Launch Xilinx Vitis HLS (the following screenshots comes from Vitis HLS 2020.2)<br>2. Click on <strong>Create Project<\/strong> or go to <strong>File <\/strong>-&gt; <strong>New Project&#8230;<\/strong><br>3. Enter a project name and hit <strong>Next<\/strong><\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"588\" height=\"430\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-141.png\" alt=\"\" class=\"wp-image-3574\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-141.png 588w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-141-300x219.png 300w\" sizes=\"auto, (max-width: 588px) 100vw, 588px\" \/><\/figure><\/div>\n\n\n\n<p>4. Chose a top function name. This will also be the name of the resulting Vivado IP. Hit <strong>Next<\/strong><\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"588\" height=\"430\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-142.png\" alt=\"\" class=\"wp-image-3575\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-142.png 588w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-142-300x219.png 300w\" sizes=\"auto, (max-width: 588px) 100vw, 588px\" \/><\/figure><\/div>\n\n\n\n<p>5. There is no need to select a testbench file at this stage. Hit <strong>Next.<\/strong><\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"588\" height=\"430\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-143.png\" alt=\"\" class=\"wp-image-3576\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-143.png 588w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-143-300x219.png 300w\" sizes=\"auto, (max-width: 588px) 100vw, 588px\" \/><\/figure><\/div>\n\n\n\n<p>6. Setup the clock period of <strong>4 ns<\/strong>. Select the part&nbsp;<strong>xc7z030fbg676-3<\/strong>, keep <strong>Vivado IP Flow Target <\/strong>for the Flow Target, and hit <strong>Finish<\/strong>.<\/p>\n\n\n\n<p>7. Add sources the C++ source files to the project. In this example, we add the sources <code>PiBasedCurrentControl.cpp<\/code> and <code>PiBasedCurrentControl.h<\/code>. These files are available in the zip provided above.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"780\" height=\"417\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-84.png\" alt=\"\" class=\"wp-image-5187\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-84.png 780w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-84-300x160.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-84-768x411.png 768w\" sizes=\"auto, (max-width: 780px) 100vw, 780px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"780\" height=\"417\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-86.png\" alt=\"\" class=\"wp-image-5189\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-86.png 780w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-86-300x160.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-86-768x411.png 768w\" sizes=\"auto, (max-width: 780px) 100vw, 780px\" \/><\/figure>\n\n\n\n<p>Below is the C++ code of the algorithm used in this example, for reference. Each portion of this code is explained and commented on in the following sections.<\/p>\n\n\n<style>.kt-accordion-id_564463-28 .kt-accordion-inner-wrap{column-gap:var(--global-kb-gap-md, 2rem);row-gap:1px;}.kt-accordion-id_564463-28 .kt-accordion-panel-inner{border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;padding-top:20px;padding-right:20px;padding-bottom:20px;padding-left:20px;}.kt-accordion-id_564463-28 > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header{border-top-color:#f2f2f2;border-right-color:#f2f2f2;border-bottom-color:#f2f2f2;border-left-color:#f2f2f2;border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;font-size:16px;line-height:24px;letter-spacing:0px;font-weight:bold;text-transform:none;color:var(--global-palette3, #1A202C);padding-top:12px;padding-right:10px;padding-bottom:8px;padding-left:16px;}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id_564463-28 > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header:hover, \n\t\t\t\tbody:not(.hide-focus-outline) .kt-accordion-id_564463-28 .kt-blocks-accordion-header:focus-visible{color:#444444;background:#ffffff;border-top-color:#eeeeee;border-right-color:#eeeeee;border-bottom-color:#eeeeee;border-left-color:#eeeeee;}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion--visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#444444;}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger, body:not(.hide-focus-outline) .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger{background:#444444;}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id_564463-28 .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible,\n\t\t\t\t.kt-accordion-id_564463-28 > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active{color:var(--global-palette3, #1A202C);background:var(--global-palette9, #ffffff);border-top-color:var(--global-palette6, #718096);border-right-color:var(--global-palette6, #718096);border-bottom-color:var(--global-palette6, #718096);border-left-color:var(--global-palette6, #718096);}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_564463-28:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette9, #ffffff);}@media all and (max-width: 767px){.kt-accordion-id_564463-28 .kt-accordion-inner-wrap{display:block;}.kt-accordion-id_564463-28 .kt-accordion-inner-wrap .kt-accordion-pane:not(:first-child){margin-top:1px;}}<\/style>\n<div class=\"wp-block-kadence-accordion alignnone\"><div class=\"kt-accordion-wrap kt-accordion-wrap kt-accordion-id_564463-28 kt-accordion-has-3-panes kt-active-pane-0 kt-accordion-block kt-pane-header-alignment-left kt-accodion-icon-style-arrow kt-accodion-icon-side-left\" style=\"max-width:none\"><div class=\"kt-accordion-inner-wrap\" data-allow-multiple-open=\"false\" data-start-open=\"none\">\n<div class=\"wp-block-kadence-pane kt-accordion-pane kt-accordion-pane-1 kt-pane_8dac90-60\"><div class=\"kt-accordion-header-wrap\"><button class=\"kt-blocks-accordion-header kt-acccordion-button-label-show\"><span class=\"kt-blocks-accordion-title-wrap\"><span class=\"kt-blocks-accordion-title\"><strong>PI-based current control in C++ using Vitis HLS<\/strong><\/span><\/span><span class=\"kt-blocks-accordion-icon-trigger\"><\/span><\/button><\/div><div class=\"kt-accordion-panel kt-accordion-panel-hidden\"><div class=\"kt-accordion-panel-inner\"><pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"PiBasedCurrentControl.h\"<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_stream.h&gt; \/\/ hls::stream<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_math.h&gt;   \/\/ hls::signbit<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdint.h&gt;     \/\/ int16_t, uint16_t<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"ap_fixed.h\"<\/span><\/span>\n\n<span class=\"hljs-comment\">\/\/ Duty cycle saturation limits<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">define<\/span> SAT_LIMIT_HIGH 1.0f<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">define<\/span> SAT_LIMIT_LOW  0.0f<\/span>\n\n<span class=\"hljs-comment\">\/\/ Gains for imperix PEB 8038 half-bridge SiC power module<\/span>\n<span class=\"hljs-comment\">\/\/ with a B-Box frontpanel gain value of x4 for all inputs<\/span>\n<span class=\"hljs-keyword\">const<\/span> <span class=\"hljs-keyword\">float<\/span> Gain_Il   = (<span class=\"hljs-number\">10<\/span>\/<span class=\"hljs-number\">32768<\/span>)*<span class=\"hljs-number\">1<\/span>\/(<span class=\"hljs-number\">0.05<\/span>*<span class=\"hljs-number\">4<\/span>);    <span class=\"hljs-comment\">\/\/   50 mV\/A, x4 B-Box gain<\/span>\n<span class=\"hljs-keyword\">const<\/span> <span class=\"hljs-keyword\">float<\/span> Gain_Vin  = (<span class=\"hljs-number\">10<\/span>\/<span class=\"hljs-number\">32768<\/span>)*<span class=\"hljs-number\">1<\/span>\/(<span class=\"hljs-number\">0.00499<\/span>*<span class=\"hljs-number\">4<\/span>); <span class=\"hljs-comment\">\/\/ 4.99 mV\/A, x4 B-Box gain<\/span>\n<span class=\"hljs-keyword\">const<\/span> <span class=\"hljs-keyword\">float<\/span> Gain_Vout = (<span class=\"hljs-number\">10<\/span>\/<span class=\"hljs-number\">32768<\/span>)*<span class=\"hljs-number\">1<\/span>\/(<span class=\"hljs-number\">0.00499<\/span>*<span class=\"hljs-number\">4<\/span>); <span class=\"hljs-comment\">\/\/ 4.99 mV\/A, x4 B-Box gain<\/span>\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">PiBasedCurrentControl<\/span><span class=\"hljs-params\">(hls::stream&lt;<span class=\"hljs-keyword\">int16_t<\/span>&gt;&amp; in_Vin_raw,\n\thls::stream&lt;<span class=\"hljs-keyword\">int16_t<\/span>&gt;&amp; in_Vout_raw,\n\thls::stream&lt;<span class=\"hljs-keyword\">int16_t<\/span>&gt;&amp; in_Il_raw,\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Il_ref,\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Ki,\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Kp,\n\thls::stream&lt;<span class=\"hljs-keyword\">uint32_t<\/span>&gt;&amp; in_Ts,\n\t<span class=\"hljs-keyword\">uint16_t<\/span> in_CLOCK_period,\n\t<span class=\"hljs-keyword\">uint16_t<\/span> &amp;out_duty_cycle_ticks)<\/span>\n<\/span>{\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS TOP name=PiBasedCurrentControl<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Vin_raw<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Vout_raw<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Il_raw<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Il_ref<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Ki<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Kp<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Ts<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE ap_none port=CLOCK_period<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE ap_vld port=duty_cycle_ticks<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE ap_ctrl_none port=return<\/span>\n\n\t<span class=\"hljs-comment\">\/\/ read inputs<\/span>\n\n\t<span class=\"hljs-keyword\">int16_t<\/span> Vin_raw  = in_Vin_raw.read();\n\t<span class=\"hljs-keyword\">int16_t<\/span> Vout_raw = in_Vout_raw.read();\n\t<span class=\"hljs-keyword\">int16_t<\/span> Il_raw   = in_Il_raw.read();\n\t<span class=\"hljs-keyword\">float<\/span>   Il_ref   = in_Il_ref.read();\n\t<span class=\"hljs-keyword\">float<\/span>   Ki       = in_Ki.read();\n\t<span class=\"hljs-keyword\">float<\/span>   Kp       = in_Kp.read();\n\t<span class=\"hljs-keyword\">float<\/span>   Ts_ns    = (<span class=\"hljs-keyword\">float<\/span>) in_Ts.read();\n\n\t<span class=\"hljs-comment\">\/\/ apply ADC gains<\/span>\n\n\t<span class=\"hljs-keyword\">float<\/span> Vin  = Gain_Vin  * (<span class=\"hljs-keyword\">float<\/span>)Vin_raw;\n\t<span class=\"hljs-keyword\">float<\/span> Il   = Gain_Il   * (<span class=\"hljs-keyword\">float<\/span>)Il_raw;\n\t<span class=\"hljs-keyword\">float<\/span> Vout = Gain_Vout * (<span class=\"hljs-keyword\">float<\/span>)Vout_raw;\n\n\t<span class=\"hljs-comment\">\/\/ transform from nanoseconds to seconds<\/span>\n\n\t<span class=\"hljs-keyword\">float<\/span> Ts = Ts_ns * <span class=\"hljs-number\">1e-9<\/span>f;\n\n\t<span class=\"hljs-comment\">\/\/ error<\/span>\n\n\t<span class=\"hljs-keyword\">float<\/span> err = Il_ref - Il;\n\n\t<span class=\"hljs-comment\">\/\/ PI<\/span>\n\n\t<span class=\"hljs-keyword\">static<\/span> <span class=\"hljs-keyword\">float<\/span> accumulator = <span class=\"hljs-number\">0<\/span>;\n\t<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS RESET variable=accumulator<\/span>\n\n\t<span class=\"hljs-keyword\">static<\/span> <span class=\"hljs-keyword\">bool<\/span> saturation = <span class=\"hljs-literal\">false<\/span>;\n\t<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS RESET variable=saturation<\/span>\n\n\t<span class=\"hljs-keyword\">float<\/span> Ki_times_Ts = Ki*Ts;\n\t<span class=\"hljs-keyword\">bool<\/span> if_same_sign = hls::signbit(accumulator) == hls::signbit(err);\n\t<span class=\"hljs-keyword\">bool<\/span> clamping = if_same_sign &amp; saturation;\n\n\t<span class=\"hljs-keyword\">if<\/span>(!clamping) {\n\t\taccumulator += Ki_times_Ts*err;\n\t}\n\n\t<span class=\"hljs-keyword\">float<\/span> pi_result = accumulator + Kp*err;\n\n\t<span class=\"hljs-comment\">\/\/ Duty cycle computation<\/span>\n\n\t<span class=\"hljs-keyword\">float<\/span> duty_cycle = (Vout + pi_result) \/ Vin;\n\n\t<span class=\"hljs-keyword\">if<\/span> (duty_cycle &gt; SAT_LIMIT_HIGH) {\n\t\tduty_cycle = SAT_LIMIT_HIGH;\n\t\tsaturation = <span class=\"hljs-literal\">true<\/span>;\n\t} <span class=\"hljs-keyword\">else<\/span> <span class=\"hljs-keyword\">if<\/span> (duty_cycle &lt;= SAT_LIMIT_LOW) {\n\t\tduty_cycle = SAT_LIMIT_LOW;\n\t\tsaturation = <span class=\"hljs-literal\">true<\/span>;\n\t}\n\t<span class=\"hljs-keyword\">else<\/span>\n\t{\n\t\tsaturation = <span class=\"hljs-literal\">false<\/span>;\n\t}\n\n\t<span class=\"hljs-comment\">\/\/ Transform duty cycle in a value in ticks<\/span>\n\t<span class=\"hljs-comment\">\/\/ The PWM carrier varies between \"0\" and \"in_CLOCK_period\" ticks<\/span>\n\t<span class=\"hljs-comment\">\/\/ so the duty_cycle_ticks must have the same range<\/span>\n\n\tap_fixed&lt;<span class=\"hljs-number\">17<\/span>,<span class=\"hljs-number\">1<\/span>&gt; duty_fixed = duty_cycle;\n\tout_duty_cycle_ticks = (<span class=\"hljs-keyword\">uint16_t<\/span>) (duty_fixed*in_CLOCK_period);\n}\n<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre><\/div><\/div><\/div>\n<\/div><\/div><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-defining-the-ip-input-and-output-ports\"><span class=\"ez-toc-section\" id=\"Defining-the-IP-input-and-output-ports\"><\/span>Defining the IP input and output ports<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The code below defines the inputs and outputs of the IP. We made the following choices:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Data types:<ul><li>The parameters coming from the CPU (<code>Il_ref<\/code>, <code>Kp<\/code> and <code>Ki<\/code>) are set as <em>single-precision<\/em> (float).<\/li><li>The inputs <code>Il_raw<\/code>, <code>Vin_raw<\/code> and <code>Vout_raw<\/code> will be directly connected to the ADC interfaces and as such must be set as <em>int16<\/em>.<\/li><li>The input <code>Ts<\/code> is a <em>uint32<\/em> value holding the sampling time in nanoseconds.<\/li><li>The input <code>CLOCK_period<\/code> is a <em>uint16 <\/em>value representing the PWM period in ticks.<\/li><li>The output <code>duty_cycle_ticks<\/code> is a <em>uint16 <\/em>value that will be connected to the PWM IP.<\/li><\/ul><\/li><li>Interfaces<ul><li>After the user CPU code starts, the <code>CLOCK_period <\/code>input is constant. Thus its mode is set as <em>ap_none<\/em> (No protocol).<\/li><li>The <code>duty_cycle_ticks<\/code> output uses the <em>ap_vld<\/em> (Valid Port) mode. As shown on the very last image of this page, it will generate an additionnal &#8220;valid&#8221; port <code>duty_cycle_ticks_ap_vld<\/code> indicating when the <code>duty_cycle_ticks<\/code> can be read.<\/li><li>All the other inputs use the <em>AXI4-Stream<\/em> protocol.<\/li><\/ul><\/li><\/ul>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-2\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">PiBasedCurrentControl<\/span><span class=\"hljs-params\">(hls::stream&lt;<span class=\"hljs-keyword\">int16_t<\/span>&gt;&amp; in_Vin_raw,\n\thls::stream&lt;<span class=\"hljs-keyword\">int16_t<\/span>&gt;&amp; in_Vout_raw,\n\thls::stream&lt;<span class=\"hljs-keyword\">int16_t<\/span>&gt;&amp; in_Il_raw,\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Il_ref,\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Ki,\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Kp,\n\thls::stream&lt;<span class=\"hljs-keyword\">uint32_t<\/span>&gt;&amp; in_Ts,\n\t<span class=\"hljs-keyword\">uint16_t<\/span> in_period,\n\t<span class=\"hljs-keyword\">uint16_t<\/span> &amp;out_dutycycle)<\/span>\n<\/span>{\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS TOP name=PiBasedCurrentControl<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Vin_raw<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Vout_raw<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Il_raw<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Il_ref<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Ki<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Kp<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Ts<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE ap_none port=CLOCK_period<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE ap_vld port=duty_cycle_ticks<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE ap_ctrl_none port=return<\/span>\n\n    <span class=\"hljs-comment\">\/\/ implementation...<\/span>\n\n}<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-2\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<h2 class=\"wp-block-heading\" id=\"h-implementing-the-algorithm\"><span class=\"ez-toc-section\" id=\"Implementing-the-algorithm\"><\/span>Implementing the algorithm<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The algorithm implemented in this example is the same as the one in the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer introduction<\/a>. Taking a look at that page may help to understand the algorithm.<\/p>\n\n\n\n<p>The <code>read()<\/code> method reads one value from an AXI4-Stream. The algorithm starts by reading all the stream inputs. The <code>Ts<\/code> input is multiplied by 1e-9 to obtain a value in seconds.<\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-3\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-keyword\">int16_t<\/span> Vin_raw = in_Vin_raw.read();\n<span class=\"hljs-keyword\">int16_t<\/span> Vout_raw = in_Vout_raw.read();\n<span class=\"hljs-keyword\">int16_t<\/span> Il_raw = in_Il_raw.read();\n<span class=\"hljs-keyword\">float<\/span> Il_ref = in_Il_ref.read();\n<span class=\"hljs-keyword\">float<\/span> Ki = in_Ki.read();\n<span class=\"hljs-keyword\">float<\/span> Kp = in_Kp.read();\n<span class=\"hljs-keyword\">float<\/span> Ts_ns = (<span class=\"hljs-keyword\">float<\/span>) in_Ts.read();\n<span class=\"hljs-keyword\">float<\/span> Ts = Ts_ns * <span class=\"hljs-number\">1e-9<\/span>f;<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-3\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<p>The ADC values provided by the starter template are the raw result from the ADC chips. They must be multiplied by a <em>gain <\/em>to obtain physical values. An example of <em>gain<\/em> computation is available on the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC block<\/a> help page. To simplify the model, the ADC gains are defined as constants and offsets are simply ignored. This example considers the sensor sensitivities of a <a href=\"https:\/\/imperix.com\/products\/power\/half-bridge-module\/\">PEB 8038<\/a> module. The user could choose to use tunable parameters coming from the CPU so that the ADC can be tuned in real-time.<\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-4\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-comment\">\/\/ Gains for imperix PEB 8038 half-bridge SiC power module<\/span>\n<span class=\"hljs-comment\">\/\/ with a B-Box frontpanel gain value of x4 for all inputs<\/span>\n<span class=\"hljs-keyword\">const<\/span> <span class=\"hljs-keyword\">float<\/span> Gain_Il   = <span class=\"hljs-number\">10<\/span>\/<span class=\"hljs-number\">32768<\/span>*<span class=\"hljs-number\">1<\/span>\/(<span class=\"hljs-number\">0.05<\/span>*<span class=\"hljs-number\">4<\/span>); <span class=\"hljs-comment\">\/\/50 mV\/A, x4 frontpanel gain<\/span>\n<span class=\"hljs-keyword\">const<\/span> <span class=\"hljs-keyword\">float<\/span> Gain_Vin  = <span class=\"hljs-number\">10<\/span>\/<span class=\"hljs-number\">32768<\/span>*<span class=\"hljs-number\">1<\/span>\/(<span class=\"hljs-number\">0.00499<\/span>*<span class=\"hljs-number\">4<\/span>); <span class=\"hljs-comment\">\/\/4.99 mV\/A, x4 frontpanel gain<\/span>\n<span class=\"hljs-keyword\">const<\/span> <span class=\"hljs-keyword\">float<\/span> Gain_Vout = <span class=\"hljs-number\">10<\/span>\/<span class=\"hljs-number\">32768<\/span>*<span class=\"hljs-number\">1<\/span>\/(<span class=\"hljs-number\">0.00499<\/span>*<span class=\"hljs-number\">4<\/span>); <span class=\"hljs-comment\">\/\/4.99 mV\/A, x4 frontpanel gain<\/span>\n\n<span class=\"hljs-keyword\">float<\/span> Il   = Gain_Il   * (<span class=\"hljs-keyword\">float<\/span>)Il_raw;\n<span class=\"hljs-keyword\">float<\/span> Vin  = Gain_Vin  * (<span class=\"hljs-keyword\">float<\/span>)Vin_raw;\n<span class=\"hljs-keyword\">float<\/span> Vout = Gain_Vout * (<span class=\"hljs-keyword\">float<\/span>)Vout_raw;<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-4\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<p>The integrator of the PI controller acts as an accumulator and, thus, requires that its value is kept in memory between executions. To that end, the <em>static<\/em> keyword must be used. The HLS RESET pragma specifies that this variable is reset when the IP block reset input pin (<code>ap_rst_n<\/code>) is asserted.<\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-5\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-keyword\">static<\/span> <span class=\"hljs-keyword\">float<\/span> accumulator = <span class=\"hljs-number\">0<\/span>;\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS RESET variable=accumulator<\/span><\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-5\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<p>By design, the <code>duty_cycle<\/code> ranges from 0.0 to 1.0. Such a narrow range is particularly well-suited for a fixed-point algorithm, as we know beforehand that only a single bit is required for the integer part. We arbitrarily choose a fractional length of 15 bits so we obtain a <em>fix16_1<\/em>5 value. Since the output is a number of <em>ticks<\/em>, it must be an integer value, and the fractional part is removed by simply transforming the result into a <em>uint16<\/em>.<\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-6\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">define<\/span> SAT_LIMIT_HIGH 1.0f<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">define<\/span> SAT_LIMIT_LOW  0.0f<\/span>\n\n<span class=\"hljs-comment\">\/\/ some code... <\/span>\n\n<span class=\"hljs-keyword\">float<\/span> duty_cycle = (Vout + pi_result) \/ Vin;\n\n<span class=\"hljs-keyword\">if<\/span> (duty_cycle &gt; SAT_LIMIT_HIGH) {\n\tduty_cycle = SAT_LIMIT_HIGH;\n\tsaturation = <span class=\"hljs-literal\">true<\/span>;\n} <span class=\"hljs-keyword\">else<\/span> <span class=\"hljs-keyword\">if<\/span> (duty_cycle &lt;= SAT_LIMIT_LOW) {\n\tduty_cycle = SAT_LIMIT_LOW;\n\tsaturation = <span class=\"hljs-literal\">true<\/span>;\n}\n<span class=\"hljs-keyword\">else<\/span>\n{\n\tsaturation = <span class=\"hljs-literal\">false<\/span>;\n}\n<span class=\"hljs-comment\">\/\/ Width = 16 bits, integer part = 1 bit<\/span>\nap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">1<\/span>&gt; duty_fixed = duty_cycle;\n\nout_dutycycle = (<span class=\"hljs-keyword\">uint16_t<\/span>) (duty_fixed*in_period);\n<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-6\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<h3 class=\"wp-block-heading\" id=\"h-generating-an-ip-core-using-vitis-hls\"><span class=\"ez-toc-section\" id=\"Generating-an-IP-core-using-Vitis-HLS\"><\/span>Generating an IP core using Vitis HLS<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li>Launch the C Synthesis by going to <strong>Solution <\/strong>-&gt; <strong>Run C Synthesis<\/strong> -&gt; <strong>Active Solution<\/strong><\/li><\/ul>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"780\" height=\"417\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-87.png\" alt=\"\" class=\"wp-image-5190\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-87.png 780w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-87-300x160.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-87-768x411.png 768w\" sizes=\"auto, (max-width: 780px) 100vw, 780px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\"><li>Once the synthesis is done, export the RTL using the Vivado IP format<ul><li>Click <strong>Solution <\/strong>-&gt; <strong>Export RTL<\/strong>,<\/li><li>Select the <em>Vivado IP (.zip)<\/em> format.<\/li><li>The generated RTL can be VHDL or Verilog, it does not matter.<\/li><li>Choose an output location, for instance <code><code>C:\/KB\/PN163\/Generated\/IP<\/code><\/code>,<\/li><\/ul><ul><li>Click <strong>OK<\/strong>.<br><\/li><\/ul><\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"536\" height=\"377\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-89.png\" alt=\"\" class=\"wp-image-5192\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-89.png 536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-89-300x211.png 300w\" sizes=\"auto, (max-width: 536px) 100vw, 536px\" \/><\/figure><\/div>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-performance-and-resource-estimates\">Performance and resource estimates<\/h4>\n\n\n\n<p>The FPGA of imperix controllers (part: xc7z030fbg676-3) possesses 78600 LUT, 157200 FF and 400 DSP, from which around ~30% is used by the imperix firmware IP. By clicking on Solution -&gt; Open Report -&gt; Synthesis, the user has access to the <strong>synthesis summary report<\/strong> which estimates the IP latency and resource usage.  In this example, Vitis HLS shows the following estimation: 2624 LUT (3.3% of total), 2211 FF (1.4%), and 9 DSP (2.3%).<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"855\" height=\"315\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-91.png\" alt=\"\" class=\"wp-image-5194\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-91.png 855w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-91-300x111.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-91-768x283.png 768w\" sizes=\"auto, (max-width: 855px) 100vw, 855px\" \/><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The tool generates a warning if it thinks a timing violation may occur. However, this is only an estimation. Experience has shown that Xilinx Vitis HLS always generates a timing violation warning when using an integer to floating-point conversion (<em>uitofp <\/em>operation) and a target period of 4 ns. However, when implementing the full FPGA design, Vivado still reaches successful timing closure.<\/div>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-adding-the-ip-core-in-a-vivado-project\">Adding the IP core in a Vivado project<\/h4>\n\n\n\n<p>Here are the steps required to add the example IP generated by Xilinx Vitis HLS into a Vivado project.<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Unzip the file generated by Xilinx Vitis HLS (PiBasedCurrentControl.zip),<\/li><li>Go in the IP Catalog,<\/li><li>Right-click and select Add Repository&#8230;<\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-82.png\" alt=\"\"\/><\/figure><\/div>\n\n\n\n<ul class=\"wp-block-list\"><li>Select the folder containing your unzipped IP (e.g. <code>C:\\imperix\\sandbox_sources\\my_IPs<\/code>). This folder can contain multiple IPs.<\/li><li>And finally the IP can be added to a block design like any other Xilinx IP<\/li><\/ul>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"419\" height=\"285\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-92.png\" alt=\"Example IP generated by Xilinx Vitis HLS\" class=\"wp-image-5195\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-92.png 419w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-92-300x204.png 300w\" sizes=\"auto, (max-width: 419px) 100vw, 419px\" \/><figcaption>Example IP generated by Xilinx Vitis HLS<\/figcaption><\/figure><\/div>\n\n\n\n<p>To see an example where the PI-based current control IP in action please refer to the <a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">high-Level Synthesis for FPGA developments<\/a> page.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>Xilinx Vitis HLS (formerly Xilinx Vivado HLS) is a High-Level Synthesis (HLS) tool developed by Xilinx and available at no cost. Vitis HLS allows the&#8230;<\/p>\n","protected":false},"author":4,"featured_media":7234,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[105,106],"provided-results":[],"related-products":[50,31,32,92,166,51,110],"guidedreadings":[],"tutorials":[130],"user-manuals":[],"coauthors":[70],"class_list":["post-3184","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-c-plus-plus","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-cpp-sdk","related-products-tpi","tutorials-custom-fpga-pwm-modulator-implementation"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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