{"id":3190,"date":"2021-06-02T11:33:54","date_gmt":"2021-06-02T11:33:54","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3190"},"modified":"2025-05-07T09:26:44","modified_gmt":"2025-05-07T09:26:44","slug":"matlab-hdl-coder","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder","title":{"rendered":"Introduction to HDL Coder"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\/#Intended-use-and-alternatives-to-HDL-Coder\" >Intended use and alternatives to HDL Coder<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\/#Licensing-and-installation-of-MATLAB-HDL-Coder\" >Licensing and installation of MATLAB HDL Coder<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\/#Typical-MATLAB-HDL-Coder-workflow\" >Typical MATLAB HDL Coder workflow<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\/#Implementing-a-design-using-HDL-Coder\" >Implementing a design using HDL Coder<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\/#Testing-a-design-in-simulation\" >Testing a design in simulation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\/#Generating-RTL-code-using-MATLAB-HDL-Coder\" >Generating RTL code using MATLAB HDL Coder<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\/#Adding-the-module-to-a-Vivado-project\" >Adding the module to a Vivado project<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p><strong>HDL Coder<\/strong> is a MATLAB add-on that can generate VHDL and Verilog code from MATLAB functions or Simulink models. This approach can greatly accelerate rapid prototyping as the design is performed from a higher level of abstraction. The second benefit is the possibility of simulating the FPGA logic directly from within Simulink.<\/p>\n\n\n\n<p>A typical use case for HDL Coder is the implementation of a custom PWM modulator for the <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a> power converter controller.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0the <a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-intended-use-and-alternatives-to-hdl-coder\"><span class=\"ez-toc-section\" id=\"Intended-use-and-alternatives-to-HDL-Coder\"><\/span>Intended use and alternatives to HDL Coder<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>An alternative to HDL Coder is <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\">System Generator<\/a>, another Simulink add-on that works very similarly. The main difference between System Generator and HDL Coder is that System Generator targets exclusively Xilinx devices. As such, it generates pre-packaged core IPs that can easily be imported into Vivado. Moreover, System Generator is bundled with <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a>, another FPGA development blockset that provides additional features that HDL Coder does not have.<\/p>\n\n\n\n<p>Compared to high-level synthesis tools such as <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> (Simulink) and <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a><strong> <\/strong>(C++), System Generator and HDL Coder are \u201clower-level\u201d design tools intended for architecture-level designs, down to the flip-flop register. MATLAB HDL Coder allows finer control over the resulting HDL code and is more adapted for peripheral designs (e.g. <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">PWM modulator<\/a> or <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-spi-communication-ip\">SPI communication controller<\/a>). Unlike Model Composer and Vitis HLS, System Generator does not support AXI4-Stream interfaces.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-licensing-and-installation-of-matlab-hdl-coder\"><span class=\"ez-toc-section\" id=\"Licensing-and-installation-of-MATLAB-HDL-Coder\"><\/span>Licensing and installation of MATLAB HDL Coder<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>HDL Coder is a paid add-on for MATLAB, which also required the Fixed-Point Designer add-on, as well as the MATLAB Coder add-on.<\/p>\n\n\n\n<p>Installing HDL Coder is straightforward: open a MATLAB session, go to the <strong>HOME<\/strong> tab and click on <strong>Add-Ons<\/strong>. Search for <strong>HDL Coder<\/strong> and hit install. The same process applies to <strong>Fixed-Point Designer<\/strong> and <strong>MATLAB Coder<\/strong>.<\/p>\n\n\n\n<p>After the installation has finished, the HDL Coder library is available in the Simulink libraries. The command <code>help hdlcoder<\/code> may be used in the <em>Command Window<\/em>.<\/p>\n\n\n\n<p>The <a href=\"https:\/\/fr.mathworks.com\/help\/deep-learning-hdl\/ref\/hdlsetuptoolpath.html\">hdlsetuptoolpath<\/a> command must be entered in the MATLAB Command Window to setup the FPGA synthesis software. The path must be edited to match the installed Vivado version.<\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"Matlab\" data-shcb-language-slug=\"matlab\"><span><code class=\"hljs language-matlab\">hdlsetuptoolpath(<span class=\"hljs-string\">'ToolName'<\/span>, <span class=\"hljs-string\">'Xilinx Vivado'<\/span>,  <span class=\"hljs-string\">'ToolPath'<\/span>, <span class=\"hljs-string\">'C:\\Xilinx\\Vivado\\20xx.x\\bin\\vivado.bat'<\/span>);<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">Matlab<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">matlab<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"884\" height=\"107\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlsetuptoolpath.png\" alt=\"\" class=\"wp-image-3800\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlsetuptoolpath.png 884w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlsetuptoolpath-300x36.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlsetuptoolpath-768x93.png 768w\" sizes=\"auto, (max-width: 884px) 100vw, 884px\" \/><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-typical-matlab-hdl-coder-workflow\"><span class=\"ez-toc-section\" id=\"Typical-MATLAB-HDL-Coder-workflow\"><\/span>Typical MATLAB HDL Coder workflow<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This section broadly outlines the main steps required to generate VHDL or Verilog sources using MATLAB HDL Coder. For more detailed information the user should refer to the official documentation of which some are listed below:<\/p>\n\n\n\n<ul class=\"wp-block-list\" id=\"block-b69c4084-efab-4a11-ae2d-6d6b2d586d8f\"><li><a href=\"https:\/\/www.mathworks.com\/help\/pdf_doc\/hdlcoder\/hdlcoder_gs.pdf\">HDL Coder Getting Started Guide (mathworks.com)<\/a><\/li><li><a href=\"https:\/\/www.mathworks.com\/help\/pdf_doc\/hdlcoder\/hdlcoder_ug.pdf\">HDL Coder User&#8217;s Guide (mathworks.com)<\/a><\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-implementing-a-design-using-hdl-coder\"><span class=\"ez-toc-section\" id=\"Implementing-a-design-using-HDL-Coder\"><\/span>Implementing a design using HDL Coder<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The screenshot below shows an example of a MATLAB HDL Coder design taken from the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">custom FPGA PWM modulator<\/a> page. This example will be used as a support to illustrate the key points of the MATLAB HDL Coder workflow. The sources are available in the zip below.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"583\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm-1024x583.png\" alt=\"PWM implementation on FPGA using MATLAB HDL Coder\" class=\"wp-image-3804\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm-1024x583.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm-300x171.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm-768x438.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm.png 1055w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>PWM implementation on FPGA using MATLAB HDL Coder<\/figcaption><\/figure>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/PN162_HDL_Coder_PWM.zip\" class=\"wp-block-file__button\" download>Download <strong>PN162_HDL_Coder_PWM<\/strong>.zip<\/a><\/div>\n\n\n\n<p>The user creates the design using HDL Coder blocks (available in the Simulink library browser) as illustrated above. The logic must be placed within a <em>subsystem<\/em>. <\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<p>The input and output types are set as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li><strong><em>i_nextDutyCycle<\/em><\/strong>, <strong><em>CLOCK_period<\/em><\/strong>, <strong><em>CLOCK_prescaler <\/em><\/strong>: 16-bit unsigned integer (Data type: uint16)<\/li><li><em><strong>CLOCK_clk_en<\/strong><\/em>, <strong><em>i_UpdateRate<\/em><\/strong>: 1-bit (Data type: boolean)<\/li><\/ul>\n\n\n\n<p>In HDL Coder, there is no model for the clock signal in FPGA. Instead, the sample period of the Simulink signals represents the FPGA clock signal period. In the FPGA PWM example, the <em>clk_250_mhz <\/em>output is used, which corresponds to a period of 4 ns.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\">\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/dutycycle_input_config.png\" alt=\"\" class=\"wp-image-3803\" width=\"251\" height=\"355\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/dutycycle_input_config.png 464w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/dutycycle_input_config-212x300.png 212w\" sizes=\"auto, (max-width: 251px) 100vw, 251px\" \/><\/figure>\n<\/div>\n<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-testing-a-design-in-simulation\"><span class=\"ez-toc-section\" id=\"Testing-a-design-in-simulation\"><\/span>Testing a design in simulation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>An HDL design can be validated using a test bench that uses standard Simulink blocks. Below is shown an example of a testbench, which is further documented in the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">FPGA-based PWM modulator example<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"341\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm_tb-1024x341.png\" alt=\"HDL Coder testbench for FPGA PWM\" class=\"wp-image-3805\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm_tb-1024x341.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm_tb-300x100.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm_tb-768x256.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/hdlcoder_pwm_tb.png 1117w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>HDL Coder testbench for FPGA PWM<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-5.png\" alt=\"\"\/><figcaption>Simulation result of a Pulse Width Modulator using MATLAB HDL Coder<\/figcaption><\/figure><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-generating-rtl-code-using-matlab-hdl-coder\"><span class=\"ez-toc-section\" id=\"Generating-RTL-code-using-MATLAB-HDL-Coder\"><\/span>Generating RTL code using MATLAB HDL Coder<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<ol class=\"wp-block-list\"><li>Go to <strong>Apps<\/strong> and click on <strong>HDL Coder<\/strong>.<\/li><li>Click on <strong>Workflow Advisor<\/strong>.<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"897\" height=\"118\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-109.png\" alt=\"Toolbar of MATLAB HDL Coder\" class=\"wp-image-3449\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-109.png 897w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-109-300x39.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-109-768x101.png 768w\" sizes=\"auto, (max-width: 897px) 100vw, 897px\" \/><\/figure>\n\n\n\n<ol class=\"wp-block-list\" start=\"3\"><li>In the pop-up window, select<ul><li><strong>Generic ASIC\/FPGA<\/strong> as target workflow,<\/li><li><strong>Xilinx Vivado<\/strong> as synthesis tool,<\/li><li><strong>Zynq xc7z030fbg676-3<\/strong> as device.<\/li><\/ul><\/li><li>Set a correct project folder. <\/li><li>Click on <strong>Run This Task<\/strong>.<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"751\" height=\"579\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-51.png\" alt=\"\" class=\"wp-image-4915\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-51.png 751w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-51-300x231.png 300w\" sizes=\"auto, (max-width: 751px) 100vw, 751px\" \/><\/figure>\n\n\n\n<ol class=\"wp-block-list\" start=\"6\"><li>Set the target frequency to <strong>250MHz<\/strong>.<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"751\" height=\"410\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-52.png\" alt=\"\" class=\"wp-image-4916\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-52.png 751w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-52-300x164.png 300w\" sizes=\"auto, (max-width: 751px) 100vw, 751px\" \/><\/figure>\n\n\n\n<ol class=\"wp-block-list\" start=\"7\"><li>Run the rest of the tasks until <strong>3.1.3 Set Advanced Options<\/strong>. There, set Reset asserted level to <strong>Active-low<\/strong>.<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"752\" height=\"682\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-61.png\" alt=\"\" class=\"wp-image-4927\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-61.png 752w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-61-300x272.png 300w\" sizes=\"auto, (max-width: 752px) 100vw, 752px\" \/><\/figure>\n\n\n\n<ol class=\"wp-block-list\" start=\"8\"><li>Run the rest of the tasks, until <strong>3.2. Generate RTL Code and Testbench<\/strong> finishes.<br>Do not run synthesis now, since we use MATLAB HDL Coder only to generate the RTL sources. The synthesis will be performed by Vivado.<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"991\" height=\"706\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-123.png\" alt=\"\" class=\"wp-image-3482\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-123.png 991w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-123-300x214.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-123-768x547.png 768w\" sizes=\"auto, (max-width: 991px) 100vw, 991px\" \/><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">You can use the option <a target=\"_blank\" rel=\"noreferrer noopener\" href=\"https:\/\/www.mathworks.com\/help\/hdlcoder\/ug\/minimize-clock-enables-and-reset-signals.html\">Minimize Clock Enables<\/a> to remove the clock enable port under<br>HDL Code Generation -> Global Settings -> Ports -> Minimize clock enables (check this box).<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-adding-the-module-in-a-vivado-project\"><span class=\"ez-toc-section\" id=\"Adding-the-module-to-a-Vivado-project\"><\/span>Adding the module to a Vivado project<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Unlike System Generator, MATLAB HDL Coder does not generate a Vivado IP directly. Instead, the generated RTL sources must be added to Vivado.<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>In Vivado, right-click on the Design Sources and select Add Sources<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-53.png\" alt=\"\" class=\"wp-image-4917\" width=\"300\" height=\"299\"\/><figcaption>Adding RTL sources to an existing Vivado project<\/figcaption><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"2\"><li>Browse into the generated folders and select the source files<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-56.png\" alt=\"\" class=\"wp-image-4920\" width=\"541\" height=\"339\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-56.png 721w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-56-300x188.png 300w\" sizes=\"auto, (max-width: 541px) 100vw, 541px\" \/><figcaption>Selecting sources files for integration within an existing Vivado project<\/figcaption><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"3\"><li>Give Vivado some time to update its sources hierarchy<\/li><li>Finally, the module can be added to the block design:<ul><li>by doing a right-click and selecting Add Module&#8230;<\/li><li>or by directly drag-and-dropping the design source<br><\/li><\/ul><\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"351\" height=\"343\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-58.png\" alt=\"\" class=\"wp-image-4922\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-58.png 351w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-58-300x293.png 300w\" sizes=\"auto, (max-width: 351px) 100vw, 351px\" \/><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"313\" height=\"322\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-60.png\" alt=\"FPGA PWM generated by MATLAB HDL Coder\" class=\"wp-image-4924\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-60.png 313w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-60-292x300.png 292w\" sizes=\"auto, (max-width: 313px) 100vw, 313px\" \/><figcaption>FPGA PWM generated by MATLAB HDL Coder<\/figcaption><\/figure><\/div>\n\n\n\n<p>A step-by-step example explaining how to integrate the PWM modulator IP in a Vivado project is available on the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">FPGA PWM modulator<\/a> page.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>HDL Coder is a MATLAB add-on that can generate VHDL and Verilog code from MATLAB functions or Simulink models. This approach can greatly accelerate rapid&#8230;<\/p>\n","protected":false},"author":10,"featured_media":7240,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106,103],"provided-results":[107],"related-products":[31,32,92,166,110],"guidedreadings":[],"tutorials":[179,130],"user-manuals":[],"coauthors":[72],"class_list":["post-3190","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","software-environments-matlab","provided-results-simulation","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","tutorials-automated-tools-for-fpga-developments","tutorials-custom-fpga-pwm-modulator-implementation"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - 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