{"id":3199,"date":"2021-06-02T11:40:35","date_gmt":"2021-06-02T11:40:35","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3199"},"modified":"2025-12-31T10:52:20","modified_gmt":"2025-12-31T10:52:20","slug":"fpga-based-inverter-control","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control","title":{"rendered":"FPGA-based control of a grid-tied inverter"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Grid-tied-inverter-control\" >Grid-tied inverter control<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Overview-of-the-FPGA-based-inverter-control-task\" >Overview of the FPGA-based inverter control task<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Performance-analysis-of-the-control-task\" >Performance analysis of the control task<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Latency-and-control-delay\" >Latency and control delay<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Resource-utilization\" >Resource utilization<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Experimental-validation\" >Experimental validation<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Testbench-description\" >Testbench description<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Experimental-results\" >Experimental results<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Creation-of-the-Vivado-block-design\" >Creation of the Vivado block design<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Raw-ADC-data-conversion\" >Raw ADC data conversion<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Sample-time-Ts-conversion\" >Sample time (Ts) conversion<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Grid-synchronization\" >Grid synchronization<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#DQ-current-control\" >DQ current control<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Duty-cycles-computation\" >Duty cycles computation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-15\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#PWM-generation\" >PWM generation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-16\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#CPU-side-implementation\" >CPU-side implementation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-17\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\/#Debugging-and-monitoring\" >Debugging and monitoring<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p>This note presents an FPGA control implementation of a <strong>grid-tied current-controlled inverter<\/strong>. It combines several control modules presented in different Technical Notes to form a complete converter control, executed entirely in the FPGA of a <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a> controller.<\/p>\n\n\n\n<p>Thanks to the <a href=\"https:\/\/imperix.com\/software\/fpga-programming\/\">FPGA programmability<\/a> of the B-Box controller, complex control algorithms can be effectively executed at high rates and with minimal latency. In particular, this example shows that a grid-oriented current control algorithm can be executed as fast as 650 kHz, whereas the equivalent CPU-based execution is &#8220;limited&#8221; to 210 kHz (which is already an industry-leading figure amongst prototyping controllers).<\/p>\n\n\n\n<p>Besides, the fast switching frequency used in this example takes full advantage of the imperix <a href=\"https:\/\/imperix.com\/products\/power\/sic-power-module\/\">SiC phase leg module<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-grid-tied-inverter-control\"><span class=\"ez-toc-section\" id=\"Grid-tied-inverter-control\"><\/span>Grid-tied inverter control<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The controlled system is a standard current-controlled voltage-source inverter, connected to a 3-phase grid. This converter is built using imperix power modules in the <a href=\"#h-experimental-validation\">experimental validation<\/a> section.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"558\" height=\"269\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Converter_scheme_v2_100pc.png\" alt=\"Grid-tied voltage-source inverter controlled by an FPGA\" class=\"wp-image-12462\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Converter_scheme_v2_100pc.png 558w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Converter_scheme_v2_100pc-300x145.png 300w\" sizes=\"auto, (max-width: 558px) 100vw, 558px\" \/><figcaption class=\"wp-element-caption\">Grid-tied voltage-source inverter<\/figcaption><\/figure>\n<\/div>\n\n\n<p>The control algorithm is entirely executed in the controller FPGA and implements a <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-implementation-pll\">three-phase PLL<\/a> for grid synchronization coupled to a standard <a href=\"https:\/\/imperix.com\/doc\/implementation\/vector-current-control\">dq current control<\/a> in the grid-oriented reference frame. Based on user-defined current references, the controller computes the voltages that the inverter should produce in order to match the required current. These voltages are then modulated in PWM signals and fed to the gates of the inverter.<\/p>\n\n\n\n<p>The overall inverter control algorithm is shown below, and each of the elementary control blocks is further described in the following sections.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"799\" height=\"502\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/Block_diagram_CPU_FPGA_100pc.png\" alt=\"Block diagram of the implemented FPGA-based control algorithm (simplified view)\" class=\"wp-image-10277\" style=\"width:799px;height:502px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/Block_diagram_CPU_FPGA_100pc.png 799w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/Block_diagram_CPU_FPGA_100pc-300x188.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/Block_diagram_CPU_FPGA_100pc-768x483.png 768w\" sizes=\"auto, (max-width: 799px) 100vw, 799px\" \/><figcaption class=\"wp-element-caption\">Block diagram of the implemented FPGA-based control algorithm (simplified view)<\/figcaption><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-overview-of-the-fpga-based-inverter-control-task\"><span class=\"ez-toc-section\" id=\"Overview-of-the-FPGA-based-inverter-control-task\"><\/span>Overview of the FPGA-based inverter control task<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Below is shown the implemented Vivado block design used to generate the FPGA bitstream. The <a href=\"#Creation-of-the-Vivado-block-design\">creation of the Vivado block design<\/a> section describes in more detail how to reproduce this block design. All the sources can be downloaded by clicking on the button below.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"3652\" height=\"911\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-12.png\" alt=\"Vivado screenshot of the FPGA control algorithm\" class=\"wp-image-12306\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-12.png 3652w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-12-300x75.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-12-1024x255.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-12-768x192.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-12-1536x383.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-12-2048x511.png 2048w\" sizes=\"auto, (max-width: 3652px) 100vw, 3652px\" \/><\/figure>\n\n\n\n<div style=\"height:10px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/TN147_block_design.pdf\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>TN147_block_design.pdf<\/strong><\/a><\/div>\n\n\n\n<p>The design uses the following IPs<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>ADC conversion<\/strong> module (Vitis HLS)<\/li>\n\n\n\n<li><strong>Ts conversion<\/strong> module (Vitis HLS)<\/li>\n\n\n\n<li><strong>Grid synchronization<\/strong> module (Vitis HLS or Model Composer, documented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-implementation-pll\">TN143<\/a>)<\/li>\n\n\n\n<li><strong>Dq current controller<\/strong> (Vitis HLS or Model Composer, documented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\">TN144<\/a>)<\/li>\n\n\n\n<li><strong>duty cycle computation<\/strong> module (Vitis HLS)<\/li>\n\n\n\n<li><strong>Carrier-based PWM<\/strong> module (System Generator or HDL Coder, documented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">TN141<\/a>)<\/li>\n<\/ul>\n\n\n\n<p><\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/TN147_FPGA_Grid_Tied_Inverter.zip\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>TN147_FPGA_Grid_Tied_Inverter.zip<\/strong><\/a><\/div>\n\n\n\n<p>These IPs have been implemented using <strong>High-Level Synthesis<\/strong> tools such as <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a> (free of cost, C++) and <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> (~500$, requires MATLAB Simulink). These tools offer a simple yet powerful way of developing control algorithms in FPGA.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-performance-analysis-of-the-control-task\"><span class=\"ez-toc-section\" id=\"Performance-analysis-of-the-control-task\"><\/span>Performance analysis of the control task<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Without any special optimization, the latency of the presented inverter control algorithm is roughly 1.5\u00b5s (see details below), which means that it can run above 650 kHz. Comparatively, the similar CPU-based algorithm presented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/vector-current-control\">TN106<\/a> can run at up to 210 kHz.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-latency-and-control-delay\"><span class=\"ez-toc-section\" id=\"Latency-and-control-delay\"><\/span>Latency and control delay<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The total latency can be estimated by simply adding up the latency of each module, which are:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><thead><tr><th class=\"has-text-align-left\" data-align=\"left\"><br>Module<\/th><th class=\"has-text-align-center\" data-align=\"center\">Latency<br>Vitis HLS<\/th><th class=\"has-text-align-center\" data-align=\"center\">Latency<br>Model Composer<\/th><\/tr><\/thead><tbody><tr><td class=\"has-text-align-left\" data-align=\"left\">ADC conversion<\/td><td class=\"has-text-align-center\" data-align=\"center\">24 cycles<\/td><td class=\"has-text-align-center\" data-align=\"center\">24 cycles<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Grid synchronization<\/td><td class=\"has-text-align-center\" data-align=\"center\">145 cycles<\/td><td class=\"has-text-align-center\" data-align=\"center\">146 cycles<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">DQ current control<\/td><td class=\"has-text-align-center\" data-align=\"center\">72 cycles<\/td><td class=\"has-text-align-center\" data-align=\"center\">56 cycles<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Duty cycles computation<\/td><td class=\"has-text-align-center\" data-align=\"center\">138 cycles<\/td><td class=\"has-text-align-center\" data-align=\"center\">137 cycles<\/td><\/tr><\/tbody><tfoot><tr><td class=\"has-text-align-left\" data-align=\"left\"><strong>Total latency<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\">379 cycles<br>(<strong>1.52\u00b5s<\/strong>)<\/td><td class=\"has-text-align-center\" data-align=\"center\">363 cycles<br>(<strong>1.45\u00b5s<\/strong>)<\/td><\/tr><\/tfoot><\/table><\/figure>\n\n\n\n<p>That estimated latency is comparable to the measured latency of 385 cycles (1.54\u00b5s) with the Vitis HLS implementation. The Model Composer approach achieves a slightly lower latency thanks to automatic optimization but at the expense of slightly higher resource utilization.<\/p>\n\n\n\n<p>Considering a conversion time of the ADC chip of 2\u00b5s, the total control delay is 3.54\u00b5s, which is larger than one sampling period (chosen 2.5\u00b5s &#8211; 400kHz). Therefore, the execution of the control task is pipelined with the ADC acquisition, as shown in the figure below. The control delay to consider when tuning the current controller is therefore \\(T_{d,ctrl}=2T_{s}\\).<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"550\" height=\"232\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/execution_pipeline.png\" alt=\"Pipeline execution of the FPGA converter control algorithm\" class=\"wp-image-10360\" style=\"width:550px;height:232px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/execution_pipeline.png 550w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/execution_pipeline-300x127.png 300w\" sizes=\"auto, (max-width: 550px) 100vw, 550px\" \/><\/figure>\n<\/div>\n\n\n<p>Further details on control delay identification can be found in the <a href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\">PN142<\/a>.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-controller-tuning\"><strong>Control<\/strong>ler tuning<\/h4>\n\n\n\n<p>The gains of the PI controllers are tuned using the Magnitude Optimum, as introduced in <a href=\"https:\/\/imperix.com\/doc\/implementation\/vector-current-control\">Vector current control<\/a>. The total delay of the control loop is identified as:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Control delay: \\(T_{d,ctrl}=2T_{s}=5\\,\\text{\u00b5s}\\)<\/li>\n\n\n\n<li>Modulator delay (double-rate update): \\(T_{d,\\text{PWM}}=T_{sw}\/4=T_{s}\/2=1.25\\,\\text{\u00b5s}\\)<\/li>\n\n\n\n<li>Sensing delay: (16 kHz filter) \\(T_{d,sens}\\approx 10\\,\\text{\u00b5s}\\)<\/li>\n\n\n\n<li>Total loop delay: \\(T_{d,tot}=T_{d,ctrl}+T_{d,\\text{PWM}}+T_{d,sens}\\approx 16.25\\,\\text{\u00b5s}\\)<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-resource-utilization\"><span class=\"ez-toc-section\" id=\"Resource-utilization\"><\/span><strong>Resource utilization<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The resource utilization is estimated by Vivado after the implementation and is shown below, for the Vitis HLS approach.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><thead><tr><th><br>Resource<\/th><th class=\"has-text-align-center\" data-align=\"center\">Utilization<br>(inverter control)<\/th><th class=\"has-text-align-center\" data-align=\"center\">Utilization<br>(imperix firmware 3.6)<\/th><th class=\"has-text-align-center\" data-align=\"center\"><br>Total utilization<\/th><\/tr><\/thead><tbody><tr><td>LUT<\/td><td class=\"has-text-align-center\" data-align=\"center\">18&#8217;733<\/td><td class=\"has-text-align-center\" data-align=\"center\">24&#8217;220<\/td><td class=\"has-text-align-center\" data-align=\"center\">42&#8217;953 (54.65%)<\/td><\/tr><tr><td>LUTRAM<\/td><td class=\"has-text-align-center\" data-align=\"center\">115<\/td><td class=\"has-text-align-center\" data-align=\"center\">798<\/td><td class=\"has-text-align-center\" data-align=\"center\">913 (3.43%)<\/td><\/tr><tr><td>FF<\/td><td class=\"has-text-align-center\" data-align=\"center\">30&#8217;713<\/td><td class=\"has-text-align-center\" data-align=\"center\">50&#8217;732<\/td><td class=\"has-text-align-center\" data-align=\"center\">81&#8217;445 (51.81%)<\/td><\/tr><tr><td>BRAM<\/td><td class=\"has-text-align-center\" data-align=\"center\">2<\/td><td class=\"has-text-align-center\" data-align=\"center\">37<\/td><td class=\"has-text-align-center\" data-align=\"center\">39 (14.72%)<\/td><\/tr><tr><td>DSP<\/td><td class=\"has-text-align-center\" data-align=\"center\">104<\/td><td class=\"has-text-align-center\" data-align=\"center\">0<\/td><td class=\"has-text-align-center\" data-align=\"center\">104 (26%)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">FPGA resource utilization of the inverter control algorithm and the imperix firmware <\/figcaption><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Resource utilization and latency may vary depending on the software&#8217;s versions, selected synthesis\/placement optimizations, etc.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-experimental-validation\"><span class=\"ez-toc-section\" id=\"Experimental-validation\"><\/span>Experimental validation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-success\" role=\"alert\">General\u00a0<strong>safety-related recommendations<\/strong>\u00a0for operating power converters in a laboratory environment are given in\u00a0<a href=\"https:\/\/imperix.com\/doc\/implementation\/safety-and-protection-in-the-lab\">TN181<\/a>.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-testbench-description\"><span class=\"ez-toc-section\" id=\"Testbench-description\"><\/span>Testbench description<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>A physical testbench is built to validate the developed control strategy experimentally, using the following equipment:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Controller:  <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<\/a> with <a href=\"https:\/\/imperix.com\/software\/acg-sdk\/simulink\/\">ACG SDK for Simulink<\/a><\/li>\n\n\n\n<li>Inverter: 3x <a href=\"https:\/\/imperix.com\/products\/power\/sic-power-module\/\">PEB8024 phase leg module<\/a> with fast-switching SiC MOSFETs<\/li>\n\n\n\n<li>Grid inductors: from <a href=\"https:\/\/imperix.com\/products\/power\/filter-box\/\">passive filters box<\/a><\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"894\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/setup_photo_v2-1024x894.png\" alt=\"Experimental setup of grid-connected inverter controlled by an FPGA\" class=\"wp-image-10332\" style=\"width:592px;height:517px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/setup_photo_v2-1024x894.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/setup_photo_v2-300x262.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/setup_photo_v2-768x670.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/setup_photo_v2-1536x1341.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/setup_photo_v2.png 1614w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p>The main operating parameters are summarized in the tables below.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-table\"><table><thead><tr><th>Parameter<\/th><th>Value<\/th><\/tr><\/thead><tbody><tr><td>DC bus voltage<\/td><td>750 V<\/td><\/tr><tr><td>Grid voltage<\/td><td>380 V<\/td><\/tr><tr><td>Grid inductor (from <a href=\"https:\/\/imperix.com\/products\/power\/filter-box\/\">filter box<\/a>)<\/td><td>2.36 mH<\/td><\/tr><\/tbody><\/table><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-table\"><table><thead><tr><th>Parameter<\/th><th>Value<\/th><\/tr><\/thead><tbody><tr><td>Sampling frequency<\/td><td>400 kHz<\/td><\/tr><tr><td>Control frequency (FPGA)<\/td><td>400 kHz<\/td><\/tr><tr><td>Switching frequency<\/td><td>200 kHz<\/td><\/tr><\/tbody><\/table><\/figure>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-danger\" role=\"alert\">Due to the high switching frequency of this application (200kHz), the PWM modulators are configured with a small deadtime (200ns). Therefore, only PEB8024 power modules, which support smaller deadtimes can be used for this testbench. Using other types of modules may result in irreversible damage to the semiconductors.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-experimental-results\"><span class=\"ez-toc-section\" id=\"Experimental-results\"><\/span>Experimental results<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Various reference steps are performed on the d- and q-axis current references to validate the reference tracking and perturbation rejection abilities of the developed algorithm.<\/p>\n\n\n\n<p>The graph below shows the measured grid currents when the d-axis current reference takes the values 5, 12, and 8 A.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"300\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/abc_currents_vitis_steps.png\" alt=\"Experimental grid currents in voltage source inverter\" class=\"wp-image-10331\" style=\"width:800px;height:300px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/abc_currents_vitis_steps.png 800w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/abc_currents_vitis_steps-300x113.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/abc_currents_vitis_steps-768x288.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><figcaption class=\"wp-element-caption\">Measured grid currents when changing the d-axis current reference<\/figcaption><\/figure>\n\n\n\n<p>When projected into the dq rotating reference frame, the measured grid currents give the following results. It can be seen that the current reference is successfully and rapidly tracked by the d-axis controllers and that the perturbation is well rejected on the q axis.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"300\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dstep_vitis.png\" alt=\"Experimental results with d-axis grid current tracking\" class=\"wp-image-10329\" style=\"width:800px;height:300px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dstep_vitis.png 800w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dstep_vitis-300x113.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dstep_vitis-768x288.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><figcaption class=\"wp-element-caption\">Measured grid currents in the dq reference frame when changing the d-axis current reference<\/figcaption><\/figure>\n\n\n\n<p>If the same reference steps are performed on the q-axis, the same observations can be made.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"300\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/qstep_vitis.png\" alt=\"Experimental results with q-axis grid current tracking\" class=\"wp-image-10330\" style=\"width:800px;height:300px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/qstep_vitis.png 800w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/qstep_vitis-300x113.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/qstep_vitis-768x288.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><figcaption class=\"wp-element-caption\">Measured grid currents in the dq reference frame when changing the q-axis current reference<\/figcaption><\/figure>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-creation-of-the-vivado-block-design\"><span class=\"ez-toc-section\" id=\"Creation-of-the-Vivado-block-design\"><\/span>Creation of the Vivado block design<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This section provides a step-by-step explanation of how to re-create the Vivado project to generate the FPGA bitstream of the Grid-tied inverter control.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Information on how to create an FPGA control template is available on the\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">Getting started with FPGA control impl.<\/a><br><br>To find all FPGA-related notes, you can visit\u00a0the <a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-raw-adc-data-conversion\"><span class=\"ez-toc-section\" id=\"Raw-ADC-data-conversion\"><\/span>Raw ADC data conversion<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The ADC conversion results are available from the AXI4-Stream interfaces  <strong>M_AXIS_ADC<\/strong> of the \u201cix axis interface\u201d module. They return the raw&nbsp;<strong>16-bit signed integer<\/strong>&nbsp;result from the ADC chips.<\/p>\n\n\n\n<p>The ADC conversion IP shown below serves to convert that raw data into the <strong>actual measured quantities<\/strong> in the <code>float<\/code> datatype. Knowing the sensitivity \\(S\\) of the sensor and the B-Box RCP front-end gain \\(G\\), the formula below can be used:<\/p>\n\n\n\n<p class=\"has-text-align-center\">\\(\\alpha [\\text{bit\/A}] = S\\cdot G\\cdot 32768\/10\\,\\)<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">A numerical example of gain computation is available in the last section of the\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/analog-front-end-configuration-on-b-box-rcp\">B-Box analog frontend configuration<\/a> page.<\/div>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-center is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"170\" height=\"40\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/float_convertion_module.png\" alt=\"\" class=\"wp-image-9764\" style=\"width:170px;height:40px\"\/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"379\" height=\"277\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image.png\" alt=\"\" class=\"wp-image-12241\" style=\"width:304px;height:222px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image.png 379w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-300x219.png 300w\" sizes=\"auto, (max-width: 379px) 100vw, 379px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n<style>.kt-accordion-id3199_5df50b-aa .kt-accordion-inner-wrap{column-gap:var(--global-kb-gap-md, 2rem);row-gap:1px;}.kt-accordion-id3199_5df50b-aa .kt-accordion-panel-inner{border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;padding-top:20px;padding-right:20px;padding-bottom:20px;padding-left:20px;}.kt-accordion-id3199_5df50b-aa > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header{border-top-color:#f2f2f2;border-right-color:#f2f2f2;border-bottom-color:#f2f2f2;border-left-color:#f2f2f2;border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;font-size:16px;line-height:24px;letter-spacing:0px;font-weight:bold;text-transform:none;color:var(--global-palette3, #1A202C);padding-top:12px;padding-right:10px;padding-bottom:8px;padding-left:16px;}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id3199_5df50b-aa > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header:hover, \n\t\t\t\tbody:not(.hide-focus-outline) .kt-accordion-id3199_5df50b-aa .kt-blocks-accordion-header:focus-visible{color:#444444;background:#ffffff;border-top-color:#eeeeee;border-right-color:#eeeeee;border-bottom-color:#eeeeee;border-left-color:#eeeeee;}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion--visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#444444;}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger, body:not(.hide-focus-outline) .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger{background:#444444;}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id3199_5df50b-aa .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible,\n\t\t\t\t.kt-accordion-id3199_5df50b-aa > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active{color:var(--global-palette3, #1A202C);background:var(--global-palette9, #ffffff);border-top-color:var(--global-palette6, #718096);border-right-color:var(--global-palette6, #718096);border-bottom-color:var(--global-palette6, #718096);border-left-color:var(--global-palette6, #718096);}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_5df50b-aa:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette9, #ffffff);}@media all and (max-width: 767px){.kt-accordion-id3199_5df50b-aa .kt-accordion-inner-wrap{display:block;}.kt-accordion-id3199_5df50b-aa .kt-accordion-inner-wrap .kt-accordion-pane:not(:first-child){margin-top:1px;}}<\/style>\n<div class=\"wp-block-kadence-accordion alignnone\"><div class=\"kt-accordion-wrap kt-accordion-id3199_5df50b-aa kt-accordion-has-3-panes kt-active-pane-0 kt-accordion-block kt-pane-header-alignment-left kt-accodion-icon-style-arrow kt-accodion-icon-side-left\" style=\"max-width:none\"><div class=\"kt-accordion-inner-wrap\" data-allow-multiple-open=\"false\" data-start-open=\"none\">\n<div class=\"wp-block-kadence-pane kt-accordion-pane kt-accordion-pane-1 kt-pane3199_0e34fe-39\"><div class=\"kt-accordion-header-wrap\"><button class=\"kt-blocks-accordion-header kt-acccordion-button-label-show\" type=\"button\"><span class=\"kt-blocks-accordion-title-wrap\"><span class=\"kt-blocks-accordion-title\"><strong>Vitis HLS &#8211; ADC conversion<\/strong> C++ source<\/span><\/span><span class=\"kt-blocks-accordion-icon-trigger\"><\/span><\/button><\/div><div class=\"kt-accordion-panel kt-accordion-panel-hidden\"><div class=\"kt-accordion-panel-inner\"><pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"ADC_conversion.h\"<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_stream.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdint.h&gt;<\/span><\/span>\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">adc_conversion<\/span><span class=\"hljs-params\">(\n  hls::stream&lt;<span class=\"hljs-keyword\">int16_t<\/span>&gt;&amp; adc_in,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; adc_gain,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; adc_offset,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; adc_out)<\/span>\n<\/span>{\n<span class=\"hljs-comment\">\/\/ see https:\/\/docs.xilinx.com\/r\/en-US\/ug1399-vitis-hls\/pragma-HLS-interface<\/span>\n<span class=\"hljs-comment\">\/\/ \"both\" means registers are placed on TDATA, TVALID, and TREADY<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=adc_in register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=adc_gain register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=adc_offset register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=adc_out register_mode=both register<\/span>\n<span class=\"hljs-comment\">\/\/ turns off block-level I\/O protocols<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS interface ap_ctrl_none port=return<\/span>\n\n  <span class=\"hljs-keyword\">int16_t<\/span> adc = adc_in.read();\n  <span class=\"hljs-keyword\">float<\/span> gain = adc_gain.read();\n  <span class=\"hljs-keyword\">float<\/span> offset = adc_offset.read();\n  <span class=\"hljs-keyword\">float<\/span> result = (<span class=\"hljs-keyword\">float<\/span>)adc * gain - offset;\n  adc_out.write(result);\n}<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre><\/div><\/div><\/div>\n<\/div><\/div><\/div>\n\n\n\n<p>This ADC conversion module is connected as shown in the two screenshots below. The <strong>AXI4-Stream Broadcaster<\/strong> IP (included with Vivado) serves to propagate an AXI4-Stream to multiple ports. <\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"948\" height=\"921\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/5.png\" alt=\"\" class=\"wp-image-12287\" style=\"width:708px;height:687px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/5.png 948w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/5-300x291.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/5-768x746.png 768w\" sizes=\"auto, (max-width: 948px) 100vw, 948px\" \/><figcaption class=\"wp-element-caption\">The &#8220;adc&#8221; hierarchy contains the conversion logic<\/figcaption><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"847\" height=\"993\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/3.png\" alt=\"\" class=\"wp-image-12286\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/3.png 847w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/3-256x300.png 256w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/3-768x900.png 768w\" sizes=\"auto, (max-width: 847px) 100vw, 847px\" \/><figcaption class=\"wp-element-caption\">Content of the &#8220;adc&#8221; hierarchy<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-sample-time-ts-conversion\"><span class=\"ez-toc-section\" id=\"Sample-time-Ts-conversion\"><\/span>Sample time (Ts) conversion<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The&nbsp;<strong>M_AXIS_Ts&nbsp;<\/strong>port of the \u201cix axis interface\u201d provides the sample period \\(T_s\\) in <strong>nanoseconds <\/strong>in a <strong>32-bit unsigned integer<\/strong> format. This signal is the time distance between two consecutive samples.<\/p>\n\n\n\n<p>The<strong> Ts conversion module<\/strong> shown below converts this signal into a <strong>floating-point<\/strong> value in <strong>seconds<\/strong>. The result will be used by the PI controllers of the Grid synchronization module and the dq current control module.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1019\" height=\"240\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-2.png\" alt=\"\" class=\"wp-image-12289\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-2.png 1019w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-2-300x71.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-2-768x181.png 768w\" sizes=\"auto, (max-width: 1019px) 100vw, 1019px\" \/><\/figure>\n\n\n<style>.kt-accordion-id3199_234f0c-7d .kt-accordion-inner-wrap{column-gap:var(--global-kb-gap-md, 2rem);row-gap:1px;}.kt-accordion-id3199_234f0c-7d .kt-accordion-panel-inner{border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;padding-top:20px;padding-right:20px;padding-bottom:20px;padding-left:20px;}.kt-accordion-id3199_234f0c-7d > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header{border-top-color:#f2f2f2;border-right-color:#f2f2f2;border-bottom-color:#f2f2f2;border-left-color:#f2f2f2;border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;font-size:16px;line-height:24px;letter-spacing:0px;font-weight:bold;text-transform:none;color:var(--global-palette3, #1A202C);padding-top:12px;padding-right:10px;padding-bottom:8px;padding-left:16px;}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id3199_234f0c-7d > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header:hover, \n\t\t\t\tbody:not(.hide-focus-outline) .kt-accordion-id3199_234f0c-7d .kt-blocks-accordion-header:focus-visible{color:#444444;background:#ffffff;border-top-color:#eeeeee;border-right-color:#eeeeee;border-bottom-color:#eeeeee;border-left-color:#eeeeee;}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion--visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#444444;}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger, body:not(.hide-focus-outline) .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger{background:#444444;}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id3199_234f0c-7d .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible,\n\t\t\t\t.kt-accordion-id3199_234f0c-7d > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active{color:var(--global-palette3, #1A202C);background:var(--global-palette9, #ffffff);border-top-color:var(--global-palette6, #718096);border-right-color:var(--global-palette6, #718096);border-bottom-color:var(--global-palette6, #718096);border-left-color:var(--global-palette6, #718096);}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id3199_234f0c-7d:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette9, #ffffff);}@media all and (max-width: 767px){.kt-accordion-id3199_234f0c-7d .kt-accordion-inner-wrap{display:block;}.kt-accordion-id3199_234f0c-7d .kt-accordion-inner-wrap .kt-accordion-pane:not(:first-child){margin-top:1px;}}<\/style>\n<div class=\"wp-block-kadence-accordion alignnone\"><div class=\"kt-accordion-wrap kt-accordion-id3199_234f0c-7d kt-accordion-has-3-panes kt-active-pane-0 kt-accordion-block kt-pane-header-alignment-left kt-accodion-icon-style-arrow kt-accodion-icon-side-left\" style=\"max-width:none\"><div class=\"kt-accordion-inner-wrap\" data-allow-multiple-open=\"false\" data-start-open=\"none\">\n<div class=\"wp-block-kadence-pane kt-accordion-pane kt-accordion-pane-1 kt-pane3199_ff978f-f1\"><div class=\"kt-accordion-header-wrap\"><button class=\"kt-blocks-accordion-header kt-acccordion-button-label-show\" type=\"button\"><span class=\"kt-blocks-accordion-title-wrap\"><span class=\"kt-blocks-accordion-title\"><strong>Vitis HLS &#8211; Ts conversion<\/strong> C++ source<\/span><\/span><span class=\"kt-blocks-accordion-icon-trigger\"><\/span><\/button><\/div><div class=\"kt-accordion-panel kt-accordion-panel-hidden\"><div class=\"kt-accordion-panel-inner\"><pre class=\"wp-block-code\" aria-describedby=\"shcb-language-2\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"Ts_conversion.h\"<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_stream.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdint.h&gt;<\/span><\/span>\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">ts_conversion<\/span><span class=\"hljs-params\">(\n  hls::stream&lt;<span class=\"hljs-keyword\">uint32_t<\/span>&gt;&amp; Ts_ns_in,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; Ts_s_out)<\/span>\n<\/span>{\n\n<span class=\"hljs-comment\">\/\/ see https:\/\/docs.xilinx.com\/r\/en-US\/ug1399-vitis-hls\/pragma-HLS-interface<\/span>\n<span class=\"hljs-comment\">\/\/ \"both\" means registers are placed on TDATA, TVALID, and TREADY<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=Ts_ns_in register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=Ts_s_out register_mode=both register<\/span>\n<span class=\"hljs-comment\">\/\/ turns off block-level I\/O protocols<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS interface ap_ctrl_none port=return<\/span>\n\n  <span class=\"hljs-keyword\">uint32_t<\/span> Ts_ns = Ts_ns_in.read();\n  <span class=\"hljs-comment\">\/\/ convert from nanoseconds to seconds<\/span>\n  <span class=\"hljs-keyword\">float<\/span> Ts_s  = (<span class=\"hljs-keyword\">float<\/span>)Ts_ns * <span class=\"hljs-number\">0.000000001f<\/span>; \n  Ts_s_out.write(Ts_s);\n}<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-2\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre><\/div><\/div><\/div>\n<\/div><\/div><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-grid-synchronization\"><span class=\"ez-toc-section\" id=\"Grid-synchronization\"><\/span>Grid synchronization<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The grid synchronization is done using the <strong>dq-type PLL<\/strong> which transforms both the grid voltages and currents into dq components, that are used in the dq current controller.<\/p>\n\n\n\n<p>The grid synchronization IP shown below is documented in the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-implementation-pll\">FPGA impl. of a PLL for grid sync<\/a> page.<\/p>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-center is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"209\" height=\"167\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/grid_snychro_module.png\" alt=\"\" class=\"wp-image-9756\"\/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"399\" height=\"349\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-3.png\" alt=\"\" class=\"wp-image-12290\" style=\"width:324px;height:283px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-3.png 399w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-3-300x262.png 300w\" sizes=\"auto, (max-width: 399px) 100vw, 399px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>In the Vivado project, the IP is connected as follows. An <strong>AXI4-Stream Broadcaster<\/strong> is used because the sample time (Ts) signal is also connected to the dq current controller as shown in the next section.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"561\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-4-1024x561.png\" alt=\"\" class=\"wp-image-12291\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-4-1024x561.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-4-300x164.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-4-768x421.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-4.png 1258w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-dq-current-control\"><span class=\"ez-toc-section\" id=\"DQ-current-control\"><\/span>DQ current control<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The implementation of the dq current controller is detailed in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\">FPGA-based PI for dq current control<\/a>. It consists of two identical PI controllers with a decoupling network for independent control of the d- and q-components of the grid current.<\/p>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-center is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"181\" height=\"210\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dq_current_ctrl_module.png\" alt=\"\" class=\"wp-image-9758\"\/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"394\" height=\"271\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dq_current_ctrl-2.png\" alt=\"\" class=\"wp-image-10308\" style=\"width:356px;height:245px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dq_current_ctrl-2.png 394w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dq_current_ctrl-2-300x206.png 300w\" sizes=\"auto, (max-width: 394px) 100vw, 394px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>The <strong>kiTs_dq <\/strong>port takes as input the results of <strong>Ts<\/strong> multiplied by <strong>Ki<\/strong> (Ki is a parameter set from the CPU, using the port <strong>CPU2FPGA_10<\/strong>). The multiplication is performed using a <strong>Floating-Point<\/strong> <strong>IP <\/strong>as shown below.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"176\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-5-1024x176.png\" alt=\"\" class=\"wp-image-12292\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-5-1024x176.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-5-300x51.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-5-768x132.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-5-1536x264.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-5.png 1795w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>The dq current controller is connected as shown below. The inputs <strong>Kp<\/strong>, <strong>Id_ref<\/strong>, and <strong>Iq_ref <\/strong>are connected to <strong>CPU2FPGA <\/strong>ports <strong>11<\/strong>, <strong>12<\/strong>, and <strong>13<\/strong>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"379\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-6-1024x379.png\" alt=\"\" class=\"wp-image-12293\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-6-1024x379.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-6-300x111.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-6-768x284.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-6-1536x568.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-6.png 1887w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-duty-cycles-computation\"><span class=\"ez-toc-section\" id=\"Duty-cycles-computation\"><\/span>Duty cycles computation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-center is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"178\" height=\"167\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/duty_cycle_module.png\" alt=\"\" class=\"wp-image-9759\"\/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"421\" height=\"276\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/duty_cycles.png\" alt=\"\" class=\"wp-image-10306\" style=\"width:339px;height:221px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/duty_cycles.png 421w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/duty_cycles-300x197.png 300w\" sizes=\"auto, (max-width: 421px) 100vw, 421px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>This block converts the voltage references computed by the dq current controller to <em>abc<\/em> quantities \\(E_{g,abc}\\), and computes the corresponding duty cycles (in the range [0,1]) according to<\/p>\n\n\n\n<p>$$ d_{abc} = \\left(\\frac{E_{g,abc}}{V_{dc}}+0.5\\right)\\cdot T_\\text{clk},$$<\/p>\n\n\n\n<p>where \\(T_\\text{clk}\\) is the period of the clock used in the PWM modulator, expressed in ticks (1 tick = 4 ns). The duty cycles are converted into <code>uint16<\/code> numbers with a unit of ticks to be compatible with the PWM modulator.<\/p>\n\n\n\n<p>It is connected as shown below. <strong>in_CLOCK_period<\/strong> is connected to <strong>CLOCK_1_period<\/strong> of the IMPERIX_FW IP.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"419\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-8-1024x419.png\" alt=\"\" class=\"wp-image-12295\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-8-1024x419.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-8-300x123.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-8-768x314.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-8-1536x628.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-8.png 2013w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n<style>.kt-accordion-id3199_86f747-b6 .kt-accordion-inner-wrap{column-gap:var(--global-kb-gap-md, 2rem);row-gap:1px;}.kt-accordion-id3199_86f747-b6 .kt-accordion-panel-inner{border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;padding-top:20px;padding-right:20px;padding-bottom:20px;padding-left:20px;}.kt-accordion-id3199_86f747-b6 > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > 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class=\"kt-blocks-accordion-title\"><strong>Vitis HLS &#8211; Duty cycles computation<\/strong><\/span><\/span><span class=\"kt-blocks-accordion-icon-trigger\"><\/span><\/button><\/div><div class=\"kt-accordion-panel kt-accordion-panel-hidden\"><div class=\"kt-accordion-panel-inner\"><pre class=\"wp-block-code\" aria-describedby=\"shcb-language-3\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"duty_cycles.h\"<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_stream.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdint.h&gt;<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"ap_fixed.h\"<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"hls_math.h\"<\/span><\/span>\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">dq02abc<\/span><span class=\"hljs-params\">(<span class=\"hljs-keyword\">float<\/span> d, <span class=\"hljs-keyword\">float<\/span> q, <span class=\"hljs-keyword\">float<\/span> zero, <span class=\"hljs-keyword\">float<\/span> wt, <span class=\"hljs-keyword\">float<\/span>&amp; A, <span class=\"hljs-keyword\">float<\/span>&amp; B, <span class=\"hljs-keyword\">float<\/span>&amp; C)<\/span>\n<\/span>{\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS inline<\/span>\n\n  <span class=\"hljs-keyword\">const<\/span> ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">2<\/span>&gt; sqrt3_2 = <span class=\"hljs-number\">0.86602540378444<\/span>;<span class=\"hljs-comment\">\/\/ sqrt(3)\/2<\/span>\n\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; d_fix    = (ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt;)d;\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; q_fix    = (ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt;)q;\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; zero_fix = (ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt;)zero;\n  ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">4<\/span>&gt; wt_fix\t   = (ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">4<\/span>&gt;)wt;\n\n  ap_fixed&lt;<span class=\"hljs-number\">16<\/span>, <span class=\"hljs-number\">2<\/span>&gt; cos_wt = hls::<span class=\"hljs-built_in\">cos<\/span>(wt_fix);\n  ap_fixed&lt;<span class=\"hljs-number\">16<\/span>, <span class=\"hljs-number\">2<\/span>&gt; sin_wt = hls::<span class=\"hljs-built_in\">sin<\/span>(wt_fix);\n\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; alpha_fix = d_fix*cos_wt - q_fix*sin_wt;\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; beta_fix  = d_fix*sin_wt + q_fix*cos_wt;\n\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; A_fix = alpha_fix + zero_fix;\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; B_fix = zero_fix - alpha_fix\/<span class=\"hljs-number\">2<\/span> + sqrt3_2*beta_fix;\n  ap_fixed&lt;<span class=\"hljs-number\">32<\/span>,<span class=\"hljs-number\">16<\/span>&gt; C_fix = zero_fix - alpha_fix\/<span class=\"hljs-number\">2<\/span> - sqrt3_2*beta_fix;\n\n  A = (<span class=\"hljs-keyword\">float<\/span>)A_fix;\n  B = (<span class=\"hljs-keyword\">float<\/span>)B_fix;\n  C = (<span class=\"hljs-keyword\">float<\/span>)C_fix;\n}\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">float<\/span> <span class=\"hljs-title\">sat<\/span><span class=\"hljs-params\">(<span class=\"hljs-keyword\">float<\/span> input, <span class=\"hljs-keyword\">float<\/span> max_sat, <span class=\"hljs-keyword\">float<\/span> min_sat)<\/span>\n<\/span>{\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS inline<\/span>\n\n  <span class=\"hljs-keyword\">if<\/span>(input &gt; max_sat) {\n    <span class=\"hljs-keyword\">return<\/span> max_sat;\n  } <span class=\"hljs-keyword\">else<\/span> <span class=\"hljs-keyword\">if<\/span>(input &lt; min_sat) {\n    <span class=\"hljs-keyword\">return<\/span> min_sat;\n  } <span class=\"hljs-keyword\">else<\/span> {\n    <span class=\"hljs-keyword\">return<\/span> input;\n  }\n}\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">vitis_duty_cycles<\/span><span class=\"hljs-params\">(\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Udc,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Ed_ref,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Eq_ref,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_E0_ref,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_theta,\n  <span class=\"hljs-keyword\">uint16_t<\/span> in_CLOCK_period,\n  <span class=\"hljs-keyword\">uint16_t<\/span>&amp; out_dutycycle_A,\n  <span class=\"hljs-keyword\">uint16_t<\/span>&amp; out_dutycycle_B,\n  <span class=\"hljs-keyword\">uint16_t<\/span>&amp; out_dutycycle_C)<\/span>\n<\/span>{\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Udc register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Ed_ref register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Eq_ref register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_E0_ref register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_theta register_mode=both register<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS interface ap_ctrl_none port=return<\/span>\n\n  <span class=\"hljs-keyword\">float<\/span> Udc = in_Udc.read();\n  <span class=\"hljs-keyword\">float<\/span> Ed_ref = in_Ed_ref.read();\n  <span class=\"hljs-keyword\">float<\/span> Eq_ref = in_Eq_ref.read();\n  <span class=\"hljs-keyword\">float<\/span> E0_ref = in_E0_ref.read();\n  <span class=\"hljs-keyword\">float<\/span> theta = in_theta.read();\n\n  <span class=\"hljs-keyword\">float<\/span> A,B,C;\n  dq02abc(Ed_ref, Eq_ref, E0_ref, theta, A, B, C);\n\n  <span class=\"hljs-keyword\">float<\/span> next_d_A = A\/Udc + <span class=\"hljs-number\">0.5<\/span>;\n  <span class=\"hljs-keyword\">float<\/span> next_d_B = B\/Udc + <span class=\"hljs-number\">0.5<\/span>;\n  <span class=\"hljs-keyword\">float<\/span> next_d_C = C\/Udc + <span class=\"hljs-number\">0.5<\/span>;\n\n  <span class=\"hljs-keyword\">float<\/span> d_A = sat(next_d_A, <span class=\"hljs-number\">1.0<\/span>, <span class=\"hljs-number\">0.0<\/span>);\n  <span class=\"hljs-keyword\">float<\/span> d_B = sat(next_d_B, <span class=\"hljs-number\">1.0<\/span>, <span class=\"hljs-number\">0.0<\/span>);\n  <span class=\"hljs-keyword\">float<\/span> d_C = sat(next_d_C, <span class=\"hljs-number\">1.0<\/span>, <span class=\"hljs-number\">0.0<\/span>);\n\n  ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">2<\/span>&gt; d_A_fix = (ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">2<\/span>&gt;)d_A;\n  ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">2<\/span>&gt; d_B_fix = (ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">2<\/span>&gt;)d_B;\n  ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">2<\/span>&gt; d_C_fix = (ap_fixed&lt;<span class=\"hljs-number\">16<\/span>,<span class=\"hljs-number\">2<\/span>&gt;)d_C;\n\n  out_dutycycle_A = (<span class=\"hljs-keyword\">uint16_t<\/span>)(d_A_fix * in_CLOCK_period);\n  out_dutycycle_B = (<span class=\"hljs-keyword\">uint16_t<\/span>)(d_B_fix * in_CLOCK_period);\n  out_dutycycle_C = (<span class=\"hljs-keyword\">uint16_t<\/span>)(d_C_fix * in_CLOCK_period);\n}\n<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-3\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre><\/div><\/div><\/div>\n<\/div><\/div><\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-pwm-generation\"><span class=\"ez-toc-section\" id=\"PWM-generation\"><\/span>PWM generation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-center is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"198\" height=\"136\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/pwm_modulator_module.png\" alt=\"\" class=\"wp-image-9760\"\/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"338\" height=\"223\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/pwm_modulator.png\" alt=\"\" class=\"wp-image-10346\" style=\"width:294px;height:194px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/pwm_modulator.png 338w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/pwm_modulator-300x198.png 300w\" sizes=\"auto, (max-width: 338px) 100vw, 338px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>Finally, the duty cycles are transformed into PWM signals in the PWM modulator block. The implementation details are presented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">PWM modulator implementation in FPGA<\/a>.<\/p>\n\n\n\n<p>The PWM block uses the clock signal <code>CLOCK_1<\/code> as a reference to generate the PWM triangular carrier signal. The switching frequency is therefore equal to the frequency of <code>CLOCK_1<\/code>, which can be configured using a <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> block.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"654\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-9-1024x654.png\" alt=\"\" class=\"wp-image-12296\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-9-1024x654.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-9-300x192.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-9-768x491.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-9.png 1529w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>The high-side switching signals are obtained by comparing the 3 duty cycles \\(d_{abc}\\) with the triangular carrier. The generation of the low-side switching signals is done by the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-pwm\">SB-PWM<\/a> driver incorporated into the imperix IP and the dead time duration is specified in the CPU block <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-pwm\">Sandbox PWM configurator<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"476\" height=\"661\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/deadtime_simulink.png\" alt=\"\" class=\"wp-image-20830\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/deadtime_simulink.png 476w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/deadtime_simulink-216x300.png 216w\" sizes=\"auto, (max-width: 476px) 100vw, 476px\" \/><figcaption class=\"wp-element-caption\">Configuration of the SB-PWM block in Simulink<\/figcaption><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"747\" height=\"1024\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/TN147_deadtime.png\" alt=\"\" class=\"wp-image-20836\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/TN147_deadtime.png 747w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/TN147_deadtime-219x300.png 219w\" sizes=\"auto, (max-width: 747px) 100vw, 747px\" \/><figcaption class=\"wp-element-caption\">Mapping between sb_pwm and pwm ports of the imperix IP in Vivado<\/figcaption><\/figure>\n<\/div>\n<\/div>\n\n\n\n<p>Thanks to the SB-PWM driver, the safety mechanism of the B-Box RCP is also available for custom-made PWM modulators. In case an over-value is detected during operation, the PWM outputs are immediately blocked and the operation is safely stopped.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"880\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-10-1024x880.png\" alt=\"\" class=\"wp-image-12297\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-10-1024x880.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-10-300x258.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-10-768x660.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-10.png 1102w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-cpu-side-implementation\"><span class=\"ez-toc-section\" id=\"CPU-side-implementation\"><\/span>CPU-side implementation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The CPU model shown below is only used for the following tasks:<\/p>\n\n\n\n<p><strong>Configuration:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Configure the sampling frequency using the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">Configuration block<\/a> (CLOCK_0 = 100 kHz, oversampling = 4)<\/li>\n\n\n\n<li>Configure the modulator clocks using the <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK block<\/a> (CLOCK_1 = 200 kHz)<\/li>\n\n\n\n<li>Configure the ADC conversion parameters (gain and offset)<\/li>\n<\/ul>\n\n\n\n<p><strong>Parameter tuning:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Tune the controller gains (Kp and Ki)<\/li>\n\n\n\n<li>Transfer the dq current references \\(I_{g,d}^*\\) and \\(I_{g,q}^*\\) to the FPGA<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The mapping between SBI\/SBO registers and CPU2FPGA\/FPGA2CPU port is explained on the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">Getting started<\/a> page.<\/div>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"273\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-18-1024x273.png\" alt=\"\" class=\"wp-image-12346\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-18-1024x273.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-18-300x80.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-18-768x205.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-18.png 1419w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-debugging-and-monitoring\"><span class=\"ez-toc-section\" id=\"Debugging-and-monitoring\"><\/span>Debugging and monitoring<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>For debugging and monitoring purposes, internal signals of the FPGA inverter control model can be split using <strong>AXI4-Stream Broadcaster IPs<\/strong> and routed to <strong>FPGA2CPU <\/strong>ports of the imperix IP. This way, the signals can be accessed from the CPU, connected to <a href=\"https:\/\/imperix.com\/doc\/software\/probe-variable\">probe variable<\/a> blocks, and observed using <a href=\"https:\/\/imperix.com\/software\/cockpit\/\">Cockpit<\/a>.<\/p>\n\n\n\n<p>Additionally, ADC blocks can still be used to observe the analog input signals. For accurate readings, make sure the sensitivities of the ADC blocks match the gain parameter sent to the FPGA!<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Please note that if the FPGA control is running faster than the CPU, then the CPU will only see a downsampled version of the observed signals.<\/div>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"241\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/block_design_with_debug_probes_screenshot-1024x241.png\" alt=\"\" class=\"wp-image-12349\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/block_design_with_debug_probes_screenshot-1024x241.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/block_design_with_debug_probes_screenshot-300x70.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/block_design_with_debug_probes_screenshot-768x180.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/block_design_with_debug_probes_screenshot-1536x361.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/block_design_with_debug_probes_screenshot-2048x481.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Vivado block design with debug probes<\/figcaption><\/figure>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/TN147_block_design_with_debug_probes.pdf\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>TN147_block_design_with_debug_probes.pdf<\/strong><\/a><\/div>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"668\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-19-1024x668.png\" alt=\"\" class=\"wp-image-12351\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-19-1024x668.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-19-300x196.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-19-768x501.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/image-19.png 1422w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Complete CPU model with debug probes and ADC blocks<\/figcaption><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n","protected":false},"excerpt":{"rendered":"<p>This note presents an FPGA control implementation of a grid-tied current-controlled inverter. It combines several control modules presented in different Technical Notes to form a&#8230;<\/p>\n","protected":false},"author":10,"featured_media":10465,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[4],"tags":[17],"software-environments":[106,103],"provided-results":[108],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[129],"user-manuals":[],"coauthors":[72],"class_list":["post-3199","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-implementation","tag-fpga-programming","software-environments-fpga","software-environments-matlab","provided-results-experimental","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","tutorials-fpga-based-control-of-a-grid-tied-inverter"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - 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