{"id":3420,"date":"2021-06-10T08:49:51","date_gmt":"2021-06-10T08:49:51","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3420"},"modified":"2025-05-07T12:54:06","modified_gmt":"2025-05-07T12:54:06","slug":"axi4-stream-ip-from-xilinx","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/implementation\/axi4-stream-ip-from-xilinx","title":{"rendered":"AXI4-Stream IPs from Xilinx"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/implementation\/axi4-stream-ip-from-xilinx\/#Floating-point-IP\" >Floating-point IP<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/implementation\/axi4-stream-ip-from-xilinx\/#AXI4-Stream-Broadcaster\" >AXI4-Stream Broadcaster<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/implementation\/axi4-stream-ip-from-xilinx\/#AXI4-Stream-Subset-Converter\" >AXI4-Stream Subset Converter<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>This page presents some useful Xilinx IP cores for Vivado. These IPs use the widely used AXI4-Stream protocol to easily exchange data with other Xilinx IPs or with user-made algorithms developed using High-Level Synthesis (HLS) design tools such as <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> or <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a>.<\/p>\n\n\n\n<p>For more detailed information on the AXI4-Stream interconnect protocol, please refer to\u00a0<a href=\"https:\/\/zipcpu.com\/doc\/axi-stream.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">AMBA\u00ae4 AXI4-Stream Protocol Specification<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-floating-point-ip\"><span class=\"ez-toc-section\" id=\"Floating-point-IP\"><\/span><strong>Floating-point IP<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Xilinx Floating-point IPs can be used to deal with most floating-point computations. The operation, precision, optimization, latency can be customized.<\/p>\n\n\n\n<p>In Vivado, open the block design, right-click somewhere, and chose&nbsp;<strong>Add IP\u2026<\/strong> Search for <strong>Floating-point<\/strong> and drag it into the diagram.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/floating_point_ip.png\" alt=\"\" class=\"wp-image-3269\" width=\"280\" height=\"142\"\/><\/figure><\/div>\n\n\n\n<p>Double-click on the block and configure the block in the pop-up window.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"831\" height=\"892\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-41.png\" alt=\"\" class=\"wp-image-3279\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-41.png 831w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-41-279x300.png 279w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-41-768x824.png 768w\" sizes=\"auto, (max-width: 831px) 100vw, 831px\" \/><\/figure>\n\n\n\n<p>For more details please refer to <a href=\"https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/floating_point\/v7_1\/pg060-floating-point.pdf\">Floating-Point Operator v7.1 LogiCORE IP Product Guide (xilinx.com)<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-group\"><div class=\"wp-block-group__inner-container is-layout-flow wp-block-group-is-layout-flow\">\n<h3 class=\"wp-block-heading\" id=\"h-axi4-stream-broadcaster\"><span class=\"ez-toc-section\" id=\"AXI4-Stream-Broadcaster\"><\/span><strong>AXI4-Stream Broadcaster<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>In some cases, it can be useful to send one data to multiple slaves, or copy one data and send it to the CPU for debugging. For that purpose, the AXI4-Stream Broadcaster can be used.<\/p>\n\n\n\n<p>In Vivado, open the block design, right-click somewhere and chose&nbsp;<strong>Add IP\u2026<\/strong> Search for <strong>AXI4-Stream Broadcaster<\/strong> and drag it into the diagram.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"241\" height=\"125\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/axis_broadcaster.png\" alt=\"\" class=\"wp-image-3272\"\/><\/figure><\/div>\n\n\n\n<p>Double-click on the block and configure the block in the pop-up window. Usually, users only have to change the number of master interfaces and the SI\/MI data width.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-38.png\" alt=\"\" class=\"wp-image-3274\" width=\"675\" height=\"645\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-38.png 802w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-38-300x287.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-38-768x734.png 768w\" sizes=\"auto, (max-width: 675px) 100vw, 675px\" \/><\/figure><\/div>\n\n\n\n<p><strong>WARNING 1:<\/strong> Note that users should not leave the output ports floating or not connected to a AXI4-Stream slave. Since the AXI4-Stream Broadcaster IP doesn&#8217;t provide a default <em>tready<\/em> signal, a floating output port will block the dataflow. A relevant discussion about the problem caused by floating <em>tready<\/em> is in <a href=\"https:\/\/forums.xilinx.com\/t5\/Video-and-Audio\/axis-broadcaster\/m-p\/860070\">Solved: axis broadcaster &#8211; Community Forums (xilinx.com)<\/a><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1018\" height=\"172\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/wrong_case2.png\" alt=\"\" class=\"wp-image-3275\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/wrong_case2.png 1018w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/wrong_case2-300x51.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/wrong_case2-768x130.png 768w\" sizes=\"auto, (max-width: 1018px) 100vw, 1018px\" \/><figcaption>The dataflow is blocked at M01_AXIS because no <em>tready<\/em> signal is received<\/figcaption><\/figure>\n\n\n\n<p><strong>WARNING 2: <\/strong>There is a known bug of AXI4-Stream Broadcaster that the width of all the <em>tdata\/tready\/tvalid\/&#8230;<\/em> signals looks &#8220;bigger&#8221; than normal. For example if one broadcasts a 4 Byte signal to 2 slaves, he will see a 8-Byte <em>tdata<\/em> in the output port, and this <em>tdata <\/em>cannot be overridden. This is only a display bug and users should only refer to the real data width in the configuration window. A relevant discussion about the problem is in <a href=\"https:\/\/forums.xilinx.com\/t5\/Video-and-Audio\/using-axi-broadcaster\/m-p\/1051159\">Solved: using axi broadcaster &#8211; Community Forums (xilinx.com)<\/a>.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-axi4-stream-subset-converter\"><span class=\"ez-toc-section\" id=\"AXI4-Stream-Subset-Converter\"><\/span><strong>AXI4-Stream Subset Converter<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>This IP is used to extract a subset from an AXI4-Stream signal.<\/p>\n\n\n\n<p>In Vivado, open the block design, right-click somewhere and chose&nbsp;<strong>Add IP\u2026<\/strong> Search for <strong>AXI4-Stream Subset Converter<\/strong> and drag it into the diagram.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"263\" height=\"120\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/axis_subset_converter.png\" alt=\"\" class=\"wp-image-3276\"\/><\/figure><\/div>\n\n\n\n<p>Double-click on the block and configure the block in the pop-up window. Usually, users only have to change the SI\/MI data width.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"596\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-40-1024x596.png\" alt=\"\" class=\"wp-image-3278\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-40-1024x596.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-40-300x175.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-40-768x447.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-40.png 1520w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>For more details of AXI4-Stream Protocol Broadcaster and Subset Converter, please refer to <a href=\"https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/axis_infrastructure_ip_suite\/v1_1\/pg085-axi4stream-infrastructure.pdf\">AXI4-Stream Infrastructure IP Suite v3.0 LogiCORE IP Product Guide (xilinx.com)<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n<\/div><\/div>\n","protected":false},"excerpt":{"rendered":"<p>This page presents some useful Xilinx IP cores for Vivado. These IPs use the widely used AXI4-Stream protocol to easily exchange data with other Xilinx&#8230;<\/p>\n","protected":false},"author":10,"featured_media":7231,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[4],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[],"coauthors":[72],"class_list":["post-3420","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-implementation","tag-fpga-programming","software-environments-fpga","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>AXI4-Stream IPs from Xilinx - imperix<\/title>\n<meta name=\"description\" content=\"This page presents some useful Xilinx IP cores for Vivado. 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