{"id":3438,"date":"2021-06-10T09:43:16","date_gmt":"2021-06-10T09:43:16","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3438"},"modified":"2026-04-16T11:26:16","modified_gmt":"2026-04-16T11:26:16","slug":"fpga-development-on-imperix-controllers","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers","title":{"rendered":"FPGA development on imperix controllers"},"content":{"rendered":"<div class=\"wp-block-image is-resized\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"350\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/banner.png\" alt=\"\" class=\"wp-image-7780\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/banner.png 800w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/banner-300x131.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/banner-768x336.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/figure>\n<\/div>\n\n\n<p>Usually, the user programs the imperix controller&#8217;s CPU using imperix <a href=\"https:\/\/imperix.com\/software\/acg-sdk\/\">ACG SDK<\/a> or <a href=\"https:\/\/imperix.com\/software\/cpp-sdk\/\">C++ SDK<\/a>, and uses the pre-implemented FPGA peripherals such as the ADC drivers or PWM generators. Nevertheless, advanced users can also directly program the FPGA to implement high-performance algorithms, interface with specialized peripherals, or implement high-speed communications with other devices.<\/p>\n\n\n\n<p>This page summarizes the documentation pages relating to <strong>FPGA development on imperix controllers<\/strong>.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-starting-an-fpga-development-project\">Starting an FPGA development project<\/h2>\n\n\n\n<p>Imperix offers the possibility to customize its FPGA firmware by instantiating the <strong>imperix firmware IP<\/strong> in AMD Vivado and editing programmable logic around it, in a workspace referred to as the <strong>FPGA sandbox<\/strong>.<\/p>\n\n\n\n<p>The first step to start editing the FPGA consists of <strong>installing AMD Vivado Design Suite<\/strong>, which is available for free as the ML Standard (or WebPACK) edition.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/vivado-design-suite-installation\">PN168: <strong>AMD Vivado Design Suite<\/strong> installation<\/a><\/li>\n<\/ul>\n\n\n\n<p>The user can then download the necessary source files and create the <strong>sandbox template<\/strong> by following these guides:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox\">PN117: <strong>Download of the imperix firmware IP <\/strong>for FPGA sandbox<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">PN159: <strong>Getting started with FPGA<\/strong> <strong>programming<\/strong><\/a><\/li>\n<\/ul>\n\n\n\n<p>After setting up its environment, the user should familiarise himself with the essential aspects of FPGA developments on imperix controllers by reading the following pages:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">PN116: <strong>Imperix firmware IP<\/strong> product guide<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126: Retrieving&nbsp;<strong>ADC measurements<\/strong>&nbsp;from the FPGA<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128: Exchanging data between the&nbsp;<strong>CPU and the FPGA<\/strong><\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127: Driving the<strong>&nbsp;PWM output chain<\/strong><\/a><\/li>\n<\/ul>\n\n\n\n<p>After the basics are mastered, the following advanced product notes can be explored:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\">PN129: Using an\u00a0<strong>ILA<\/strong>\u00a0to debug an FPGA design<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\">PN179: Accessing the\u00a0<strong>USR pins<\/strong>\u00a0in the FPGA sandbox<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">PN118: Example of FPGA-based\u00a0<strong>Aurora communication<\/strong><\/a><\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-learning-about-automated-generation-tools-for-fpga\">Learning about automated generation tools for FPGA<\/h2>\n\n\n\n<p>Traditionally, FPGA designs are implemented using HDL languages such as VHDL or Verilog. However, the user can use <strong>automated code generation tools<\/strong> to design FPGA modules without writing any line of any HDL language. These tools can be separated into two main categories: <strong>HDL <\/strong>tools and <strong>HLS<\/strong> tools.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>HDL-level tools<\/strong><\/h3>\n\n\n\n<p>These tools provide a graphical or model-based interface while still granting the developer low-level hardware control, right down to individual flip-flops. Because they operate at the register-transfer level, the design process remains conceptually very close to writing raw VHDL or Verilog. They are recommended to implement peripherals such as custom PWM modulators or communication interfaces.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\">PN161: Xilinx <strong>System Generator<\/strong> introduction<\/a> (now <em><strong><strong><em>AMD Vitis Model Composer HDL<\/em><\/strong><\/strong><\/em>)<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\">PN162: <strong>MATLAB<\/strong> <strong>HDL Coder<\/strong> introduction<\/a><\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>High-Level Synthesis (HLS)<\/strong> tools<\/h3>\n\n\n\n<p>Unlike HDL-level tools, High-Level Synthesis tools abstract away the low-level hardware architecture. They are particularly well-suited for designing advanced control algorithms, working with complex data types, and implementing sophisticated mathematical functions without needing to manage the underlying register-level timing.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">PN163: Xilinx <strong>Model Composer<\/strong> introduction<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">PN164: Xilinx <strong>Vitis HLS<\/strong> introduction<\/a><\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Only Vitis HLS is free of cost<\/strong>, the others require a paid license.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-implementing-closed-loop-control-of-a-buck-converter-in-fpga\">Implementing <strong>closed-loop control of a buck converter<\/strong> in FPGA<\/h2>\n\n\n\n<p>The following notes show a step-by-step example of how to implement the <strong>closed-loop control of a buck converter<\/strong> in FPGA.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"740\" height=\"298\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/08\/Block_diagram_HLS_IPs-1.png\" alt=\"FPGA-based PI controller implemented with high level synthesis tools\" class=\"wp-image-7129\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/Block_diagram_HLS_IPs-1.png 740w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/Block_diagram_HLS_IPs-1-300x121.png 300w\" sizes=\"auto, (max-width: 740px) 100vw, 740px\" \/><figcaption class=\"wp-element-caption\">FPGA-based control of a buck converter<\/figcaption><\/figure>\n\n\n\n<p>The first page presents three ways of implementing a custom <strong>triangular carrier PWM modulator<\/strong>, using VHDL or code generation tools such as <strong><em>AMD Vitis Model Composer HDL<\/em><\/strong> (formerly System Generator) or <em><strong>MATLAB HDL Coder<\/strong><\/em>.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">TN141: Custom FPGA <strong>PWM modulator<\/strong> implementation<\/a><\/p>\n\n\n\n<p>The second page explains how to create a <strong>PI-based current controller for a buck converter<\/strong> using high-level synthesis (HLS) tools such as <strong><em>Model Composer<\/em> <\/strong>and <em><strong>Vitis HLS<\/strong><\/em>.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">TN142: <strong>PI-based current controller<\/strong> for a buck converter<\/a><\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-executing-power-converter-control-algorithms-on-an-fpga\">Executing power converter control algorithms on an FPGA<\/h2>\n\n\n\n<p>The <strong>FPGA-based control of a grid-tied inverter<\/strong> example shows how an entire control algorithm can be ported to the FPGA and reach a control frequency above <strong>650 kHz<\/strong>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"558\" height=\"269\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Converter_scheme_v2_100pc.png\" alt=\"Grid-tied voltage-source inverter controlled by an FPGA\" class=\"wp-image-12462\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Converter_scheme_v2_100pc.png 558w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Converter_scheme_v2_100pc-300x145.png 300w\" sizes=\"auto, (max-width: 558px) 100vw, 558px\" \/><\/figure>\n<\/div>\n\n\n<p class=\"has-text-align-center\"><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">TN147: FPGA-based control of a <strong>grid-tied inverter<\/strong><\/a><\/p>\n\n\n\n<p>This example also demonstrates how High-Level Synthesis tools can be leveraged to generate complex FPGA modules such as a <strong>grid synchronization module with dq-PLL<\/strong> or a <strong>dq current control<\/strong>.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-implementation-pll\">TN143: FPGA implementation of a <strong>PLL for grid synchronization<\/strong><\/a><br><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\">TN144: <strong>DQ current control<\/strong> using FPGA-based PI controllers<\/a><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Implementing communication with other devices<\/h2>\n\n\n\n<p>FPGA can also be used to implement high-speed communication with other devices such as hardware-in-the-loop (HIL) or third-party FPGA. The following page details how SFP ports can be used to communicate using the Aurora protocol.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">PN118: Example of FPGA-based <strong>Aurora 8B\/10B<\/strong> communication<\/a><br><a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices?currentThread=sfp-communication-with-third-party-devices\" type=\"link\" id=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices?currentThread=sfp-communication-with-third-party-devices\">PN109: <strong>SFP communication with third-party devices<\/strong><\/a><br><a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-opal-rt-via-sfp?currentThread=sfp-communication-with-third-party-devices\">PN110: <strong>Aurora link with OPAL-RT<\/strong> via SFP<\/a><br><a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-plexim-via-sfp?currentThread=sfp-communication-with-third-party-devices\">PN111: <strong>Aurora link with Plexim<\/strong> via SFP<\/a><br><a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\">PN122: <strong>SFP communication with an RTDS<\/strong> MMC simulator<\/a><\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-additional-examples\">Additional examples<\/h2>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">These older examples were written before AXI4-Stream was introduced to the FPGA development template. As such, they may not implement all the recommendations provided in the pages above.<\/div>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-spi-communication-ip\">FPGA-based SPI communication IP for A\/D converter<\/a><br><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-direct-torque-control\">FPGA-based Direct Torque Control using Vivado HLS<\/a><br><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-hysteresis-controller-hdl-coder\">FPGA-based hysteresis controller for three-phase inverter using HDL Coder<\/a><br><a href=\"https:\/\/imperix.com\/doc\/implementation\/hysteresis-current-control\">FPGA-based hysteresis current controller for three-phase inverter<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Usually, the user programs the imperix controller&#8217;s CPU using imperix ACG SDK or C++ SDK, and uses the pre-implemented FPGA peripherals such as the ADC&#8230;<\/p>\n","protected":false},"author":4,"featured_media":12409,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[],"software-environments":[],"provided-results":[],"related-products":[31,32,92,110],"guidedreadings":[],"tutorials":[131],"user-manuals":[],"coauthors":[70],"class_list":["post-3438","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-tpi","tutorials-direct-torque-control-of-a-permanent-magnet-synchronous-motor"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - 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imperix\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/fpga-development-on-imperix-controllers#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/fpga-development-on-imperix-controllers#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/06\\\/3_2_ratio_TN169_2.png\",\"datePublished\":\"2021-06-10T09:43:16+00:00\",\"dateModified\":\"2026-04-16T11:26:16+00:00\",\"description\":\"This content table summarizes the documentation pages relating to FPGA development on imperix controllers.\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/fpga-development-on-imperix-controllers#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/fpga-development-on-imperix-controllers\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/fpga-development-on-imperix-controllers#primaryimage\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/06\\\/3_2_ratio_TN169_2.png\",\"contentUrl\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/06\\\/3_2_ratio_TN169_2.png\",\"width\":450,\"height\":300,\"caption\":\"FPGA development on imperix controllers\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/help\\\/fpga-development-on-imperix-controllers#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Knowledge base\",\"item\":\"https:\\\/\\\/imperix.com\\\/doc\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Product notes\",\"item\":\"https:\\\/\\\/imperix.com\\\/doc\\\/category\\\/help\"},{\"@type\":\"ListItem\",\"position\":3,\"name\":\"FPGA development on imperix controllers\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#website\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/\",\"name\":\"imperix\",\"description\":\"power electronics\",\"publisher\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/imperix.com\\\/doc\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#organization\",\"name\":\"imperix\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#\\\/schema\\\/logo\\\/image\\\/\",\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/03\\\/imperix_logo.png\",\"contentUrl\":\"https:\\\/\\\/imperix.com\\\/doc\\\/wp-content\\\/uploads\\\/2021\\\/03\\\/imperix_logo.png\",\"width\":350,\"height\":120,\"caption\":\"imperix\"},\"image\":{\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#\\\/schema\\\/logo\\\/image\\\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/imperix.com\\\/doc\\\/#\\\/schema\\\/person\\\/a69a3bda75b05d0923cc76d7268cc94f\",\"name\":\"Beno\u00eet Steinmann\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g3b3f3d8e66019ebcb2848094940b98c0\",\"url\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g\",\"contentUrl\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g\",\"caption\":\"Beno\u00eet Steinmann\"},\"description\":\"Benoit is an embedded systems expert and the leader of software and firmware developments at imperix. On the knowledge base, he is the author of numerous software reference documents.\",\"sameAs\":[\"https:\\\/\\\/www.linkedin.com\\\/in\\\/benoit-steinmann\\\/\"],\"url\":\"https:\\\/\\\/imperix.com\\\/doc\\\/author\\\/steinmann\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"FPGA development on imperix controllers - imperix","description":"This content table summarizes the documentation pages relating to FPGA development on imperix controllers.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers","og_locale":"en_US","og_type":"article","og_title":"FPGA development on imperix controllers - imperix","og_description":"This content table summarizes the documentation pages relating to FPGA development on imperix controllers.","og_url":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers","og_site_name":"imperix","article_published_time":"2021-06-10T09:43:16+00:00","article_modified_time":"2026-04-16T11:26:16+00:00","og_image":[{"width":450,"height":300,"url":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/3_2_ratio_TN169_2.png","type":"image\/png"}],"author":"Beno\u00eet Steinmann","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Beno\u00eet Steinmann","Est. reading time":"5 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#article","isPartOf":{"@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers"},"author":{"name":"Beno\u00eet Steinmann","@id":"https:\/\/imperix.com\/doc\/#\/schema\/person\/a69a3bda75b05d0923cc76d7268cc94f"},"headline":"FPGA development on imperix controllers","datePublished":"2021-06-10T09:43:16+00:00","dateModified":"2026-04-16T11:26:16+00:00","mainEntityOfPage":{"@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers"},"wordCount":801,"commentCount":0,"publisher":{"@id":"https:\/\/imperix.com\/doc\/#organization"},"image":{"@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#primaryimage"},"thumbnailUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/3_2_ratio_TN169_2.png","articleSection":["Product notes"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#respond"]}]},{"@type":"WebPage","@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers","url":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers","name":"FPGA development on imperix controllers - imperix","isPartOf":{"@id":"https:\/\/imperix.com\/doc\/#website"},"primaryImageOfPage":{"@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#primaryimage"},"image":{"@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#primaryimage"},"thumbnailUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/3_2_ratio_TN169_2.png","datePublished":"2021-06-10T09:43:16+00:00","dateModified":"2026-04-16T11:26:16+00:00","description":"This content table summarizes the documentation pages relating to FPGA development on imperix controllers.","breadcrumb":{"@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#primaryimage","url":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/3_2_ratio_TN169_2.png","contentUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/3_2_ratio_TN169_2.png","width":450,"height":300,"caption":"FPGA development on imperix controllers"},{"@type":"BreadcrumbList","@id":"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Knowledge base","item":"https:\/\/imperix.com\/doc\/"},{"@type":"ListItem","position":2,"name":"Product notes","item":"https:\/\/imperix.com\/doc\/category\/help"},{"@type":"ListItem","position":3,"name":"FPGA development on imperix controllers"}]},{"@type":"WebSite","@id":"https:\/\/imperix.com\/doc\/#website","url":"https:\/\/imperix.com\/doc\/","name":"imperix","description":"power electronics","publisher":{"@id":"https:\/\/imperix.com\/doc\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/imperix.com\/doc\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/imperix.com\/doc\/#organization","name":"imperix","url":"https:\/\/imperix.com\/doc\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/imperix.com\/doc\/#\/schema\/logo\/image\/","url":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/imperix_logo.png","contentUrl":"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/imperix_logo.png","width":350,"height":120,"caption":"imperix"},"image":{"@id":"https:\/\/imperix.com\/doc\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/imperix.com\/doc\/#\/schema\/person\/a69a3bda75b05d0923cc76d7268cc94f","name":"Beno\u00eet Steinmann","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/secure.gravatar.com\/avatar\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g3b3f3d8e66019ebcb2848094940b98c0","url":"https:\/\/secure.gravatar.com\/avatar\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/22a9252907f853f91d07b143dfcc84f6ec0cc31f6b72408b503a7026eed5b109?s=96&d=mm&r=g","caption":"Beno\u00eet Steinmann"},"description":"Benoit is an embedded systems expert and the leader of software and firmware developments at imperix. On the knowledge base, he is the author of numerous software reference documents.","sameAs":["https:\/\/www.linkedin.com\/in\/benoit-steinmann\/"],"url":"https:\/\/imperix.com\/doc\/author\/steinmann"}]}},"_links":{"self":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts\/3438","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/comments?post=3438"}],"version-history":[{"count":92,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts\/3438\/revisions"}],"predecessor-version":[{"id":45306,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/posts\/3438\/revisions\/45306"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/media\/12409"}],"wp:attachment":[{"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/media?parent=3438"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/categories?post=3438"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/tags?post=3438"},{"taxonomy":"software-environments","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/software-environments?post=3438"},{"taxonomy":"provided-results","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/provided-results?post=3438"},{"taxonomy":"related-products","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/related-products?post=3438"},{"taxonomy":"guidedreadings","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/guidedreadings?post=3438"},{"taxonomy":"tutorials","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/tutorials?post=3438"},{"taxonomy":"user-manuals","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/user-manuals?post=3438"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/imperix.com\/doc\/wp-json\/wp\/v2\/coauthors?post=3438"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}