{"id":3489,"date":"2021-06-15T11:49:48","date_gmt":"2021-06-15T11:49:48","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=3489"},"modified":"2025-05-07T12:57:49","modified_gmt":"2025-05-07T12:57:49","slug":"high-level-synthesis-for-fpga","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga","title":{"rendered":"High-Level Synthesis for FPGA developments"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\/#Integrating-HLS-designs-in-the-FPGA\" >Integrating HLS designs in the FPGA<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\/#Description-of-the-design\" >Description of the design<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\/#CPU-side-implementation-using-Simulink\" >CPU-side implementation using Simulink<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\/#FPGA-side-implementation-using-Vivado\" >FPGA-side implementation using Vivado<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p><strong>High-level synthesis (HLS)<\/strong> tools greatly facilitate the implementation of complex power electronics controller algorithms in FPGA. Indeed HLS tools allow the user to work at a higher level of abstraction. For instance, the user can use <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Xilinx Vitis HLS<\/a> to develop FPGA modules using <strong>C\/C++<\/strong> or the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> plug-in for <strong>Simulink<\/strong> to use graphical programming instead.<\/p>\n\n\n\n<p>This page shows how IPs generated using high-level synthesis tools can be integrated into the FPGA of an imperix power controller. To this end, the example of a <strong>PI-based current controller for a buck converter<\/strong> is used to illustrate all the required steps.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Block_diagram_FPGA_CPU_overall.png\" alt=\"Power converter control FPGA\" class=\"wp-image-10456\" width=\"499\" height=\"346\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Block_diagram_FPGA_CPU_overall.png 499w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/Block_diagram_FPGA_CPU_overall-300x208.png 300w\" sizes=\"auto, (max-width: 499px) 100vw, 499px\" \/><figcaption>Power converter control FPGA<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-integrating-hls-designs-in-the-fpga\"><span class=\"ez-toc-section\" id=\"Integrating-HLS-designs-in-the-FPGA\"><\/span>Integrating HLS designs in the FPGA<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-description-of-the-design\"><span class=\"ez-toc-section\" id=\"Description-of-the-design\"><\/span>Description of the design<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The image below shows the example that will be implemented on this page. It is a PI-based current controller for a buck converter, based on the algorithm presented on the <a href=\"https:\/\/imperix.com\/doc\/implementation\/basic-pi-control\">PI controller implementation for current control<\/a> technical note. This example uses the following resources<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>the <strong>FPGA control starter template<\/strong>  from the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">getting started with FPGA<\/a> guide<\/li><li>the <strong>PWM modulator IP<\/strong> from the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">FPGA PWM modulator<\/a> example<\/li><li>the <strong>high-level synthesis PI-based current control IP<\/strong> from either<ul><li>the C++ implementation presented in the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Xilinx Vitis HLS<\/a> guide<\/li><li>or the Simulink implemention presented in the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> guide<\/li><\/ul><\/li><\/ul>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/Block_diagram_HLS_IPs-1.png\" alt=\"FPGA-based PI controller implemented with high level synthesis tools\" class=\"wp-image-7129\" width=\"740\" height=\"298\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/Block_diagram_HLS_IPs-1.png 740w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/Block_diagram_HLS_IPs-1-300x121.png 300w\" sizes=\"auto, (max-width: 740px) 100vw, 740px\" \/><\/figure>\n\n\n\n<p>The <strong>axis interface<\/strong> provides the inputs of the current control algorithm in form of<strong> AXI4-Stream<\/strong> ports. The following ports are used:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li><code>CPU2FPGA_00 <\/code>for the current reference <code>Il_ref <\/code>(32-bit single-precision)<\/li><li><code>CPU2FPGA_01 <\/code>for the parameter <code>Kp <\/code>(32-bit single-precision)<\/li><li><code>CPU2FPGA_02 <\/code>for the parameter <code>Ki <\/code>(32-bit single-precision)<\/li><li><code>ADC_00 <\/code>for the measured current <code>Il<\/code> (16-bit signed integer)<\/li><li><code>ADC_01 <\/code>for the measured output voltage of the converter <code>Vout <\/code>(16-bit signed integer)<\/li><li><code>ADC_02 <\/code>for the measured input voltage of the converter <code>Vint <\/code>(16-bit signed integer)<\/li><li><code>Ts <\/code>for the sampling period in nanoseconds (32-bit unsigned integer)<\/li><\/ul>\n\n\n\n<p>Aside from AXI4-Stream data, the current control IP also uses the ports:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li><code>CLOCK_period <\/code>for the PWM period in ticks (16-bit unsigned)<\/li><li><code>nReset_ctrl <\/code>to reset the PI when the controller is not in OPERATING state<\/li><\/ul>\n\n\n\n<p>Using these signals, the HLS IP computes a 16-bit unsigned <code>duty_cycle_ticks<\/code> that is forwarded to the PWM IP. And finally, the PWM IP uses the <code>sb_pwm<\/code> driver to output the PWM signals to optical fibers of the B-Box RCP controller. The PWM IP and the SB-PWM driver are further documented on the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">FPGA PWM modulator<\/a> page.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The ADC values provided by the starter template are the raw result from the ADC chips. They are multiplied by a <em>gain <\/em>inside the HLS IP to obtain physical values. An example of <em>gain<\/em> computation is available on the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC block<\/a> help page.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-cpu-side-implementation-using-simulink\"><span class=\"ez-toc-section\" id=\"CPU-side-implementation-using-Simulink\"><\/span>CPU-side implementation using Simulink<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The CPU-side model is quite simple, as the control algorithm runs entirely in the FPGA. The CPU code provides the current reference and Kp\/Ki parameters, operates the PI reset signal, and configures the PWM outputs.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"693\" height=\"492\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-35.png\" alt=\"\" class=\"wp-image-4882\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-35.png 693w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-35-300x213.png 300w\" sizes=\"auto, (max-width: 693px) 100vw, 693px\" \/><\/figure><\/div>\n\n\n\n<p>The <em>single2sbo<\/em> MATLAB Function blocks are used to map the current reference <strong>Il_ref<\/strong> and the <strong>Kp<\/strong>, <strong>Ki <\/strong>parameter to the CPU2FPGA ports.<\/p>\n\n\n\n<p>This <strong>nReset_ctrl <\/strong>signal is used to keep the PI integrator at reset when the controller is not in OPERATING state. As documented in <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">Getting started with FPGA<\/a>, this reset signal is controlled using <em>SBO_63<\/em>. To obtain the desired behavior, we&#8217;ll simply connect the reset output of a <a href=\"https:\/\/imperix.com\/doc\/software\/core-state\">Core state<\/a> block to <em>SBO_63<\/em>.<\/p>\n\n\n\n<p>And finally, the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-pwm\">SB-PWM<\/a> block is used to activate the output PWM <strong>channel 0 (CH0)<\/strong> (lane #0 and lane #1). The output is configured as <strong>Dual (PWM_H + PWM_L)<\/strong> with a <strong>deadtime <\/strong>of 1 \u00b5s. This configuration expects a PWM signal coming to <strong>sb_pwm[0]<\/strong> input of the <em>imperix firmware<\/em> IP and will automatically generate the complementary signals with the configured deadtime.<\/p>\n\n\n\n<p>The ADC blocks are only used to retrieve the analog input signals at the CPU level for real-time monitoring. They do not affect the closed-loop control behavior.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-fpga-side-implementation-using-vivado\"><span class=\"ez-toc-section\" id=\"FPGA-side-implementation-using-Vivado\"><\/span>FPGA-side implementation using Vivado<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The <strong>TN142_vivado_design.pdf<\/strong> file below shows the full Vivado FPGA design. Here are the step-by-step instructions to reproduce it.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"361\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-106-1024x361.png\" alt=\"\" class=\"wp-image-6919\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-106-1024x361.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-106-300x106.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-106-768x270.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-106-1536x541.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-106.png 1979w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<ol class=\"wp-block-list\"><li>Create an FPGA control implementation starter template by following the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">Getting started with FPGA control implementation<\/a>.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1019\" height=\"990\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/template_screenshot.png\" alt=\"\" class=\"wp-image-3695\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/template_screenshot.png 1019w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/template_screenshot-300x291.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/template_screenshot-768x746.png 768w\" sizes=\"auto, (max-width: 1019px) 100vw, 1019px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"2\"><li>Add the <em>PWM IP<\/em> (from the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">custom PWM in FPGA<\/a> page) and <em>current control IP<\/em> (from the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Xilinx Vitis HLS<\/a> guide or the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> guide) into your Vivado project. In the screenshots of this example, we&#8217;ll use the IPs generated using System Generator and Vitis HLS, respectively. <br>To read the <code>duty_cycle_ticks <\/code>only when <code>duty_cycle_ticks_ap_vld <\/code>is &#8216;1&#8217;, the <em>RAM-based Shift Register<\/em> IP is used. With the configuration shown in the screenshot below, this block adds one register stage that acts as a buffer. It keeps the last computed duty cycle until a new value has been computed. When a new value is available, it replaces the old one.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-65-1024x369.png\" alt=\"\" class=\"wp-image-4942\" width=\"729\" height=\"262\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-65-1024x369.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-65-300x108.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-65-768x277.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-65.png 1069w\" sizes=\"auto, (max-width: 729px) 100vw, 729px\" \/><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-25.png\" alt=\"\" class=\"wp-image-4780\" width=\"688\" height=\"437\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-25.png 812w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-25-300x191.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-25-768x488.png 768w\" sizes=\"auto, (max-width: 688px) 100vw, 688px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"3\"><li>Add a <strong>Constant<\/strong> IP to set all the 31 unused sb_pwm outputs to &#8216;0&#8217;. Set its <em>Const Width<\/em> to 31 and its <em>Const Val <\/em>to 0.<\/li><li>Add a <strong>Concat<\/strong> IP. It will serve to concat the pwm output of the PWM IP with the zeros of the Constant IP.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-69.png\" alt=\"\" class=\"wp-image-4946\" width=\"586\" height=\"312\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-69.png 773w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-69-300x160.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-69-768x409.png 768w\" sizes=\"auto, (max-width: 586px) 100vw, 586px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"5\"><li>Add a <strong>Constant<\/strong> IP to set to set the update rate. &#8216;0&#8217; = single rate, &#8216;1&#8217; = double rate.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-68.png\" alt=\"\" class=\"wp-image-4945\" width=\"414\" height=\"223\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-68.png 508w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-68-300x162.png 300w\" sizes=\"auto, (max-width: 414px) 100vw, 414px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"6\"><li>Connect the clock signals as below:<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-71.png\" alt=\"\" class=\"wp-image-4948\" width=\"576\" height=\"375\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-71.png 721w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-71-300x196.png 300w\" sizes=\"auto, (max-width: 576px) 100vw, 576px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"7\"><li>Connect the AXI4-Streams<ul><li><code><strong>M_AXIS_CPU2FPGA_00 <\/strong><\/code>to <code><strong>Il_ref_V<\/strong><\/code><\/li><li><strong><code>M_AXIS_CPU2FPGA_01 <\/code><\/strong>to <code><strong>Kp_V<\/strong><\/code><\/li><li><strong><code>M_AXIS_CPU2FPGA_02 <\/code><\/strong>to <code><strong>Ki_V<\/strong><\/code><\/li><li><strong><code>M_AXIS_ADC_00 <\/code><\/strong>to <code><strong>Il_raw_v<\/strong><\/code><\/li><li><strong><code>M_AXIS_ADC_01 <\/code><\/strong>to voltage <code><strong>Vout_raw_V<\/strong><\/code><\/li><li><strong><code>M_AXIS_ADC_02 <\/code><\/strong>to <code><strong>Vint_raw_V<\/strong><\/code><\/li><li><code><strong>M_AXIS_Ts <\/strong><\/code>to <code><strong>Ts_V<\/strong><\/code><\/li><\/ul><\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-77.png\" alt=\"\" class=\"wp-image-5025\" width=\"541\" height=\"789\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-77.png 618w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-77-206x300.png 206w\" sizes=\"auto, (max-width: 541px) 100vw, 541px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"8\"><li>The provided <em>Delay Counter<\/em> VHDL module (delay_counter.vhd) measures the elapsed time between two signals and outputs a time in nanoseconds, encoded as a uint32.<br>In this design, the <em>delay counter<\/em> modules are used purely for debugging purposes. As shown in the image below, one is used to measure the <em>FPGA processing delay<\/em>, which is the delay between the <code>adc_done_pulse <\/code>and the <code>duty_cycle_ticks_ap_vld<\/code>. Another module is used to measure the <em>FPGA cycle delay<\/em> by measuring the delay between the <code>sampling_pulse <\/code>and the <code>duty_cycle_ticks_ap_vld<\/code>. More information on what these delays represent are available on the <a href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\">discrete control delay<\/a> product node.<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"480\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-78-1024x480.png\" alt=\"\" class=\"wp-image-5026\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-78-1024x480.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-78-300x141.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-78-768x360.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-78.png 1307w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<ol class=\"wp-block-list\" start=\"9\"><li>Connect the <code>nReset_ctrl<\/code> signal to <code>ap_rst_n<\/code>. <\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-79.png\" alt=\"\" class=\"wp-image-5027\" width=\"665\" height=\"277\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-79.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/08\/image-79-300x125.png 300w\" sizes=\"auto, (max-width: 665px) 100vw, 665px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"10\"><li>And finally connect the clk signals to <code>clk_250_mhz<\/code>.<\/li><li>Click\u00a0<strong>Generate bitstream<\/strong>. It will launch the synthesis, implementation, and bitstream generation<\/li><li>Once the bitstream generation is completed, click on\u00a0<strong>File\u00a0<\/strong>\u2192\u00a0<strong>Export\u00a0<\/strong>\u2192\u00a0<strong>Export Bitstream File\u2026<\/strong>\u00a0to save the bitstream somewhere on your computer.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>High-level synthesis (HLS) tools greatly facilitate the implementation of complex power electronics controller algorithms in FPGA. Indeed HLS tools allow the user to work at&#8230;<\/p>\n","protected":false},"author":4,"featured_media":7134,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[4],"tags":[53,17],"software-environments":[106,103],"provided-results":[],"related-products":[50,31,32,92,166],"guidedreadings":[],"tutorials":[130],"user-manuals":[],"coauthors":[70],"class_list":["post-3489","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-implementation","tag-current-control","tag-fpga-programming","software-environments-fpga","software-environments-matlab","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","tutorials-custom-fpga-pwm-modulator-implementation"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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