{"id":40107,"date":"2026-02-06T15:20:10","date_gmt":"2026-02-06T15:20:10","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=40107"},"modified":"2026-04-10T10:13:21","modified_gmt":"2026-04-10T10:13:21","slug":"timing-configuration-on-imperix-controllers","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers","title":{"rendered":"Timing configuration on imperix controllers"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Timing-architecture\" >Timing architecture<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Timing-configuration\" >Timing configuration<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Basic-timing-configurations\" >Basic timing configurations<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Single-rate-update\" >Single rate update<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Double-rate-update\" >Double rate update<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Advanced-timing-configurations\" >Advanced timing configurations<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Postscaler\" >Postscaler<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Data-history\" >Data history<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Variable-switching-frequency\" >Variable switching frequency<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Multi-rate-execution\" >Multi-rate execution<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\/#Related-topics\" >Related topics<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>This article details the underlying clock architecture and timing configurations of imperix controllers, focusing on the four internal time bases (CLK0\u2013CLK3) that govern ADC sampling, control loop execution, and PWM modulation. These timing principles are common across the entire imperix hardware family and are applicable to both standalone systems and synchronized multi-controller networks. <br>While the <a href=\"https:\/\/imperix.com\/doc\/help\/simulation-essentials-simulink?currentThread=getting-started-with-acg-sdk\" target=\"_blank\" rel=\"noreferrer noopener\">Simulation Essentials<\/a> pages cover general model setup and <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics?currentThread=b-board-pro\" target=\"_blank\" rel=\"noreferrer noopener\">Sampling Techniques<\/a> explores data acquisition theory, this page provides the specific technical foundation for the clocking mechanisms that support both.<\/p>\n\n\n\n<p>Additionally, a set of ready-to-use Simulink\/PLECS example projects is provided to demonstrate the implementation of a double-rate update configuration.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Timing-architecture\"><\/span>Timing architecture<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The timing architecture of imperix controllers typically differs from the distributed peripheral model of conventional microcontrollers by using a centralized FPGA-based timing engine. This approach abstracts the underlying hardware complexity, allowing the user to focus on control algorithms rather than taxing manual register management. <\/p>\n\n\n\n<p>Conventional MCUs also often introduce timing jitter due to variable interrupt latencies (where the CPU&#8217;s response time to an ADC trigger fluctuates). In contrast, the imperix architecture utilizes a 250 MHz global clock to align all resources within a single time domain. This design achieves nanosecond-level determinism between resources and bypasses the interrupt latencies found in traditional architectures. <br><br>The system also supports multiple phase-locked timing domains, maintaining precise synchronization across different frequencies in complex timing configuration. To accommodate various hardware requirements, the 250 MHz clock is divided into four distinct clocks, CLK0 through CLK3 (see Fig. 1), which can then be allocated to resources such as ADCs, PWM modulators, and CPU interrupts.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1560\" height=\"830\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Clock-generation.jpg\" alt=\"Clock generation and timing manipulation at the hardware level in Imperix controllers\" class=\"wp-image-45092\" style=\"width:600px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Clock-generation.jpg 1560w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Clock-generation-300x160.jpg 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Clock-generation-1024x545.jpg 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Clock-generation-768x409.jpg 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Clock-generation-1536x817.jpg 1536w\" sizes=\"auto, (max-width: 1560px) 100vw, 1560px\" \/><figcaption class=\"wp-element-caption\">Figure 1 : Clocks generation in imperix controllers<\/figcaption><\/figure>\n<\/div>\n\n\n<p>Among the four time bases,&nbsp;CLK0 has a special role: it is always active and sets the timing for both sampling and CPU control execution. Two important internal signals are derived from&nbsp;CLK0, which are :<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The&nbsp;CPU interrupt clock&nbsp;(frequency&nbsp;\\(F_{\\text{CPU}}\\)), which triggers the execution of the control task. When required,&nbsp;\\(F_{\\text{CPU}}\\)&nbsp;can be obtained by&nbsp;decimating&nbsp;\\(F_{\\text{SCLK}}\\) using a <a href=\"#postscaler\" type=\"internal\" id=\"#postscaler\">postscaler<\/a>.<\/li>\n\n\n\n<li>SCLK, the physical sampling clock (frequency&nbsp;\\(F_{\\text{SCLK}}\\)). It runs at the same rate as CLK0, but with a user-defined&nbsp;constant phase shift&nbsp;that sets the exact sampling instant.<\/li>\n<\/ul>\n\n\n\n<p>Unlike CLK0, CLK1-3 can only be used as a time base for PWM modulators. A summary of the uses of the different clocks is given in Table 1.<\/p>\n\n\n\n<figure class=\"wp-block-table is-style-stripes\"><table class=\"has-fixed-layout\"><thead><tr><th class=\"has-text-align-center\" data-align=\"center\">Clock<\/th><th class=\"has-text-align-center\" data-align=\"center\">Mandatory<\/th><th class=\"has-text-align-center\" data-align=\"center\">Where to configure<\/th><th class=\"has-text-align-center\" data-align=\"center\">Used for<\/th><th class=\"has-text-align-center\" data-align=\"center\">Variable frequency support<\/th><\/tr><\/thead><tbody><tr><td class=\"has-text-align-center\" data-align=\"center\">CLK0<\/td><td class=\"has-text-align-center\" data-align=\"center\">Yes<\/td><td class=\"has-text-align-center\" data-align=\"center\">CONFIG block<\/td><td class=\"has-text-align-center\" data-align=\"center\">CPU, ADC, <br>PWM modulators<\/td><td class=\"has-text-align-center\" data-align=\"center\">No<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">CLK1<\/td><td class=\"has-text-align-center\" data-align=\"center\">No<\/td><td class=\"has-text-align-center\" data-align=\"center\">CLK block<\/td><td class=\"has-text-align-center\" data-align=\"center\">PWM modulators<\/td><td class=\"has-text-align-center\" data-align=\"center\">Yes<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">CLK2<\/td><td class=\"has-text-align-center\" data-align=\"center\">No<\/td><td class=\"has-text-align-center\" data-align=\"center\">CLK block<\/td><td class=\"has-text-align-center\" data-align=\"center\">PWM modulators<\/td><td class=\"has-text-align-center\" data-align=\"center\">Yes<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">CLK3<\/td><td class=\"has-text-align-center\" data-align=\"center\">No<\/td><td class=\"has-text-align-center\" data-align=\"center\">CLK block<\/td><td class=\"has-text-align-center\" data-align=\"center\">PWM modulators<\/td><td class=\"has-text-align-center\" data-align=\"center\">Yes<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Table 1 : Summary of clock functions and configuration<\/figcaption><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<p>Finally, thanks to <a href=\"https:\/\/imperix.com\/technology\/low-latency-communication\/\">RealSync<\/a>, all clocks within a network of imperix controllers are synchronized with a timing accuracy of \u00b12 ns. This means that the phase coherence and synchronization inherent to local resources, driven by the common 250 MHz time base, are maintained across the entire distributed network.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Timing-configuration\"><\/span>Timing configuration<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>At the software level, the four clocks described above are configured through the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> and <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> blocks. These are available within the ACG SDK and illustrated in Fig. 2.<\/p>\n\n\n\n<p>The CONFIG block is mandatory for every Simulink or PLECS model. Among its various functions, it handles the configuration of CLK0 and its associated signals. In contrast, CLK blocks (CLK1\u20133) are optional and can run at variable frequency. These clocks are only used&nbsp;to drive modulation blocks (PWMs), whenever the PWM time base must differ from CLK0. Further details regarding the simulation of these blocks can be found on the <a href=\"https:\/\/imperix.com\/doc\/help\/simulation-essentials-simulink?currentThread=getting-started-with-acg-sdk\">PN135<\/a> and <a href=\"https:\/\/imperix.com\/doc\/help\/simulation-essentials-plecs?currentThread=getting-started-with-acg-sdk\">PN137<\/a> pages.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"635\" height=\"85\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/image-8.png\" alt=\"Timing configuration blocks using imperix's SDK\" class=\"wp-image-43485\" style=\"width:420px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/image-8.png 635w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/image-8-300x40.png 300w\" sizes=\"auto, (max-width: 635px) 100vw, 635px\" \/><figcaption class=\"wp-element-caption\">Figure 2 : Configuration blocks for the four different clocks (The displayed values are only for the sake of example)<\/figcaption><\/figure>\n<\/div>\n\n\n<p>In practice, most control schemes can rely on CLK0 only. CLK0 is configured in the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> block and sets the sampling and CPU interrupt frequency, i.e., how often the control code is executed. In many applications, CLK0 is also used to define the PWM switching frequency. This common arrangement is often referred to as single rate update, and it covers a large fraction of standard use cases. This case is illustrated in Fig. 3.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"521\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU_config-1024x521.png\" alt=\"Single rate update configuration using simulink.\" class=\"wp-image-44861\" style=\"width:780px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU_config-1024x521.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU_config-300x153.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU_config-768x391.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU_config-1536x782.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU_config.png 1560w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Figure 3 : Clocks setting and allocation in Simulink in single rate update mode configuration<\/figcaption><\/figure>\n<\/div>\n\n\n<p>Consequently, the clock configuration impacts three core subsystems as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\"><strong>ADC<\/strong><\/a> resources are always referenced to CLK0, which defines the sampling instants according to the physical sampling clock SCLK and with a frequency of \\(F_{\\text{SCLK}}\\).<\/li>\n\n\n\n<li><strong>CPU <\/strong>execution is always tied to CLK0 with a configurable phase offset and postscaler.<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/software\/pulse-width-modulator\"><strong>PWM<\/strong><\/a> blocks can be referenced to any of CLK0\u2013CLK3. The selected PWM clock can be an integer multiple or submultiple of CLK0, or it may be non-integer related (including variable-frequency operation), depending on the modulation scheme and the chosen clock source.<\/li>\n<\/ul>\n\n\n\n<p>Figure 4 shows the use of CLK1 in a configuration where the control loop is executed twice as fast as the PWMs. This configuration is also called double rate update and is detailed later.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"780\" height=\"491\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_clk.png\" alt=\"\" class=\"wp-image-43501\" style=\"width:780px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_clk.png 780w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_clk-300x189.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_clk-768x483.png 768w\" sizes=\"auto, (max-width: 780px) 100vw, 780px\" \/><figcaption class=\"wp-element-caption\">Figure 4 : Clocks setting and allocation in Simulink in double rate update configuration<\/figcaption><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\" id=\"Basic-timing-configurations\"><span class=\"ez-toc-section\" id=\"Basic-timing-configurations\"><\/span>Basic timing configurations<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>On imperix controllers, the timing configurations arise from the relationship between CLK0 and the selected PWM time base. While CLKO provides a fixed reference for ADC sampling and CPU execution, the PWM clocks determine the carrier frequency of the <a href=\"https:\/\/imperix.com\/doc\/software\/pulse-width-modulator\">modulators<\/a> and the specific instants at which the duty cycles are latched. <\/p>\n\n\n\n<p>Those duty cycle update instants are not the same for all PWM carrier types. With a sawtooth (single-edge) carrier, there is only one effective update opportunity per PWM period, since the duty cycle is determined by a single intersection between the reference and the carrier. With a triangular (double-edge) carrier, two crossings occur per period, creating two distinct opportunities to update the duty cycle, as shown in Fig. 5.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"304\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/triangular_vs_sawtooth-2-1024x304.png\" alt=\"PMW carrier, triangular vs sawtooth update instant\" class=\"wp-image-42621\" style=\"width:780px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/triangular_vs_sawtooth-2-1024x304.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/triangular_vs_sawtooth-2-300x89.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/triangular_vs_sawtooth-2-768x228.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/triangular_vs_sawtooth-2-1536x455.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/triangular_vs_sawtooth-2-2048x607.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Figure 5 : PWM carriers and possible duty cycle update instant<\/figcaption><\/figure>\n<\/div>\n\n\n<p>Therefore, two fundamental timing configurations stem from these situations:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"#Single-rate-update\" type=\"internal\" id=\"#Single-rate-update\">Single rate update<\/a>, in which case the control task is executed <strong>once<\/strong> per PWM period, and duty cycles are updated once per PWM period.<\/li>\n\n\n\n<li><a href=\"#Double-rate-update\" type=\"internal\" id=\"#Double-rate-update\">Double rate update<\/a>, in which case the control task is executed <strong>twice<\/strong> per PWM period, and duty cycles are updated twice per PWM period.<\/li>\n<\/ul>\n\n\n\n<p>With the double-rate update configuration, the control performance is enhanced by doubling the execution frequency (\\(F_{CPU}\\)) relative to the PWM switching frequency (\\(F_{SW}\\)). By executing the control task twice per carrier period, the system achieves a higher effective sampling rate and more frequent duty cycle updates. This approach allows for a higher closed-loop bandwidth at a given switching frequency, improving the overall dynamic response without increasing switching losses.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"Single-rate-update\"><span class=\"ez-toc-section\" id=\"Single-rate-update\"><\/span><strong>Single rate update<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Single rate update is the simplest timing configuration and remains the most widely used, as it covers a broad range of practical applications.<\/p>\n\n\n\n<p>In a single rate configuration, ADC sampling, CPU control execution, and PWM duty cycle updating all occur at the same fundamental frequency (which is also the switching frequency). Consequently, only CLK0 is required, and it serves as the common time base. This configuration is represented in Fig. 6.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"2560\" height=\"1549\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU-7-scaled.png\" alt=\"single rate update timing configuration using imperix controllers\" class=\"wp-image-42649\" style=\"aspect-ratio:1.7335784076617975;object-fit:contain;width:478px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU-7-scaled.png 2560w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU-7-300x182.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU-7-1024x620.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU-7-768x465.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU-7-1536x929.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/SRU-7-2048x1239.png 2048w\" sizes=\"auto, (max-width: 2560px) 100vw, 2560px\" \/><figcaption class=\"wp-element-caption\">Figure 6 : Single rate update timing configuration<\/figcaption><\/figure>\n<\/div>\n\n\n<p>The remaining degree of freedom is the sampling phase, which must be selected according to the chosen sampling method (e.g., synchronous sampling, synchronous averaging), see <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics\">sampling techniques<\/a>. When relevant, the sampling phase needs to be adjusted to account for analog front-end delays. The practical selection of this sampling phase is discussed below.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Sampling phase configuration<\/h4>\n\n\n\n<p>On imperix controllers, configuring CLK0 (the sampling frequency) is only the first step. The sampling instant must also be defined by selecting a proper phase within the CLK0 period.<\/p>\n\n\n\n<p>This phase is configured in the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\"><strong>CONFIG<\/strong><\/a> block and is implemented by generating a dedicated sampling clock, SCLK, derived from CLK0. SCLK has the same frequency as CLK0, but with a constant phase shift. This shift sets the sampling instant within the PWM period and, immediately after the ADC acquisition delay, when the CPU control cycle starts. This sequence is shown in Fig. 7.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"24796\" height=\"10501\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/timing_cockpit_1.png\" alt=\"Sampling phase setting on imperix controller\" class=\"wp-image-41811\"\/><figcaption class=\"wp-element-caption\">Figure 7 : Sampling phase configuration on imperix controller<\/figcaption><\/figure>\n\n\n\n<p>On most applications, the required phase value depends largely on the sampling method.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>When <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics#Synchronous-averaging\">synchronous averaging<\/a> is used, the exact sampling instant within the PWM period is not critical because the measurement corresponds to a periodic average over a full switching period. In this scenario, the phase is typically adjusted to <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics#SyncAvg-optimal\" type=\"link\" id=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics#SyncAvg-optimal\">minimize the total control loop delay.<\/a><\/li>\n\n\n\n<li>When <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics#2-Synchronous-sampling\">synchronous sampling<\/a> is used, the sampling instant must be placed at a point that yields a representative ripple-averaged value (for example if a current is measured). This generally leads to two phase options, 0 or 0.5, which often have to be adjusted to compensate for the propagation delays inherent in the analog measurement chain, such as those resulting from <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics#sensor-bandwidth\">low sensor bandwidth<\/a>.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The sampling phase selection (0 or 0.5) is typically determined by the CPU execution time. A phase of 0.5 is generally preferred to minimize control delay, provided the CPU task completes within half a switching period. Alternatively, a phase of 0 is adopted for intensive computations to allow a full switching period for CPU execution.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"Double-rate-update\"><span class=\"ez-toc-section\" id=\"Double-rate-update\"><\/span><strong>Double rate update<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>In a double rate update control scheme on imperix controllers, ADC sampling and CPU execution remain tied to CLK0, while the PWM block(s) use a separate time base, typically CLK1 (but can also be CLK2 or CLK3). In order to obtain two duty cycles update opportunities within one PWM period, the PWM time base has to be set to \\(F_{\\text{CLK1}} = 0.5\\cdot F_{\\text{CLK0}}\\). This configuration is illustrated in Fig. 8.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"2560\" height=\"1762\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU-4-scaled.png\" alt=\"double rate update timing on imperix controllers\" class=\"wp-image-42650\" style=\"width:500px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU-4-scaled.png 2560w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU-4-300x206.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU-4-1024x705.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU-4-768x528.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU-4-1536x1057.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU-4-2048x1409.png 2048w\" sizes=\"auto, (max-width: 2560px) 100vw, 2560px\" \/><figcaption class=\"wp-element-caption\">Figure 8 : Double rate update timing configuration on imperix controllers<\/figcaption><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">Double rate update requires a double-edge (<strong>triangular<\/strong>) carrier as single-edge carriers (sawtooth) offer only one update instant per PWM period.<\/div>\n\n\n\n<p>As with single-rate configurations, the optimal sampling phase in double-rate update mode depends on the chosen acquisition technique :<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>When <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics#Synchronous-averaging\">synchronous averaging<\/a> is used, the acquisition must be configured to average over two periods of CLK0 (in the ADC block). Since CLK0 runs at twice the switching frequency in this configuration, this setting ensures that the average is calculated over one full PWM period.<\/li>\n\n\n\n<li>When <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics#2-Synchronous-sampling\">synchronous sampling<\/a> is used, the sampling phase is typically set to 0 to align the acquisition with representative ripple-averaged values. This value may be further adjusted to compensate for delays inherent in the analog measurement chain (such as limited sensor bandwidth).<\/li>\n<\/ul>\n\n\n\n<p>From an implementation perspective, Fig. 9 summarizes the corresponding block-level structure and clock assignments for a double-rate update closed-loop buck setup. Reference Simulink and PLECS models implementing this configuration are provided below and can be used as a starting point for application-specific designs.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"450\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_simulink-1-1024x450.png\" alt=\"double rate update using simulink and imperix blockset\" class=\"wp-image-42654\" style=\"width:780px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_simulink-1-1024x450.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_simulink-1-300x132.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_simulink-1-768x338.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_simulink-1-1536x675.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/DRU_simulink-1-2048x901.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Figure 9: Double rate update configuration using Simulink<\/figcaption><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p class=\"has-text-align-center\"><strong>Simulink model<\/strong><\/p>\n\n\n\n<div class=\"wp-block-file\"><a id=\"wp-block-file--media-680a0eac-2e81-4bdd-985e-f8542bb41ec3\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Double_rate_update_Simulink.zip\">PN259_Double_rate_update_Simulink<\/a><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Double_rate_update_Simulink.zip\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-680a0eac-2e81-4bdd-985e-f8542bb41ec3\">Download<\/a><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p class=\"has-text-align-center\"><strong>PLECS model<\/strong><\/p>\n\n\n\n<div class=\"wp-block-file\"><a id=\"wp-block-file--media-c4e4b737-3e33-4dc4-bdf8-56fc418c9b24\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/PN259_Double_rate_update_PLECS.plecs\">PN259_Double_rate_update_PLECS<\/a><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/PN259_Double_rate_update_PLECS.plecs\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-c4e4b737-3e33-4dc4-bdf8-56fc418c9b24\">Download<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"Advanced-timing-configurations\"><span class=\"ez-toc-section\" id=\"Advanced-timing-configurations\"><\/span><strong>Advanced timing configurations<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"postscaler\"><span class=\"ez-toc-section\" id=\"Postscaler\"><\/span>Postscaler<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Imperix controllers offer the flexibility to run the CPU at a decimated rate relative to CLK0. By adjusting the post-scaler in the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> block, the CPU execution frequency is defined as \\(F_{\\text{CPU}} = F_{\\text{CLK0}}\/Postscaler\\).<\/p>\n\n\n\n<p>While the CPU operates at this reduced rate, the sampling frequency remains synchronized with CLK0. This decoupling is particularly advantageous when controlling <a href=\"https:\/\/imperix.com\/doc\/implementation\/interleaved-buck-converter?currentThread=fast-electric-vehicle-charger-with-intermediate-energy-storage\">interleaved converters<\/a>. In such topologies, the sampling phase must be specifically shifted for each converter leg to capture the current at the ideal moment. Consequently, the sampling frequency must be \\(N\\) times faster than the CPU execution rate, where \\(N\\) represents the number of legs.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1560\" height=\"773\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/cockpit_timing_postscaler_AI-2.png\" alt=\"Postscaler configuration using imperix controllers\" class=\"wp-image-44978\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/cockpit_timing_postscaler_AI-2.png 1560w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/cockpit_timing_postscaler_AI-2-300x149.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/cockpit_timing_postscaler_AI-2-1024x507.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/cockpit_timing_postscaler_AI-2-768x381.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/cockpit_timing_postscaler_AI-2-1536x761.png 1536w\" sizes=\"auto, (max-width: 1560px) 100vw, 1560px\" \/><figcaption class=\"wp-element-caption\">Figure 10: Postscaler configuration with N = 3 and corresponding timing view in Cockpit<\/figcaption><\/figure>\n<\/div>\n\n\n<p>Figure 10 illustrates the timing view within the Cockpit interface when a postscaler of 3 is applied. In this specific configuration, the CPU executes at a rate three times slower than both CLK0 and the sampling rate (SCLK).<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Data-history\"><\/span>Data history<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Imperix controllers also offer the ability to retrieve sampling data captured between CPU interrupt interrupts through the  &#8216;data history&#8217;  feature of the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC block<\/a>. This functionality is particularly advantageous when using a postscaler, as it enables the control algorithm to access the complete set of samples acquired during the preceding decimated interval. As illustrated in Fig.11, this ensures that all intermediate data points are available for processing, regardless of whether they were captured before the current CPU task was triggered.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1560\" height=\"713\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Cockpit_timing_dataHistory-2.png\" alt=\"Postscaler configuration using imperix controllers\" class=\"wp-image-44965\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Cockpit_timing_dataHistory-2.png 1560w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Cockpit_timing_dataHistory-2-300x137.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Cockpit_timing_dataHistory-2-1024x468.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Cockpit_timing_dataHistory-2-768x351.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/Cockpit_timing_dataHistory-2-1536x702.png 1536w\" sizes=\"auto, (max-width: 1560px) 100vw, 1560px\" \/><figcaption class=\"wp-element-caption\">Figure 11: ADC history configuration with 3 samples<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Variable-switching-frequency\"><\/span>Variable switching frequency<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>While most converters operate at a fixed frequency, some applications require dynamic frequency adjustment for regulation. A primary example is the <a href=\"https:\/\/imperix.com\/doc\/implementation\/llc-converter-control\">LLC Resonant Converter<\/a>, where the output voltage is controlled by modulating the switching frequency.<\/p>\n\n\n\n<p>On imperix controllers, this is achieved by configuring the CLK1-3 blocks to allow for real-time frequency updates, as shown in Fig.12. See also <a href=\"https:\/\/imperix.com\/doc\/help\/variable-frequency-operation?currentThread=b-board-pro\">Variable frequency operation with imperix controllers<\/a>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"400\" height=\"93\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/image-9.png\" alt=\"\" class=\"wp-image-44841\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/image-9.png 400w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/image-9-300x70.png 300w\" sizes=\"auto, (max-width: 400px) 100vw, 400px\" \/><figcaption class=\"wp-element-caption\">Figure 12 : Variable frequency clock using Simulink<\/figcaption><\/figure>\n<\/div>\n\n\n<p>When using variable switching frequencies, the sampling frequency remains fixed and tied to CLK0. Consequently, any form of synchronous acquisition is not possible, as the sampling instants will no longer align with the varying PWM periods.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Multi-rate-execution\"><\/span>Multi-rate execution<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Both&nbsp;Simulink&nbsp;and&nbsp;PLECS&nbsp;provide the flexibility to execute specific parts of a control algorithm at a lower frequency than the main execution rate (\\(F_{\\text{CPU}}\\)).&nbsp;As this is managed via dedicated software blocks, it requires no modifications to the controller\u2019s timing configurations. This function is described in more detail in <a href=\"https:\/\/imperix.com\/doc\/help\/multi-rate-control-with-acg-sdk-on-simulink?currentThread=going-further-with-acg-sdk\">PN145 &#8211; Multi-rate control with Simulink<\/a> and <a href=\"https:\/\/imperix.com\/doc\/help\/multi-rate-control-on-plecs-acg-sdk?currentThread=going-further-with-acg-sdk\">PN155 &#8211; Multi-rate control with PLECS<\/a>.<\/p>\n\n\n\n<p>This feature may be useful for&nbsp;cascaded control&nbsp;strategies, where high-level outer loops, such as voltage or motor speed regulation, can run at a lower rate, while the inner loops continue to operate at the main execution  rate for better dynamic performance. Example of multi-rate execution can be found in <a href=\"https:\/\/imperix.com\/doc\/implementation\/motor-speed-control?currentThread=electric-car-motor-control\" type=\"link\" id=\"https:\/\/imperix.com\/doc\/implementation\/motor-speed-control?currentThread=electric-car-motor-control\">Motor speed control<\/a> or in <a href=\"https:\/\/imperix.com\/doc\/implementation\/maximum-power-point-tracking-mppt\">MPPT algorithms<\/a>.<\/p>\n\n\n\n<div style=\"height:100px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Related-topics\"><\/span>Related topics<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics\">PN258 &#8211; Sampling techniques for power electronics<\/a> for the various sampling patterns and associated delays.<br><a href=\"https:\/\/imperix.com\/doc\/help\/analog-i-o-configuration-for-imperix-controllers\">PN108 &#8211; Analog I\/O configuration for imperix controllers<\/a> explains how to configure (via software) the various sampling schemes<br><a href=\"https:\/\/imperix.com\/doc\/help\/simulation-essentials-simulink?currentThread=getting-started-with-acg-sdk\">PN135 &#8211; Simulation essentials with Simulink<\/a> explains how to use and configure the ACG SDK blocks (for Simulink)<br><a href=\"https:\/\/imperix.com\/doc\/help\/simulation-essentials-plecs?currentThread=getting-started-with-acg-sdk\">PN137 &#8211; Simulation essentials with PLECS<\/a> explains how to use and configure the ACG SDK blocks (for PLECS)<br><a href=\"https:\/\/imperix.com\/doc\/help\/variable-frequency-operation?currentThread=b-board-pro\">PN121 &#8211; Variable frequency operation with imperix controllers<\/a> describes the variable switching frequency configuration.<br><a href=\"https:\/\/imperix.com\/technology\/low-latency-communication\/\">RealSync technology<\/a> explains how synchronisation between controllers is achieved.<\/p>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This article details the underlying clock architecture and timing configurations of imperix controllers, focusing on the four internal time bases (CLK0\u2013CLK3) that govern ADC sampling,&#8230;<\/p>\n","protected":false},"author":22,"featured_media":43494,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[],"software-environments":[105,103,104],"provided-results":[],"related-products":[50,32,166],"guidedreadings":[],"tutorials":[],"user-manuals":[],"coauthors":[98],"class_list":["post-40107","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","software-environments-c-plus-plus","software-environments-matlab","software-environments-plecs","related-products-acg-sdk","related-products-b-box-rcp","related-products-b-box-rcp-3-0"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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