{"id":40116,"date":"2026-01-21T08:25:59","date_gmt":"2026-01-21T08:25:59","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=40116"},"modified":"2026-04-16T09:16:50","modified_gmt":"2026-04-16T09:16:50","slug":"retrieving-adc-measurements-from-the-fpga","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga","title":{"rendered":"Retrieving ADC measurements from the FPGA"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#Data-acquisition-architecture\" >Data acquisition architecture<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#Accessing-ADC-samples-from-the-FPGA-sandbox\" >Accessing ADC samples from the FPGA sandbox<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#ADC-interface\" >ADC interface<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#ADC-FLOAT-interface-B-Box-4-only\" >ADC_FLOAT interface (B-Box 4 only)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#AXI4-Stream-interface\" >AXI4-Stream interface<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#Example\" >Example<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#Gain-computation\" >Gain computation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#Step-by-step-FPGA-implementation\" >Step-by-step FPGA implementation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#CPU-model\" >CPU model<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#Experimental-validation\" >Experimental validation<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\/#Going-further\" >Going further<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>Imperix provides direct access to ADC measurements within the FPGA which allows for reduced delay between the sampling and the processing, but also helps supporting higher sampling frequencies.<\/p>\n\n\n\n<p>In imperix devices, the ADC measurements are performed by the data acquisition stage, which is shared by both the CPU and FPGA control paths. From the sandbox, the FPGA development environment for imperix controllers, users have direct access to the ADC measurements from the acquisition module.<\/p>\n\n\n\n<p>After a brief introduction to the data acquisition architecture, this page explains how to access the ADC measurements from the sandbox as registers or as AXI4-Stream interfaces. A practical example finally illustrates how to retrieve ADC samples from the sandbox, compute and apply the appropriate scaling gain to convert the raw data into physical quantities and apply it.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Note on FPGA development for imperix controllers<\/strong><br>Customizing the FPGA firmware involves instantiating the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">imperix firmware IP<\/a> within Xilinx Vivado to edit the surrounding programmable logic, known as the sandbox. For step-by-step instructions on creating the required FPGA sandbox template, refer to the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development?currentThread=getting-started-with-fpga-programming\">getting started<\/a>\u00a0guide.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"acquisition-architecture\"><span class=\"ez-toc-section\" id=\"Data-acquisition-architecture\"><\/span>Data acquisition architecture<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The general architecture of imperix controllers is documented in the imperix IP <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">product guide<\/a>. Below is a detailed view of the <strong>data acquisition module<\/strong>, which pilots the ADC chips and make the analog input measurement available to the user-programmable FPGA area via the following interfaces:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>ADC <\/strong>interface, which returns raw 16-bit measurements;<\/li>\n\n\n\n<li><strong>ADC_FLOAT <\/strong>interface (B-Box 4 only), which returns the physical (post-rescaling) values in a 32-bit floating-point format.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1971\" height=\"837\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_data_acquisition_architecture.png\" alt=\"\" class=\"wp-image-44196\" style=\"aspect-ratio:2.354084875677697;width:571px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_data_acquisition_architecture.png 1971w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_data_acquisition_architecture-300x127.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_data_acquisition_architecture-1024x435.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_data_acquisition_architecture-768x326.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_data_acquisition_architecture-1536x652.png 1536w\" sizes=\"auto, (max-width: 1971px) 100vw, 1971px\" \/><figcaption class=\"wp-element-caption\">Architecture of the data acquisition module<\/figcaption><\/figure>\n<\/div>\n\n\n<p>The data acquisition module is composed of the following stages:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>ADC driver<\/strong> retrieves measurements from the ADC chip.<\/li>\n\n\n\n<li>The <strong>filter<\/strong> implements the <em>synchronous sampling or averaging<\/em> (all devices), or <em>low-pass filter<\/em> (B-Box 4 only), which can be enabled from the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC<\/a> block. The filtering techniques are detailed in <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics?currentThread=b-board-pro\">PN158<\/a>.<\/li>\n\n\n\n<li>The <strong>rescaling<\/strong> module (B-Box 4 only) converts the raw ADC data into physical values using the sensitivity and offset values specified in the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC<\/a> block. On other devices, this conversion is performed within the CPU.<\/li>\n\n\n\n<li>The <strong>history<\/strong> module allows to retrieve older samples from the ADC block, which is used typically when the CPU interrupt frequency is set to be slower than the FPGA <em>sampling frequency<\/em> (SCLK) using the <em>postscaler<\/em>.<br>This scenario is further documented in the <em>Handling different execution rates<\/em> of <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">PN116<\/a>.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Accessing-ADC-samples-from-the-FPGA-sandbox\"><\/span>Accessing ADC samples from the FPGA sandbox<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>In the FPGA sandbox, ADC measurements can be accessed via two interfaces provided by the imperix firmware IP:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>ADC<\/strong> (all devices) provides data as 16-bit signed integer.<\/li>\n\n\n\n<li><strong>ADC_FLOAT <\/strong>(B-Box 4 only), provides data as 32-bit floating point (post rescaling).<\/li>\n<\/ul>\n\n\n\n<p>The <strong>AXI4-Stream interface<\/strong> provided in the sandbox template can be used to retrieve the ADC samples as AXI4-Stream interfaces.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"adc-interface\"><span class=\"ez-toc-section\" id=\"ADC-interface\"><\/span>ADC interface<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"636\" height=\"864\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_interface.png\" alt=\"\" class=\"wp-image-44003\" style=\"width:400px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_interface.png 636w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_interface-221x300.png 221w\" sizes=\"auto, (max-width: 636px) 100vw, 636px\" \/><\/figure>\n<\/div>\n\n\n<p>The <strong>ADC <\/strong>interface of the imperix firmware IP returns the raw ADC measurements in <strong>16-bit signed integer<\/strong> format, as received by the ADC. The raw values therefore follow:<\/p>\n\n\n\n<p>\\[ \\text{raw ADC value} = \\text{controller input voltage} \\;\\times\\;  \\frac{2^{15}}{\\text{full scale}} \\]<\/p>\n\n\n\n<p>The full-scale voltage for each controller is indicated in the following table:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td class=\"has-text-align-center\" data-align=\"center\"><strong>B-Box 4<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\"><strong>B-Box RCP 3.0<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\"><strong>B-Box Micro, B-Board PRO<\/strong><\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">\\(10\\text{V}\\)<\/td><td class=\"has-text-align-center\" data-align=\"center\">\\(10\\text{V} \\,\/\\; \\text{programmable gain}\\)<\/td><td class=\"has-text-align-center\" data-align=\"center\">\\(5\\text{V}\\)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>The <code>adc_done_pulse<\/code> signal indicates that the interface registers have been updated with new samples, effectively acting as a data valid strobe.<\/p>\n\n\n\n<p>The <code>adc_done_cpu_pulse<\/code> is a decimated version of the <code>adc_done_pulse<\/code>. It indicates when the samples are also available to the user application running on the CPU. The relationship between these two pulses is therefore defined by the postscaler ratio.<\/p>\n\n\n\n<p>The acquisition delay is defined as the time elapsed from the sampling pulse (<code>sampling_pulse<\/code>) to the corresponding data being available at the ADC interface (<code>adc_done_pulse<\/code>) when no filter is enabled (synchronous sampling). It is specified for each imperix controller in the table below.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th class=\"has-text-align-left\" data-align=\"left\">&nbsp;<\/th><th class=\"has-text-align-center\" data-align=\"center\"><strong>B-Box 4<\/strong><\/th><th class=\"has-text-align-center\" data-align=\"center\"><strong>B-Box <strong>RCP 3.0<\/strong><\/strong><\/th><th class=\"has-text-align-center\" data-align=\"center\"><strong>B-Box Micro, B-Board PRO, TPI8032<\/strong><\/th><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Acquisition delay<\/td><td class=\"has-text-align-center\" data-align=\"center\">200 ns \/ 368 ns*<\/td><td class=\"has-text-align-center\" data-align=\"center\">2 \u03bcs<\/td><td class=\"has-text-align-center\" data-align=\"center\">500 ns<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>* When channels A12-A23 are used.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The filtering technique used in the filter will induce a group delay.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"adc-float-interface\"><span class=\"ez-toc-section\" id=\"ADC-FLOAT-interface-B-Box-4-only\"><\/span>ADC_FLOAT interface (B-Box 4 only)<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"676\" height=\"866\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_float_interface.png\" alt=\"\" class=\"wp-image-44201\" style=\"width:400px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_float_interface.png 676w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_float_interface-234x300.png 234w\" sizes=\"auto, (max-width: 676px) 100vw, 676px\" \/><\/figure>\n<\/div>\n\n\n<p>In the B-Box 4, the <strong>ADC_FLOAT <\/strong>interface provides access to the rescaled data as 32-bit registers in a <strong>floating-point <\/strong>format.<\/p>\n\n\n\n<p>As already mentioned in the architecture description above, the rescaling offset and gain must be specified in the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC<\/a> block(s) in the user application.<\/p>\n\n\n\n<p>Since rescaling induces an additional delay of 192 ns, the <code>adc_done_float_pulse<\/code> and <code>adc_done_cpu_float_pulse<\/code> valid pulses are provided. They are delayed versions of the <code>adc_done_pulse<\/code> and <code>adc_done_cpu_pulse<\/code> described in the ADC interface section above.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"axi4-stream-interface\"><span class=\"ez-toc-section\" id=\"AXI4-Stream-interface\"><\/span>AXI4-Stream interface<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"855\" height=\"790\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_axis_interface.png\" alt=\"\" class=\"wp-image-44012\" style=\"aspect-ratio:1.08229833684301;width:565px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_axis_interface.png 855w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_axis_interface-300x277.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_axis_interface-768x710.png 768w\" sizes=\"auto, (max-width: 855px) 100vw, 855px\" \/><\/figure>\n<\/div>\n\n\n<p>The <strong>AXI4-Stream interface<\/strong> module included in the sandbox template exposes the ADC measurements as AXI4-Stream interfaces. This enables the use of Xilinx AXI4-Stream IPs in the subsequent custom logic and facilitates the implementation of control algorithms, as illustrated in the example below.<\/p>\n\n\n\n<p>The\u00a0<em>Master AXI4-Stream<\/em>\u00a0interfaces\u00a0<strong>M_AXIS_ADC_00<\/strong>\u00a0to\u00a0<strong>M_AXIS_ADC_15\u00a0<\/strong>correspond to the 16 analog inputs of the imperix device. They return the raw\u00a0<strong>16-bit signed integer<\/strong>\u00a0in the same format as the ADC interface.<\/p>\n\n\n\n<p>The <strong>CPU2FPGA<\/strong> and <strong>FPGA2CPU <\/strong>interfaces are documented in <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga?currentThread=getting-started-with-fpga-programming\">PN128<\/a> (Exchanging data between the CPU and the FPGA).<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Example\"><\/span>Example<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This example demonstrates how to access and process ADC measurements within the FPGA sandbox using exclusively IP provided by Vivado. Specifically, using a <a href=\"https:\/\/imperix.com\/products\/control\/rcp-controller\/\">B-Box 4<\/a> controller and a <a href=\"https:\/\/imperix.com\/products\/power\/voltage-sensors\/#vsr-1000-iso\">VSR-1000-ISO<\/a> voltage sensor, it illustrates how to:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Retrieve ADC measurements from the imperix firmware IP via the provided <strong>AXI4-Stream interface<\/strong>.<\/li>\n\n\n\n<li>Convert the data from 16-bit signed integer to a 32-bit floating-point format using Xilinx <strong>floating-point IP<\/strong> configured for <strong>fixed-to-float<\/strong> operation.<\/li>\n\n\n\n<li>Multiply by the gain factor to convert raw data into their corresponding physical quantities using another <strong>floating-point IP<\/strong> configured for <strong>multiply <\/strong>operation.<\/li>\n\n\n\n<li>Send the result to the CPU for monitoring.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">This example is provided for educational purposes. Rather than manually recomputing and applying the gain, B-Box 4 users can directly use results provided by the <strong>ADC_FLOAT<\/strong> interfaces.<\/div>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"403\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-20-1024x403.png\" alt=\"\" class=\"wp-image-45075\" style=\"aspect-ratio:2.5410150338008273;width:694px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-20-1024x403.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-20-300x118.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-20-768x302.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-20.png 1195w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h3 class=\"wp-block-heading\" id=\"gain-computation\"><span class=\"ez-toc-section\" id=\"Gain-computation\"><\/span>Gain computation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>As explained in the <a href=\"#adc-interface\">ADC interface<\/a> section, raw data follow:<\/p>\n\n\n\n<p>\\[ \\text{raw ADC value} = \\text{controller input voltage} \\;\\times\\; \\frac{2^{15}}{\\text{full scale}} \\]<\/p>\n\n\n\n<p>where the full scale is 10V for the B-Box 4. With a sensor sensitivity of 5mV\/V (see <a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/VSR-1000-ISO.pdf\">datasheet<\/a>), the gain factor to be applied to the raw data to retrieve the physical voltage on the sensor&#8217;s terminals is:<\/p>\n\n\n\n<p>\\[ \\text{gain} = \\frac{1}{\\text{sensor sensitivity}} \\;\\times\\;  \\frac{\\text{full scale}}{2^{15}} = \\frac{1}{0.005} \\;\\times\\; \\frac{10}{2^{15}} = 61.04\\cdot 10^{-3} \\left[\\frac{\\text{V}}{\\text{bit}}\\right] \\]<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Step-by-step-FPGA-implementation\"><\/span>Step-by-step FPGA implementation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>This section describes how to build the following FPGA design step by step.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"2560\" height=\"1224\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_design-scaled.png\" alt=\"\" class=\"wp-image-44253\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_design-scaled.png 2560w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_design-300x143.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_design-1024x490.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_design-768x367.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_design-1536x734.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_design-2048x979.png 2048w\" sizes=\"auto, (max-width: 2560px) 100vw, 2560px\" \/><\/figure>\n<\/div>\n\n\n<p><strong>Start from template<\/strong><\/p>\n\n\n\n<p>This example is based on the sandbox template provided in the imperix source files. Follow the procedure detailed in the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development?currentThread=getting-started-with-fpga-programming\">Getting started<\/a> page to get ready.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"754\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_template-1024x754.png\" alt=\"\" class=\"wp-image-44231\" style=\"aspect-ratio:1.3581039178148677;width:555px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_template-1024x754.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_template-300x221.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_template-768x566.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_template.png 1409w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p><strong>Add the int16-to-float converter<\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"952\" height=\"637\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_0.png\" alt=\"\" class=\"wp-image-44234\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_0.png 952w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_0-300x201.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_0-768x514.png 768w\" sizes=\"auto, (max-width: 952px) 100vw, 952px\" \/><\/figure>\n<\/div>\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"952\" height=\"637\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_1.png\" alt=\"\" class=\"wp-image-44235\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_1.png 952w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_1-300x201.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_converter_1-768x514.png 768w\" sizes=\"auto, (max-width: 952px) 100vw, 952px\" \/><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li>Right-click somewhere in the block design, select <strong>Add IP<\/strong> and search for <strong>Floating-point<\/strong>. Press Enter.<\/li>\n\n\n\n<li>In the Block Properties panel, rename the block to <strong>int16_to_float<\/strong>.<\/li>\n\n\n\n<li>Double-click on the IP to open the configuration panel. In the <strong>Operation Selection<\/strong> tab, select the <strong>Fixed-to-float<\/strong> operation. In the <strong>Precision of inputs<\/strong> tab, select <strong>Manual<\/strong> and <strong>Custom<\/strong> for the precision type. Then, select <strong>Manual<\/strong> for the integer width and set it to <strong>16<\/strong>. Other parameters can be let in their default configuration.<\/li>\n<\/ul>\n\n\n\n<p><strong>Add the multiplier<\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"793\" height=\"592\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_multiplier.png\" alt=\"\" class=\"wp-image-44236\" style=\"aspect-ratio:1.339538842052073\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_multiplier.png 793w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_multiplier-300x224.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_multiplier-768x573.png 768w\" sizes=\"auto, (max-width: 793px) 100vw, 793px\" \/><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li>Right-click somewhere in the block design, select <strong>Add IP<\/strong> and search for <strong>Floating-point<\/strong>. Press Enter.<\/li>\n\n\n\n<li>In the Block Properties panel, rename the block to <strong>multiplier<\/strong>.<\/li>\n\n\n\n<li>Double-click on the IP to open the configuration panel. In the <strong>Operation Selection<\/strong> tab, select <strong>Multiply<\/strong> for the operation. Other parameters can be let in their default configuration.<\/li>\n<\/ul>\n\n\n\n<p><strong>Add the two constants<\/strong><\/p>\n\n\n\n<p>Because the constant block does not accept decimal values, the gain computed earlier (<strong>0.06104<\/strong>) must be converted to its hexadecimal representation (<strong>0x3D7A0514<\/strong>). This can be easily achieved using free conversion tools, such as <a href=\"https:\/\/www.h-schmidt.net\/FloatConverter\/IEEE754.html\">this website<\/a>.<\/p>\n\n\n\n<p>Moreover, the gain constant output is a static register, while the multiplier expects both operands to be provided as AXI4-Stream interfaces. A constant &#8216;1&#8217; is therefore fed on <strong>tvalid<\/strong>, along with the gain on <strong>tdata<\/strong>, in the second input interface of the multiplier. This effectively transforms the static value into an (always-valid) AXI4-Stream.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"656\" height=\"362\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_constants_0.png\" alt=\"\" class=\"wp-image-44237\" style=\"aspect-ratio:1.812274368231047;width:382px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_constants_0.png 656w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_constants_0-300x166.png 300w\" sizes=\"auto, (max-width: 656px) 100vw, 656px\" \/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"219\" height=\"321\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_constants_1.png\" alt=\"\" class=\"wp-image-44238\" style=\"aspect-ratio:0.6822951551685644;width:147px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_constants_1.png 219w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_constants_1-205x300.png 205w\" sizes=\"auto, (max-width: 219px) 100vw, 219px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Right-click somewhere in the block design, select <strong>Add IP<\/strong> and search for <strong>Constant<\/strong>. Press Enter.<\/li>\n\n\n\n<li>Rename the block to <strong>gain<\/strong>. In the IP&#8217;s configuration panel, set the width to <strong>32<\/strong> and the value to <strong>0x3D7A0514<\/strong>. This is the hexadecimal representation of the gain computed in the previous section, i.e., 0.06104.<\/li>\n\n\n\n<li>Add another <strong>Constant<\/strong> IP and rename it to <strong>tvalid<\/strong>. The default configuration with a width and value of 1 does not need to be changed.<\/li>\n<\/ul>\n\n\n\n<p><strong>Apply connections<\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"2233\" height=\"1150\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_connections.png\" alt=\"\" class=\"wp-image-44239\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_connections.png 2233w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_connections-300x155.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_connections-1024x527.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_connections-768x396.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_connections-1536x791.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_vivado_procedure_connections-2048x1055.png 2048w\" sizes=\"auto, (max-width: 2233px) 100vw, 2233px\" \/><\/figure>\n<\/div>\n\n\n<p>The design can be finalized by applying the following connections:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>ix_axis_interface\/M_AXIS_ADC_00<\/strong> interface to the <strong>int16_to_float\/S_AXIS_A<\/strong> interface<\/li>\n\n\n\n<li><strong>int16_to_float\/M_AXIS_RESULT<\/strong> interface to <strong>multiplier\/S_AXIS_A<\/strong> interface<\/li>\n\n\n\n<li><strong>gain\/dout<\/strong> signal to the <strong>s_axis_b_tdata<\/strong> signal of the <strong>multiplier\/S_AXIS_B<\/strong> interface<\/li>\n\n\n\n<li><strong>tvalid\/dout<\/strong> signal to the <strong>s_axis_b_tvalid<\/strong> signal of the <strong>multiplier\/S_AXIS_B<\/strong> interface<\/li>\n\n\n\n<li><strong>multiplier\/M_AXIS_RESULT<\/strong> interface to the <strong>ix_axis_interface\/S_AXIS_FPGA2CPU_00<\/strong> interface<\/li>\n\n\n\n<li>the two clocks signals (<strong>int16_to_float\/aclk<\/strong> and <strong>multiplier\/aclk<\/strong>) to the <strong>IXIP\/clk_250_mhz<\/strong> signal<\/li>\n<\/ul>\n\n\n\n<p><strong>Save, build and load the design<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Save the design and click on <strong>Generate Bitstream<\/strong> in the sidebar on the left.<\/li>\n\n\n\n<li>Load the bitstream onto the controller via Cockpit.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"CPU-model\"><\/span>CPU model<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The CPU model is provided below in Simulink and PLECS:<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_example.slx\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>pn126_sandbox_adc_example.slx<\/strong><\/a><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_sandbox_adc_example.plecs\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>pn126_sandbox_adc_example.plecs<\/strong><\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"619\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_simulink_model-1024x619.png\" alt=\"\" class=\"wp-image-44062\" style=\"aspect-ratio:1.6543388294028771;width:455px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_simulink_model-1024x619.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_simulink_model-300x181.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_simulink_model-768x464.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_simulink_model.png 1528w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"728\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_plecs_model-1024x728.png\" alt=\"\" class=\"wp-image-44092\" style=\"aspect-ratio:1.4066549912434325;width:321px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_plecs_model-1024x728.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_plecs_model-300x213.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_plecs_model-768x546.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_plecs_model-1536x1092.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_plecs_model.png 1566w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>The user application contains:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>CONFIG<\/strong> block where the sampling clock (SCLK) frequency, which is equal to the CLK0 frequency, is set to 20 kHz. The postscaler ratio kept to 1, meaning that the CPU and FPGA receive the ADC samples at the same rate.<\/li>\n\n\n\n<li>An <strong>ADC <\/strong>block, configured on channel 0 with a VSR-1000-ISO sensor. <mark style=\"background-color:#ffffff\" class=\"has-inline-color\">Synchronous averaging is activated.<\/mark><\/li>\n\n\n\n<li>An <strong>SBI<\/strong> block to access the result computed in the FPGA from the CPU and monitor it in Cockpit. The <strong>sbi2single<\/strong> function converts the two 16-bit SBIO addresses into one 32-bit floating-point variable. More information about the CPU-FPGA communication is available in <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga?currentThread=getting-started-with-fpga-programming\">Exchanging data between the CPU and the FPGA<\/a>.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Experimental-validation\"><\/span>Experimental validation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>To validate this example, a sinusoidal voltage source has been connected to the voltage sensor terminals. The sensor output is connected to the ADC channel 0 (A0) of the B-Box.<\/p>\n\n\n\n<p>Once the bitstream is loaded (the loading procedure is detailed <a href=\"https:\/\/imperix.com\/doc\/help\/cockpit-user-guide?currentThread=b-box-4#h-how-to-load-a-custom-fpga-bitstream\">here<\/a>), the user application can be compiled (<strong>Ctrl+B<\/strong> in Simulink, <strong>Ctrl+Alt+B<\/strong> then <strong>Build<\/strong> in PLECS). Following compilation, Cockpit is automatically launched. The project can be linked to the controller and scopes can be added to the graphical interface to monitor the signals of interest. The Cockpit interface should appear as follows:<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1022\" height=\"578\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_cockpit.png\" alt=\"\" class=\"wp-image-44075\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_cockpit.png 1022w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_cockpit-300x170.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn126_cockpit-768x434.png 768w\" sizes=\"auto, (max-width: 1022px) 100vw, 1022px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Going-further\"><\/span>Going further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Using the <strong>Floating-point IP<\/strong> provided by Xilinx is convenient for simple operations, such as multiplying by a gain as demonstrated in the example above. For more complex algorithms, however, utilizing <strong>High-Level Synthesis (HLS)<\/strong> tools greatly facilitates the development process.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">PN163<\/a> introduces <strong>AMD Xilinx Model Composer<\/strong>, a paid add-on for MATLAB and Simulink<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">PN164<\/a> introduces <strong>AMD Xilinx Vitis HLS<\/strong>, the free C++ based alternative<br><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Imperix provides direct access to ADC measurements within the FPGA which allows for reduced delay between the sampling and the processing, but also helps supporting&#8230;<\/p>\n","protected":false},"author":4,"featured_media":2995,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[141],"coauthors":[70,82],"class_list":["post-40116","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","user-manuals-getting-started-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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