{"id":40118,"date":"2026-01-21T08:26:11","date_gmt":"2026-01-21T08:26:11","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=40118"},"modified":"2026-04-16T12:47:19","modified_gmt":"2026-04-16T12:47:19","slug":"driving-pwm-outputs-from-the-fpga","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga","title":{"rendered":"Driving PWM outputs from the FPGA"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#The-PWM-chain\" >The PWM chain<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#The-CLOCK-interface\" >The CLOCK interface<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#Provided-carrier-based-modulator\" >Provided carrier-based modulator<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#Pinout\" >Pinout<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#AXI4-Stream-carrier-based-modulator\" >AXI4-Stream carrier-based modulator<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#Example\" >Example<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#Experimental-validation\" >Experimental validation<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#Going-further\" >Going further<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#Debugging-an-FPGA-module\" >Debugging an FPGA module<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\/#Using-automated-code-generation-to-avoid-writing-VHDL\" >Using automated code generation to avoid writing VHDL<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p>Beyond the built-in modulators accessible from the user application, the imperix sandbox enables PWM generation directly within the FPGA, allowing for the implementation of custom modulation strategies.<\/p>\n\n\n\n<p>Within the sandbox, this process is simplified by the availability of the built-in clocks (CLK0, CLK1, CLK2, CLK3), which are configured via the user application and shared across the entire system. Utilizing these shared clocks ensures perfect synchronization between the FPGA modulator, CPU sampling, and other system components.<\/p>\n\n\n\n<p>For convenience, the sandbox source files include a ready-to-use carrier-based modulator written in VHDL. The example at the end of this page details the integration of this modulator into a functional FPGA design.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Note on FPGA development for imperix controllers<\/strong><br>Customizing the FPGA firmware involves instantiating the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">imperix firmware IP<\/a> within Xilinx Vivado to edit the surrounding programmable logic, known as the sandbox. For step-by-step instructions on creating the required FPGA sandbox template, refer to the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development?currentThread=getting-started-with-fpga-programming\">getting started<\/a>\u00a0guide.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"The-PWM-chain\"><\/span>The PWM chain<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>In the FPGA, the PWM signals are be driven via the <code>sb_pwm<\/code> port of the imperix firmware IP.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"610\" height=\"770\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_firmware_interface.png\" alt=\"\" class=\"wp-image-44951\" style=\"width:412px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_firmware_interface.png 610w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_firmware_interface-238x300.png 238w\" sizes=\"auto, (max-width: 610px) 100vw, 610px\" \/><\/figure>\n<\/div>\n\n\n<p>As shown below, the signals fed through the <code>sb_pwm<\/code> port of the imperix firmware IP (IXIP) are considered as an additional PWM source, equivalently to the output of all built-in modulators. This means that the dead-time generation, activation and protection mechanisms are also available when driving the PWM from the sandbox.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"616\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_overall_pwm_architecture-1024x616.png\" alt=\"\" class=\"wp-image-43582\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_overall_pwm_architecture-1024x616.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_overall_pwm_architecture-300x180.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_overall_pwm_architecture-768x462.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">Imperix\u00a0<strong>strongly discourages<\/strong>\u00a0the user from directly driving the top-level\u00a0<code>pwm<\/code>\u00a0port, as this would bypass the protection mechanism. Instead, PWM signals from the sandbox should be routed through the <code>sb_pwm<\/code> input port.<\/div>\n\n\n\n<p>To drive PWM outputs from the sandbox, the corresponding channels must be selected using an <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-pwm\">SB-PWM<\/a> block in the user application. For each selected channel, this block also indicates:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>output mode<\/strong> (usually <strong>single<\/strong> or <strong>dual<\/strong>).<\/li>\n\n\n\n<li>The <strong>dead-time<\/strong> to be applied for each channel set as dual.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p class=\"has-text-align-center\"><strong>Single mode<\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"476\" height=\"661\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_simulink_mask_a.png\" alt=\"\" class=\"wp-image-40218\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_simulink_mask_a.png 476w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_simulink_mask_a-216x300.png 216w\" sizes=\"auto, (max-width: 476px) 100vw, 476px\" \/><\/figure>\n<\/div>\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"573\" height=\"1024\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_a-573x1024.png\" alt=\"\" class=\"wp-image-40219\" style=\"aspect-ratio:0.5595782726829381;width:290px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_a-573x1024.png 573w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_a-168x300.png 168w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_a-768x1371.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_a-860x1536.png 860w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_a-1147x2048.png 1147w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_a-scaled.png 1434w\" sizes=\"auto, (max-width: 573px) 100vw, 573px\" \/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p class=\"has-text-align-center\"><strong>Dual mode<\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"476\" height=\"661\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_simulink_mask_b.png\" alt=\"\" class=\"wp-image-40220\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_simulink_mask_b.png 476w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_simulink_mask_b-216x300.png 216w\" sizes=\"auto, (max-width: 476px) 100vw, 476px\" \/><\/figure>\n<\/div>\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"573\" height=\"1024\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_b-573x1024.png\" alt=\"\" class=\"wp-image-40221\" style=\"aspect-ratio:0.5595782726829381;width:282px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_b-573x1024.png 573w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_b-168x300.png 168w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_b-768x1371.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_b-860x1536.png 860w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_b-1147x2048.png 1147w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_example_schematic_b-scaled.png 1434w\" sizes=\"auto, (max-width: 573px) 100vw, 573px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>A third output mode, called <strong>PWM + ACTIVE<\/strong>, is also available for very specific use cases. In this mode, the first lane of each channel behaves as the single mode, while the second lane indicates if the channel is active (PWM activated and enabled) or not.<\/p>\n\n\n\n<p>The following table summarizes the mapping of the channels (or lanes) for the three available output modes. <\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"2\"><strong>PWM output<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"4\"><strong>source of the PWM output<\/strong><\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\"><strong>channel<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\"><strong>pin<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\"><strong>single<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"2\"><strong>dual (PWM_H+PWM_L)<\/strong><\/td><td class=\"has-text-align-center\" data-align=\"center\"><strong>dual (PWM+ACTIVE)<\/strong><\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">CH0<\/td><td class=\"has-text-align-center\" data-align=\"center\">pwm(0)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(0)<\/td><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">dead-time(sb_pwm(0))<\/td><td class=\"has-text-align-center\" data-align=\"center\">H signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(0)<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">pmw(1)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(1)<\/td><td class=\"has-text-align-center\" data-align=\"center\">L signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">channel active signal<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">CH1<\/td><td class=\"has-text-align-center\" data-align=\"center\">pmw(2)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(2)<\/td><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">dead-time(sb_pwm(2))<\/td><td class=\"has-text-align-center\" data-align=\"center\">H signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(2)<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">pmw(3)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(3)<\/td><td class=\"has-text-align-center\" data-align=\"center\">L signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">channel active signal<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">CH2<\/td><td class=\"has-text-align-center\" data-align=\"center\">pmw(4)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(4)<\/td><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">dead-time(sb_pwm(4))<\/td><td class=\"has-text-align-center\" data-align=\"center\">H signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(4)<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">pmw(5)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(5)<\/td><td class=\"has-text-align-center\" data-align=\"center\">L signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">channel active signal<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"2\">\u2026<\/td><td class=\"has-text-align-center\" data-align=\"center\">\u2026<\/td><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"2\">\u2026<\/td><td class=\"has-text-align-center\" data-align=\"center\">\u2026<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">CH23<\/td><td class=\"has-text-align-center\" data-align=\"center\">pwm(46)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(46)<\/td><td class=\"has-text-align-center\" data-align=\"center\" rowspan=\"2\">dead-time(sb_pwm(46))<\/td><td class=\"has-text-align-center\" data-align=\"center\">H signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(46)<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">pmw(47)<\/td><td class=\"has-text-align-center\" data-align=\"center\">sb_pwm(47)<\/td><td class=\"has-text-align-center\" data-align=\"center\">L signal<\/td><td class=\"has-text-align-center\" data-align=\"center\">channel active signal<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"clock-configuration\"><span class=\"ez-toc-section\" id=\"The-CLOCK-interface\"><\/span>The CLOCK interface<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The modulators implemented in the sandbox can rely on the same built-in clocks than the other built-in modulators: <strong>CLK_0<\/strong>, <strong>1<\/strong>, <strong>2<\/strong>, <strong>3<\/strong>. These clocks are configured via the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> (CLK_0) or <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> (CLK_1, 2, 3) blocks in the user application.<\/p>\n\n\n\n<p>In the FPGA, the clocks can be accessed through the <strong>CLOCK_0<\/strong>, <strong>1<\/strong>, <strong>2<\/strong>, <strong>3<\/strong> interfaces on the imperix firmware IP (see right picture below). These interfaces can be directly connected to custom modulators in the sandbox, as shown in the <a href=\"#modulator-example\">example<\/a> below where CLK_1 is used to drive the modulator in the FPGA.<\/p>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-center is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"256\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_simulink-1024x256.png\" alt=\"\" class=\"wp-image-44488\" style=\"width:285px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_simulink-1024x256.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_simulink-300x75.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_simulink-768x192.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_simulink-1536x384.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_simulink.png 1914w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Configuration of CLOCK_0 and CLOCK_1<br>in Simulink.<\/figcaption><\/figure>\n<\/div>\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"381\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_plecs-1024x381.png\" alt=\"\" class=\"wp-image-44489\" style=\"aspect-ratio:2.6877858337981038;width:297px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_plecs-1024x381.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_plecs-300x112.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_plecs-768x286.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_plecs-1536x572.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_config_clk_blocks_plecs-2048x762.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Configuration of CLOCK_0 and CLOCK_1<br>in PLECS.<\/figcaption><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"513\" height=\"723\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_firmware_clock_interfaces.png\" alt=\"\" class=\"wp-image-43666\" style=\"aspect-ratio:0.7095588235294118;width:259px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_firmware_clock_interfaces.png 513w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_firmware_clock_interfaces-213x300.png 213w\" sizes=\"auto, (max-width: 513px) 100vw, 513px\" \/><figcaption class=\"wp-element-caption\">Access to the clocks in the sandbox.<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>Using the built-in clocks spares users from having to implement their own clock generation logic, guarantees the switching synchronization with the other internal modulators, and allows for easy frequency adjustments from the user application without the need to regenerate a new bitstream.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Each CLOCK interface is composed of four signals: <code>CLOCK_period<\/code>, <code>CLOCK_timer<\/code>, <code>CLOCK_prescaler<\/code> and <code>CLOCK_clk_en<\/code>. More information about the interface signals is available in the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">IXIP product guide<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"provided-carrier-based-modulator\"><span class=\"ez-toc-section\" id=\"Provided-carrier-based-modulator\"><\/span>Provided carrier-based modulator<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Since it is not possible to directly drive the built-in <a href=\"https:\/\/imperix.com\/doc\/software\/carrier-based-pwm\">CB-PWM<\/a> modulators from within the sandbox, it is required to instantiate a PWM modulator within the FPGA. For convenience, a carrier-based modulator written in VHDL is provided in the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox?currentThread=getting-started-with-fpga-programming\">imperix source files<\/a>. This modulator, shown below, is directly inspired from the built-in CB-PWM modulator.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"480\" height=\"244\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_modulator_module.png\" alt=\"\" class=\"wp-image-44953\" style=\"width:410px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_modulator_module.png 480w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_modulator_module-300x153.png 300w\" sizes=\"auto, (max-width: 480px) 100vw, 480px\" \/><\/figure>\n<\/div>\n\n\n<p>The modulator uses a <strong>pulse-width modulation<\/strong> based on a <strong>triangular carrier<\/strong>. The carrier is generated from the clock interface, which must be connected to one of the four CLOCK interfaces of the firmware IP in the FPGA and configured from the user code (see previous section).<\/p>\n\n\n\n<p>The duty cycle can be updated using a&nbsp;<strong>single rate<\/strong>&nbsp;or&nbsp;<strong>double rate<\/strong>. When using the&nbsp;single-rate&nbsp;update, the duty cycle value is applied when the triangular carrier reaches its minimum. With the&nbsp;double-rate&nbsp;update, the duty cycle is updated twice per period: when the carrier reaches its maximum and when it reaches its minimum.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">In summary, this FPGA PWM modulator behaves as a carrier-based PWM (<a href=\"https:\/\/imperix.com\/doc\/software\/carrier-based-pwm\">CB-PWM<\/a>) modulator that is configured with a triangular carrier, and a phase of 0.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Pinout\"><\/span>Pinout<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td><strong>Port name<\/strong><\/td><td><strong>Direction<\/strong><\/td><td><strong>Width<\/strong><\/td><td><strong>Description<\/strong><\/td><\/tr><tr><td><code>CLOCK_period<\/code><\/td><td>IN<\/td><td>16<\/td><td>Period of the clock used to generate the PWM carrier, expressed as an number of ticks (1 tick = 4 ns).<br><br>E.g. a clock set to 20 kHz result in <code>CLOCK_period = 12500 ticks<\/code>.<\/td><\/tr><tr><td><code>CLOCK_timer<\/code><\/td><td>IN<\/td><td>16<\/td><td>Counter of the clock used to generate the PWM carrier, counting from 0 to <code>CLOCK_period-1<\/code>.<br><br>The triangle carrier:<br>&#8211; is reset to 0 when <code>CLOCK_timer=0<\/code><br>&#8211; goes up while <code>CLOCK_timer &lt; CLOCK_period\/2-1<\/code>.<br>&#8211; goes down while <code>CLOCK_timer >= CLOCK_period\/2-1<\/code>.<\/td><\/tr><tr><td><code>CLOCK_prescaler<\/code><\/td><td>IN<\/td><td>16<\/td><td>Indicates the used prescaler division value for the CLOCK.<\/td><\/tr><tr><td><code>CLOCK_clk_en<\/code><\/td><td>IN<\/td><td>1<\/td><td>Clock enable signal indicating when <code>CLOCK_timer<\/code> was incremented.<br>When <code>CLOCK_prescaler > 1<\/code>,  <code>CLOCK_clk_en<\/code> is asserted once every N cycles (where N <code>= CLOCK_prescaler<\/code>)<\/td><\/tr><tr><td><code>i_nextDutyCycle<\/code><\/td><td>IN<\/td><td>16<\/td><td>Desired duty-cycle for the PWM signal, expressed as an number of <code>CLOCK_period<\/code> ticks. It ranges from <code>0<\/code> to <code>i_nextDutyCycle-1<\/code>.<\/td><\/tr><tr><td><code>i_enableDoubleRate<\/code><\/td><td>IN<\/td><td>1<\/td><td>Selection of the single update rate (0) or double update rate (1).<\/td><\/tr><tr><td><code>clk_250_mhz<\/code><\/td><td>IN<\/td><td>1<\/td><td>Main clock running at 250 MHz.<\/td><\/tr><tr><td><code>o_pwm<\/code><\/td><td>OUT<\/td><td>1<\/td><td>PWM signal generated by the modulator.<\/td><\/tr><tr><td><code>o_carrier<\/code><\/td><td>OUT<\/td><td>16<\/td><td>Access to the internal carrier used to generate the PWM signal, for monitoring or debug purposes.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"AXI4-Stream-carrier-based-modulator\"><\/span>AXI4-Stream carrier-based modulator<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>To facilitate the use of the carrier-based modulator described above, an extended version is provided called <strong>axis_cb_pwm<\/strong>. This variant accepts a <strong>32-bit floating-point duty cycle<\/strong>, ranging from 0.0 to 1.0, via an <strong>AXI4-Stream interface<\/strong>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"402\" height=\"199\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-21.png\" alt=\"\" class=\"wp-image-45081\" style=\"width:290px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-21.png 402w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-21-300x149.png 300w\" sizes=\"auto, (max-width: 402px) 100vw, 402px\" \/><\/figure>\n<\/div>\n\n\n<p>As shown below, the <strong>axis_cb_pwm<\/strong> was implemented using standard Vivado IPs and is distributed as a hierarchical Block Design. This approach is intended for educational purposes, allowing users to easily navigate and modify the underlying structure.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"299\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-27-1024x299.png\" alt=\"\" class=\"wp-image-45088\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-27-1024x299.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-27-300x88.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-27-768x224.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-27.png 1261w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>The blocks are the following:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>single_to_fix16_15<\/strong>: The 32-bit single-precision floating-point value is transformed into a 16-bit fixed-point value with an integer width of 1-bit and a fraction width of 15-bit (fix16_15). This repartition has been chosen because the duty cycle is expected to range between 0.0 and 1.0 so only 1-bit is required on the integer part.<\/li>\n\n\n\n<li><strong>clock_spy<\/strong>: serves to extract the <code>CLOCK_period<\/code> signal from the CLOCK interface.<\/li>\n\n\n\n<li><strong>multiplier<\/strong>: To obtain a value in&nbsp;<em>ticks<\/em>, the result of the previous step is multiplied by <code>CLOCK_period<\/code>. The result of the multiplication of a <strong>fix16_15 <\/strong>with a <strong>uint16 <\/strong>is a <strong>fix32_15 <\/strong>(32-bit, 17-bit integer part, and 15-bit fractional part). The clock enable (CE) input is enabled and connected to the&nbsp;<em>tvalid&nbsp;<\/em>output of the&nbsp;<em>single_to_fix16_15&nbsp;<\/em>IP output. This way, the multiplication is performed synchronously with the data coming from the AXI4-Stream.<\/li>\n\n\n\n<li><strong>slice<\/strong>: Only the 16 first bits of this result are used as the duty cycle input of the FPGA PWM modulator IP.<\/li>\n\n\n\n<li><strong>UserCbPwm<\/strong>: The carrier-based modulator provided with the FPGA sandbox template sources.<\/li>\n<\/ul>\n\n\n\n<p>A Tcl script to re-create an <strong>axis_cb_pwm<\/strong> module is provided below.<\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/axis_cb_pwm.zip\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>axis_cb_pwm.zip<\/strong><\/a><\/div>\n\n\n\n<p>The procedure to use it is as follow:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Download <strong>axis_cb_pwm.zip<\/strong> and unzip it.<\/li>\n\n\n\n<li>Copy <code><strong>axis_cb_pwm\/hdl\/clock_spy.vhd<\/strong><\/code> into <code><strong><code>&lt;path-to-project&gt;<\/code>\/hdl\/<\/strong><\/code><\/li>\n\n\n\n<li>Copy <code><strong><code>axis_cb_pwm<\/code>\/scripts\/axis_cb_pwm.tcl<\/strong><\/code> into <code><strong><code>&lt;path-to-project&gt;<\/code>\/scripts\/<\/strong><\/code><\/li>\n\n\n\n<li>Add <code>clock_spy.vhd<\/code> and <code>UserCbPwm.vhd<\/code> to the Vivado project using Add Sources.<\/li>\n\n\n\n<li>In Vivado Tcl Console, type <code><strong>source &lt;path-to-project&gt;\/scripts\/axis_cb_pwm.tcl<\/strong><\/code> to load the script.<\/li>\n\n\n\n<li>In Vivado Tcl Console, type <code><strong>create_hier_cell_axis_cb_pwm \/ &lt;desired_name&gt;<\/strong><\/code> to create an axis_cb_pwm.<\/li>\n<\/ol>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Example\"><\/span>Example<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This example illustrates how to insert the provided PWM modulator within a functional FPGA design, which receives the duty-cycle from the CPU user application. It was made for the B-Box 4, using the imperix firmware IP 4.0 Rev 0.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"2338\" height=\"628\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-43.png\" alt=\"\" class=\"wp-image-45117\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-43.png 2338w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-43-300x81.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-43-1024x275.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-43-768x206.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-43-1536x413.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-43-2048x550.png 2048w\" sizes=\"auto, (max-width: 2338px) 100vw, 2338px\" \/><figcaption class=\"wp-element-caption\">Example using the axis_cb_pwm module<\/figcaption><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Since the <strong>AXI4-Stream interface<\/strong> provided with the sandbox template introduces a delay on the CPU2FPGA signals (for reasons explained in <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128<\/a>) it is not used in this example. The <strong>sbio_register<\/strong> module is used instead.<\/div>\n\n\n\n<p><strong>1. Create an empty project<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Create the Vivado sandbox template<\/strong> following the &#8220;Creating the Vivado sandbox template&#8221; procedure detailed in the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development?currentThread=getting-started-with-fpga-programming\">Getting started<\/a>. <\/li>\n\n\n\n<li><strong>Remove the AXI4-Stream interface<\/strong> by clicking on <strong>ix_axis_interface <\/strong>and pressing <strong>Delete<\/strong>.<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"857\" height=\"559\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-28.png\" alt=\"\" class=\"wp-image-45095\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-28.png 857w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-28-300x196.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-28-768x501.png 768w\" sizes=\"auto, (max-width: 857px) 100vw, 857px\" \/><\/figure>\n\n\n\n<p><strong>2. Instantiate an AXI4-Stream carrier-based PWM module<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Download and unzip <strong>axis_cb_pwm.zip<\/strong> provided above.<\/li>\n\n\n\n<li>Copy <code>axis_cb_pwm\/hdl\/clock_spy.vhd<\/code> into <code>example_pwm\/hdl\/<\/code><\/li>\n\n\n\n<li>Copy <code>scripts\/scripts\/axis_cb_pwm.vhd<\/code> into <code><code>example_pwm<\/code>\/scripts\/<\/code><\/li>\n\n\n\n<li>Add <code>clock_spy.vhd<\/code> and <code>UserCbPwm.vhd<\/code> to the Vivado project using Add Sources.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"617\" height=\"460\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-29.png\" alt=\"\" class=\"wp-image-45096\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-29.png 617w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-29-300x224.png 300w\" sizes=\"auto, (max-width: 617px) 100vw, 617px\" \/><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li>In Vivado Tcl Console, type <code><strong>source &lt;path-to-project&gt;\/scripts\/axis_cb_pwm.tcl<\/strong><\/code> to load the script then type type <code><strong>create_hier_cell_axis_cb_pwm \/ &lt;desired_name&gt;<\/strong><\/code> to create an axis_cb_pwm<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"607\" height=\"232\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-32.png\" alt=\"\" class=\"wp-image-45099\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-32.png 607w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-32-300x115.png 300w\" sizes=\"auto, (max-width: 607px) 100vw, 607px\" \/><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"818\" height=\"578\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-33.png\" alt=\"\" class=\"wp-image-45100\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-33.png 818w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-33-300x212.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-33-768x543.png 768w\" sizes=\"auto, (max-width: 818px) 100vw, 818px\" \/><\/figure>\n\n\n\n<p><strong>3. Connect the PWM module frequency to CLOCK_1 so it can be changed using the <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> block<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Connect the PWM module to CLOCK_1. <\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"823\" height=\"231\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-35.png\" alt=\"\" class=\"wp-image-45106\" style=\"aspect-ratio:3.5628492608049798;width:527px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-35.png 823w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-35-300x84.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-35-768x216.png 768w\" sizes=\"auto, (max-width: 823px) 100vw, 823px\" \/><\/figure>\n<\/div>\n\n\n<p><strong>4. Output the PWM signal to Channel D0 (lanes 0 and 1)<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Connect the <code>o_pwm<\/code> output to <code>sb_pwm[0]<\/code>. Set <code>sb_pwm[1]<\/code> to <code>sb_pwm[47] <\/code>to 0.<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"952\" height=\"317\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-38.png\" alt=\"\" class=\"wp-image-45109\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-38.png 952w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-38-300x100.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-38-768x256.png 768w\" sizes=\"auto, (max-width: 952px) 100vw, 952px\" \/><\/figure>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><\/div>\n<\/div>\n\n\n\n<p><strong>5. Connect S_AXIS_DUTYCYLCE interface to the CPU<\/strong><\/p>\n\n\n\n<p>As explained in the example description, the AXI4-Stream is not used in this example because of the additional delay that it introduces on the CPU-to-FPGA signals. Instead, two SBO registers are concatenated to obtain a 32-bit value that can be written from the CPU.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Exchanging data between the CPU and the FPGA is documented in <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128<\/a>.<\/div>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Add <code>sbio_register.vhd<\/code> to the Vivado project using Add Sources.<\/li>\n\n\n\n<li>Instantiatean  <strong>sbio_register <\/strong>module.<\/li>\n\n\n\n<li>Concatenate <code>SBO_reg_00<\/code> and <code>SBO_reg_01<\/code> and connect the result to  <code>S_AXIS_DUTYCYCLE_tdata<\/code>.<\/li>\n\n\n\n<li>Connect <code>data_valid_pulse <\/code>to <code>S_AXIS_DUTYCYCLE_tvalid<\/code>.<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"303\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-40-1024x303.png\" alt=\"\" class=\"wp-image-45111\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-40-1024x303.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-40-300x89.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-40-768x227.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-40.png 1041w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><strong>6. Finally, connect the <code>clk<\/code> signals.<\/strong><\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"934\" height=\"202\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-41.png\" alt=\"\" class=\"wp-image-45112\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-41.png 934w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-41-300x65.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-41-768x166.png 768w\" sizes=\"auto, (max-width: 934px) 100vw, 934px\" \/><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Experimental-validation\"><\/span>Experimental validation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The CPU model is provided below in Simulink and PLECS.<\/p>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-center is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1826\" height=\"1263\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_simulink.png\" alt=\"\" class=\"wp-image-44532\" style=\"aspect-ratio:1.4463385354141656\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_simulink.png 1826w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_simulink-300x208.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_simulink-1024x708.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_simulink-768x531.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_simulink-1536x1062.png 1536w\" sizes=\"auto, (max-width: 1826px) 100vw, 1826px\" \/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1227\" height=\"1181\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_plecs.png\" alt=\"\" class=\"wp-image-44535\" style=\"aspect-ratio:1.0385759234515755;width:339px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_plecs.png 1227w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_plecs-300x289.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_plecs-1024x986.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_plecs-768x739.png 768w\" sizes=\"auto, (max-width: 1227px) 100vw, 1227px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sandbox_sbpwm_example.slx\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>pn127_sandbox_sbpwm_example.slx<\/strong><\/a><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sandbox_sbpwm_example.plecs\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>pn127_sandbox_sbpwm_example.plecs<\/strong><\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p>Along with the <strong>CONFIG<\/strong> block, the user application contains:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>An <strong>SB-PWM<\/strong> block with the configuration shown on the picture (right). It indicates that the source of channel 0 (CH0, LN0 LN1) must be taken from the sandbox and configures the dead-time to 1 us. The activate block input is set as visible and driven by a tunable parameter.<\/li>\n\n\n\n<li>A <strong>CLK<\/strong> block, where the clock CLK1 is set to 20 kHz. This clock drives the custom modulator in the FPGA.<\/li>\n\n\n\n<li>A <strong>MATLAB function<\/strong> (Simulink) or <strong>C-Script<\/strong> (PLECS) with an <strong>SBO<\/strong> block to convert the duty-cycle into two uint16 values and send the values to the FPGA. More information about the CPU-FPGA communication is available <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga?currentThread=getting-started-with-fpga-programming\">here<\/a>.<\/li>\n<\/ul>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"478\" height=\"673\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_simulink_mask-1.png\" alt=\"\" class=\"wp-image-44818\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_simulink_mask-1.png 478w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_simulink_mask-1-213x300.png 213w\" sizes=\"auto, (max-width: 478px) 100vw, 478px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>The figure below shows the result, obtained by controlling the activate and duty-cycle values via the built-in Cockpit <a href=\"https:\/\/imperix.com\/doc\/help\/scope-module#Transient-generator-configuration\">transient generator<\/a>. The duty-cycle is 0.5 by default, then changed to 0.8 after 0.55 ms. As expected, PWM outputs are clamped to 0 until the activate signal is asserted after 0.1 ms.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Observing PWM signals in the Scope is only available for the <a href=\"https:\/\/imperix.com\/products\/control\/rcp-controller\/\">B-Box 4<\/a><\/strong>.<br>For other imperix controllers, electrical PWM outputs can be monitored with an oscilloscope.<\/div>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"523\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_cockpit-1024x523.png\" alt=\"\" class=\"wp-image-44546\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_cockpit-1024x523.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_cockpit-300x153.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_cockpit-768x393.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn127_sbpwm_example_cockpit.png 1309w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Going-further\"><\/span>Going further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Debugging-an-FPGA-module\"><\/span>Debugging an FPGA module<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>When designing a PWM modulator or other peripherals within the FPGA, it is highly useful to capture and observe internal FPGA signals similar to a simulation environment. <a href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\">PN129<\/a><strong> <\/strong>explains how to capture these signals using a&nbsp;Xilinx&nbsp;<strong>Integrated Logic Analyzer (ILA)<\/strong>, like shown in the screenshot below.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"929\" height=\"443\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-44.png\" alt=\"\" class=\"wp-image-45176\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-44.png 929w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-44-300x143.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-44-768x366.png 768w\" sizes=\"auto, (max-width: 929px) 100vw, 929px\" \/><figcaption class=\"wp-element-caption\">The <strong>axis_cb_pwm <\/strong>module when receiving a duty-cycle step from 0.2 to 0.8<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Using-automated-code-generation-to-avoid-writing-VHDL\"><\/span>Using automated code generation to avoid writing VHDL<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The provided carrier-based modulator is written in VHDL. It is possible however to achieve the same functionality without writing a single line of HDL code. As illustrated on the screenshots below, <strong>automated code generation tools<\/strong> such as <em><strong>AMD Vitis Model Composer<\/strong><\/em>&nbsp;and&nbsp;<strong><em>MATLAB HDL <\/em><\/strong><em><strong>Coder<\/strong><\/em> can be used to create the same modulator using MATLAB Simulink.<\/p>\n\n\n\n<p>The following pages explain how to re-create the same modulator using these tools:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/matlab-hdl-coder\">Carrier-based PWM using MATLAB HDL Coder<\/a><\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-system-generator\">Carrier-based PWM using AMD Vitis Model Composer HDL<\/a> (formerly System Generator, or SysGen)<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"583\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-45.png\" alt=\"\" class=\"wp-image-45178\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-45.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-45-300x171.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-45-768x437.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Carrier-based PWM using MATLAB HDL Coder<\/figcaption><\/figure>\n<\/div>\n\n\n<p><br><\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"406\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-46.png\" alt=\"\" class=\"wp-image-45180\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-46.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-46-300x119.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-46-768x305.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Carrier-based PWM using Xilinx System Generator<br><\/figcaption><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>Beyond the built-in modulators accessible from the user application, the imperix sandbox enables PWM generation directly within the FPGA, allowing for the implementation of custom&#8230;<\/p>\n","protected":false},"author":17,"featured_media":2995,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[141],"coauthors":[82],"class_list":["post-40118","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","user-manuals-getting-started-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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