{"id":40120,"date":"2026-01-21T08:26:30","date_gmt":"2026-01-21T08:26:30","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=40120"},"modified":"2026-04-16T13:44:08","modified_gmt":"2026-04-16T13:44:08","slug":"exchanging-data-between-the-cpu-and-the-fpga","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga","title":{"rendered":"Exchanging data between the CPU and the FPGA"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#SBIO-bus\" >SBIO bus<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#SBIO-helper-modules\" >SBIO helper modules<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#SBIO-registers\" >SBIO registers<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#SBIO-interconnect\" >SBIO interconnect<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#AXI4-Stream-interface\" >AXI4-Stream interface<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#Exchanging-floats-signals\" >Exchanging floats signals<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#Simulink-model\" >Simulink model<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#PLECS-model\" >PLECS model<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#Example-using-the-AXI4-Stream-interface\" >Example using the AXI4-Stream interface<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#Experimental-validation\" >Experimental validation<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\/#Going-further\" >Going further<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>On imperix controllers, the CPU exchanges data with the FPGA via the <strong>SBIO bus<\/strong>. This memory-mapped bus allows the CPU user app to read and write FPGA registers via the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> and <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> blocks in Simulink and PLECS.<\/p>\n\n\n\n<p>On the FPGA side, helper modules are provided to abstract the bus complexity and expose registers instead. An AXI4-Stream interface is also available, designed to facilitate the implementation of FPGA-based control algorithms.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Note on FPGA development for imperix controllers<\/strong><br>Customizing the FPGA firmware involves instantiating the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">imperix firmware IP<\/a> within Xilinx Vivado to edit the surrounding programmable logic, known as the sandbox. For step-by-step instructions on creating the required FPGA sandbox template, refer to the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development?currentThread=getting-started-with-fpga-programming\">getting started<\/a>\u00a0guide.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"SBIO-bus\"><\/span>SBIO bus<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The <strong>SBIO_BUS<\/strong> (SandBox IO bus) is a 16-bit memory-mapped bus allowing the CPU to address up to 1024 SBI or SBO registers in the FPGA. The <code><strong>reading<\/strong><\/code> and <strong><code>data_valid_pulse<\/code> <\/strong>signals serves to synchronize the user logic to the reading and writing cycles.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The bus operation details are documented in the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">imperix firmware IP product guide<\/a>. However, direct interaction with these signals is rarely required due to the availability of the <strong>SBIO helper modules<\/strong> described in the following section.<\/div>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"375\" height=\"479\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbio_bus_1.png\" alt=\"\" class=\"wp-image-44918\" style=\"width:329px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbio_bus_1.png 375w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbio_bus_1-235x300.png 235w\" sizes=\"auto, (max-width: 375px) 100vw, 375px\" \/><figcaption class=\"wp-element-caption\">SBIO_BUS and associated timing signals<\/figcaption><\/figure>\n<\/div>\n\n\n<p>The user interacts with the bus using the following blocks:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> blocks to <strong>read <\/strong>FPGA registers <strong>before <\/strong>the execution of the CPU task.<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> blocks to <strong>write <\/strong>FPGA registers <strong>after <\/strong>the execution of the CPU task.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"721\" height=\"268\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbi_sbo_blocks_example.png\" alt=\"\" class=\"wp-image-40242\" style=\"aspect-ratio:2.690486317878917;width:467px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbi_sbo_blocks_example.png 721w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbi_sbo_blocks_example-300x112.png 300w\" sizes=\"auto, (max-width: 721px) 100vw, 721px\" \/><\/figure>\n<\/div>\n\n\n<p>The image below illustrates the CPU execution phases and related signals, which are further described in the  <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">imperix firmware IP product guide<\/a>.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>read <\/strong>phase is indicated by the assertion of the <code>reading<\/code> signal. During that time, <strong>SBI<\/strong> registers are read and cached in the CPU buffer, making them available to the user application.<\/li>\n\n\n\n<li>At the end of the processing phase, <strong>SBO<\/strong> values are written to the FPGA. The end of the <strong>write<\/strong> phase is indicated by the assertion of the <code>data_valid_pulse<\/code> signal.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"416\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_execution_cycle_phases-1024x416.png\" alt=\"\" class=\"wp-image-44423\" style=\"width:560px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_execution_cycle_phases-1024x416.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_execution_cycle_phases-300x122.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_execution_cycle_phases-768x312.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_execution_cycle_phases-1536x623.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_execution_cycle_phases.png 1959w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Execution timing signals<br><\/figcaption><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">When set as <em>configuration registers<\/em>, the value of the SBO registers is only written once at the code start-up. More information is available in the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> documentation page.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"sbio-helper-modules\"><span class=\"ez-toc-section\" id=\"SBIO-helper-modules\"><\/span>SBIO helper modules<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The following SBIO helper modules are provided in the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox?currentThread=getting-started-with-fpga-programming\">imperix source files<\/a> to abstract the SBIO bus complexity.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"SBIO-registers\"><\/span>SBIO registers<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The <strong><code>sbio_registers<\/code> <\/strong>and <strong><code>sbio_256_registers<\/code> <\/strong>modules provide 64, respectively 256, addressable 16-bit registers accessible from the CPU using SBI and SBO blocks.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"708\" height=\"559\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_registers.png\" alt=\"\" class=\"wp-image-40244\" style=\"aspect-ratio:1.2666105971404542;width:599px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_registers.png 708w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_registers-300x237.png 300w\" sizes=\"auto, (max-width: 708px) 100vw, 708px\" \/><figcaption class=\"wp-element-caption\"><strong><code>sbio_registers<\/code> <\/strong>module<\/figcaption><\/figure>\n<\/div>\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"SBIO-interconnect\"><\/span>SBIO interconnect<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The <strong><code>sbio_interconnect<\/code> <\/strong>divides the full range of 1024 addresses of the SBIO bus into four ranges of 256 addresses each, allowing to connect multiple SBIO modules.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"726\" height=\"772\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_interconnect.png\" alt=\"\" class=\"wp-image-40259\" style=\"aspect-ratio:0.9404283658080732;width:726px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_interconnect.png 726w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_interconnect-282x300.png 282w\" sizes=\"auto, (max-width: 726px) 100vw, 726px\" \/><figcaption class=\"wp-element-caption\"><strong><code>sbio_interconnect<\/code> <\/strong>used to connect multiple SBIO modules to the SBIO_BUS<\/figcaption><\/figure>\n<\/div>\n\n\n<p>The address mapping of the SBIO interconnect is shown below, it divides the SBIO addressable range in 4 smaller areas.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter is-resized\"><a class=\"firelight-lightbox fancybox image\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/08\/image-3-1024x666.png\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"666\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/08\/image-3-1024x666.png\" alt=\"\" class=\"wp-image-30678\" style=\"aspect-ratio:1.537578606752549;width:522px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/08\/image-3-1024x666.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/08\/image-3-300x195.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/08\/image-3-768x499.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/08\/image-3-1536x999.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2024\/08\/image-3.png 1784w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><figcaption class=\"wp-element-caption\"><code>sbio_interconnect<\/code> memory mapping<\/figcaption><\/figure>\n<\/div>\n\n\n<p>As an example, writing to <strong>SBO_reg_03<\/strong> of an <strong>sbio_register<\/strong> block connected to <strong>S2_SBIO_BUS<\/strong> requires an SBO block addressed to register 512+3=515.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"252\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_interconnect_example.png\" alt=\"\" class=\"wp-image-40260\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_interconnect_example.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_interconnect_example-300x74.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_sbio_interconnect_example-768x189.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"484\" height=\"128\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbo_simulink_example.png\" alt=\"\" class=\"wp-image-40262\" style=\"width:372px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbo_simulink_example.png 484w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sbo_simulink_example-300x79.png 300w\" sizes=\"auto, (max-width: 484px) 100vw, 484px\" \/><\/figure>\n<\/div>\n\n\n<h3 class=\"wp-block-heading\" id=\"axi4-stream-interface\"><span class=\"ez-toc-section\" id=\"AXI4-Stream-interface\"><\/span>AXI4-Stream interface<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The AXI4-Stream interface provided with the sandbox template allows exchanging 32-bit data between the CPU and FPGA using the <strong>M_AXIS_CPU2FPGA<\/strong>&nbsp;and <strong>S_AXIS_FPGA2CPU<\/strong>&nbsp;interfaces.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"872\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_axis_interface-1024x872.png\" alt=\"\" class=\"wp-image-40245\" style=\"aspect-ratio:1.174325616096617;width:737px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_axis_interface-1024x872.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_axis_interface-300x255.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_axis_interface-768x654.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_vivado_axis_interface.png 1149w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p>The  AXI4-Stream interface was made specifically to facilitate implementing <strong>control algorithm in FPGA<\/strong> , such as the high-speed current control described in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">TN147<\/a>. The interface is designed for algorithms that share the following characteristics:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The control algorithm is <strong>fully implemented in the FPGA<\/strong>.<\/li>\n\n\n\n<li>The control algorithm is executed at the <strong>ADC sampling rate (SCLK rate)<\/strong>, which may be faster than the CPU rate (postscaler &gt; 1).<\/li>\n\n\n\n<li>The control algorithm operates with <strong>32-bit floating-point<\/strong> data.<\/li>\n\n\n\n<li>The CPU model is used to <strong>writes slow-varying signals<\/strong> such as configuration parameters (Kp, Ki, etc.) and slow-varying references, or serves for <strong>monitoring\/debugging<\/strong>.<\/li>\n<\/ul>\n\n\n\n<p>To facilitate the design of such algorithm, the following design choices were made:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The M_AXIS_ADC and M_AXIS_CPU2FPGA interfaces output data <strong>at the same time<\/strong>, synchronized to the <code>adc_done_pulse<\/code>. The consequence is that <strong>CPU2FPGA signals are delayed<\/strong> to the end of the next acquisition phase.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"483\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_a-1024x483.png\" alt=\"\" class=\"wp-image-44912\" style=\"width:520px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_a-1024x483.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_a-300x142.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_a-768x362.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_a-1536x725.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_a.png 2022w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li>The M_AXIS_ADC and M_AXIS_CPU2FPGA interfaces output data <strong>at the same rate.<\/strong> That means that when the CPU execution rate is slower than the sampling clock (postscaler &gt; 1) the same CPU2FPGA values are <strong>outputted multiple times<\/strong>.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"624\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_b-1024x624.png\" alt=\"\" class=\"wp-image-44913\" style=\"width:520px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_b-1024x624.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_b-300x183.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_b-768x468.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_b-1536x936.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_timings_b.png 1974w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\" id=\"axis-address-mapping\">Address mapping of the AXI4-Stream interface<\/h4>\n\n\n\n<p>The mapping between the 16-bit SBIO registers and the 32-bit AXI4-Stream interfaces is the following:<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"393\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_mapping-1.png\" alt=\"\" class=\"wp-image-44928\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_mapping-1.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_mapping-1-300x115.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_axis_interface_mapping-1-768x295.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>These registers are typically used to exchange floating-point values with the CPU.  Ready-to-use helper functions for Simulink and PLECS are provided in the next section.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"exchanging-floats\"><span class=\"ez-toc-section\" id=\"Exchanging-floats-signals\"><\/span>Exchanging floats signals<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Algorithms typically operate using 32-bit floating-point values. The Simulink and PLECS templates provided below provide ready-to-use scripts to concatenate or decompose the 16-bit values and interpret the result as a floating-point variable.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Simulink-model\"><\/span>Simulink model<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"685\" height=\"96\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-49.png\" alt=\"\" class=\"wp-image-45243\" style=\"aspect-ratio:7.1365782191111835;width:653px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-49.png 685w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-49-300x42.png 300w\" sizes=\"auto, (max-width: 685px) 100vw, 685px\" \/><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/float_exchange_template.slx\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>float_exchange_template.slx<\/strong><\/a><\/div>\n\n\n\n<p><\/p>\n\n\n\n<p>In Simulink, the following <a href=\"https:\/\/ch.mathworks.com\/help\/simulink\/slref\/matlabfunction.html\">MATLAB functions<\/a> are used.<\/p>\n\n\n\n<p><strong>sbi2single<\/strong><\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"Matlab\" data-shcb-language-slug=\"matlab\"><span><code class=\"hljs language-matlab\"><span class=\"hljs-function\"><span class=\"hljs-keyword\">function<\/span> <span class=\"hljs-title\">y<\/span> = <span class=\"hljs-title\">sbi2single<\/span><span class=\"hljs-params\">(u1,u2)<\/span><\/span>\n  y = single(<span class=\"hljs-number\">0<\/span>); <span class=\"hljs-comment\">% fix simulink bug: force compiled size of output<\/span>\n  y = typecast(&#91;uint16(u1) uint16(u2)], <span class=\"hljs-string\">'single'<\/span>);<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">Matlab<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">matlab<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<p><strong>single2sbo<\/strong><\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-2\" data-shcb-language-name=\"Matlab\" data-shcb-language-slug=\"matlab\"><span><code class=\"hljs language-matlab\"><span class=\"hljs-function\"><span class=\"hljs-keyword\">function<\/span> <span class=\"hljs-params\">&#91;y1,y2]<\/span> = <span class=\"hljs-title\">single2sbo<\/span><span class=\"hljs-params\">(u)<\/span><\/span>\n  temp = typecast(single(u),<span class=\"hljs-string\">'uint16'<\/span>);\n  y1 = temp(<span class=\"hljs-number\">1<\/span>);\n  y2 = temp(<span class=\"hljs-number\">2<\/span>);<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-2\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">Matlab<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">matlab<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"PLECS-model\"><\/span>PLECS model<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"650\" height=\"121\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-50.png\" alt=\"\" class=\"wp-image-45244\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-50.png 650w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/image-50-300x56.png 300w\" sizes=\"auto, (max-width: 650px) 100vw, 650px\" \/><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/float_exchange_template.plecs\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>float_exchange_template.plecs<\/strong><\/a><\/div>\n\n\n\n<p><\/p>\n\n\n\n<p>The PLECS <a href=\"https:\/\/www.plexim.com\/products\/plecs\/control\/cscripts\">C-Script<\/a> function are provided below.<\/p>\n\n\n\n<p><strong>sbi2single<\/strong><\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-3\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-keyword\">float<\/span> y1 = InputSignal(<span class=\"hljs-number\">0<\/span>,<span class=\"hljs-number\">0<\/span>);\n<span class=\"hljs-keyword\">float<\/span> y2 = InputSignal(<span class=\"hljs-number\">0<\/span>,<span class=\"hljs-number\">1<\/span>);\n\n<span class=\"hljs-keyword\">union<\/span> { <span class=\"hljs-keyword\">unsigned<\/span> <span class=\"hljs-keyword\">int<\/span> i; <span class=\"hljs-keyword\">float<\/span> f; } conv;\nconv.i = ((<span class=\"hljs-keyword\">unsigned<\/span> short)y2 &lt;&lt; <span class=\"hljs-number\">16<\/span>) | (<span class=\"hljs-keyword\">unsigned<\/span> short)y1;\n\nOutputSignal(<span class=\"hljs-number\">0<\/span>,<span class=\"hljs-number\">0<\/span>) = conv.f;<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-3\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<p><strong>single2sbo<\/strong><\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-4\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\">\n<span class=\"hljs-keyword\">union<\/span> { <span class=\"hljs-keyword\">unsigned<\/span> <span class=\"hljs-keyword\">int<\/span> i; <span class=\"hljs-keyword\">float<\/span> f; } conv;\n\nconv.f = InputSignal(<span class=\"hljs-number\">0<\/span>,<span class=\"hljs-number\">0<\/span>);\n\nOutputSignal(<span class=\"hljs-number\">0<\/span>,<span class=\"hljs-number\">0<\/span>) = (<span class=\"hljs-keyword\">unsigned<\/span> short)(conv.i &amp; <span class=\"hljs-number\">0xFFFF<\/span>);\nOutputSignal(<span class=\"hljs-number\">0<\/span>,<span class=\"hljs-number\">1<\/span>) = (<span class=\"hljs-keyword\">unsigned<\/span> short)(conv.i &gt;&gt; <span class=\"hljs-number\">16<\/span>);<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-4\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Example-using-the-AXI4-Stream-interface\"><\/span>Example using the AXI4-Stream interface<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>This step-by-step example implements the FPGA design shown below which:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Receives two floating-point values from the user application (<strong><code>CPU2FPGA_00<\/code>&nbsp;<\/strong>and&nbsp;<strong><code>CPU2FPGA_01<\/code><\/strong>).<\/li>\n\n\n\n<li>Multiplies the two values together using a <strong>Xilinx Floating-Point IP<\/strong>.<\/li>\n\n\n\n<li>Sends the result back to the user application running in the CPU (<strong><code>FPGA2CPU_00<\/code><\/strong>).<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1739\" height=\"1118\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_design.png\" alt=\"\" class=\"wp-image-44376\" style=\"aspect-ratio:1.5468812382912074\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_design.png 1739w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_design-300x193.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_design-1024x658.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_design-768x494.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_design-1536x987.png 1536w\" sizes=\"auto, (max-width: 1739px) 100vw, 1739px\" \/><figcaption class=\"wp-element-caption\">Two values are multiplied in the FPGA and sent back to the CPU<\/figcaption><\/figure>\n<\/div>\n\n\n<p><strong>Start from template<\/strong><\/p>\n\n\n\n<p>Create the Vivado sandbox template&nbsp;following the \u201cCreating the Vivado sandbox template\u201d procedure detailed in the&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development?currentThread=getting-started-with-fpga-programming\">getting started<\/a>.<\/p>\n\n\n\n<p><strong>Add a multiplier<\/strong><\/p>\n\n\n\n<p>To add an AXI4-Stream IP that multiplies two floating point value:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Right-click somewhere in the block design, select&nbsp;<strong>Add IP<\/strong>&nbsp;and search for&nbsp;<strong>Floating-point<\/strong>. Press Enter.<\/li>\n\n\n\n<li>In the Block Properties panel, rename the block to&nbsp;<strong>multiplier<\/strong>.<\/li>\n\n\n\n<li>Double-click on the IP to open the configuration panel. In the&nbsp;<strong>Operation Selection<\/strong>&nbsp;tab, select&nbsp;<strong>Multiply<\/strong>&nbsp;for the operation. Other parameters can be let in their default configuration.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"793\" height=\"592\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_multiplier.png\" alt=\"\" class=\"wp-image-44378\" style=\"aspect-ratio:1.3395744680851063\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_multiplier.png 793w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_multiplier-300x224.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_multiplier-768x573.png 768w\" sizes=\"auto, (max-width: 793px) 100vw, 793px\" \/><\/figure>\n<\/div>\n\n\n<p><strong>Connect the multiplier<\/strong><\/p>\n\n\n\n<p>The design can be finalized by applying the following connections between the AXI4-Stream interface and the multiplier:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>M_AXIS_CPU2FPGA_00<\/strong> to <strong>S_AXIS_A<\/strong> <\/li>\n\n\n\n<li><strong>M_AXIS_CPU2FPGA_01<\/strong> to <strong>S_AXIS_B<\/strong> <\/li>\n\n\n\n<li><strong>M_AXIS_RESULT<\/strong> to <strong>S_AXIS_FPGA2CPU_00<\/strong><\/li>\n<\/ul>\n\n\n\n<p>The <strong>aclk<\/strong> signal of the multiplier must be connected to the <strong>clk_250_mhz<\/strong> clock.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1736\" height=\"1112\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_connections.png\" alt=\"\" class=\"wp-image-44377\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_connections.png 1736w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_connections-300x192.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_connections-1024x656.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_connections-768x492.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_connections-1536x984.png 1536w\" sizes=\"auto, (max-width: 1736px) 100vw, 1736px\" \/><\/figure>\n<\/div>\n\n\n<p><strong>Save, build and load the design<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Save the design and click on&nbsp;<strong>Generate Bitstream<\/strong>&nbsp;in the sidebar on the left.<\/li>\n\n\n\n<li>Load the bitstream onto the controller via Cockpit.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Experimental-validation\"><\/span>Experimental validation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The FPGA design is tested using the CPU model provided below. It contains two tunable parameters for the two operands, which are transmitted to the FPGA through SBO blocks and the result is received from the FPGA through an SBI block. The <strong>sbi2single <\/strong>and <strong>single2sbo <\/strong>conversions are described in the <a href=\"#exchanging-floats\">Exchanging floats<\/a> section above.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sandbox_sbio_example.slx\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>pn128_sandbox_sbio_example.slx<\/strong><\/a><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_sandbox_sbio_example.plecs\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>pn128_sandbox_sbio_example.plecs<\/strong><\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"925\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_simulink-1024x925.png\" alt=\"\" class=\"wp-image-44404\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_simulink-1024x925.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_simulink-300x271.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_simulink-768x694.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_simulink.png 1152w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"871\" height=\"1024\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_plecs-871x1024.png\" alt=\"\" class=\"wp-image-44405\" style=\"aspect-ratio:0.8506071731149393;width:289px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_plecs-871x1024.png 871w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_plecs-255x300.png 255w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_plecs-768x903.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_plecs.png 908w\" sizes=\"auto, (max-width: 871px) 100vw, 871px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>The expected results is shown in the figure below, which is obtained by checking different values for both operands thanks to the built-in Cockpit <a href=\"https:\/\/imperix.com\/doc\/help\/scope-module#Transient-generator-configuration\">transient generator<\/a>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"659\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_cockpit-1024x659.png\" alt=\"\" class=\"wp-image-44411\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_cockpit-1024x659.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_cockpit-300x193.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_cockpit-768x494.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn128_loopback_example_cockpit.png 1243w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Going-further\"><\/span>Going further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">TN147<\/a> example uses the <strong>AXI4-Stream interface<\/strong> for the CPU model to interact with the current control implemented in FPGA. The <strong>CPU2FPGA <\/strong>interfaces are used to write configuration signals (Kp, Ki, etc.) and slow-varying references (I<sub>ref<\/sub>), while the <strong>FPGA2CPU <\/strong>interfaces are dedicated to monitoring and debugging.<\/p>\n\n\n\n<p>In <a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a>, a PWM modulator is implemented in FPGA and the duty-cycle is provided by the CPU model. To avoid the additional delay introduced by the AXI4-Stream interface, the <strong>sbio_register <\/strong>helper is used instead. Two SBO register are concatenated to form a 32-bit floating-point value.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>On imperix controllers, the CPU exchanges data with the FPGA via the SBIO bus. This memory-mapped bus allows the CPU user app to read and&#8230;<\/p>\n","protected":false},"author":17,"featured_media":2995,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[108],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[141],"coauthors":[82],"class_list":["post-40120","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","provided-results-experimental","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","user-manuals-getting-started-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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