{"id":40126,"date":"2026-01-21T08:27:49","date_gmt":"2026-01-21T08:27:49","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=40126"},"modified":"2026-04-16T07:42:58","modified_gmt":"2026-04-16T07:42:58","slug":"how-to-debug-an-fpga-design","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design","title":{"rendered":"Using an ILA to debug an FPGA designF"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Enabling-the-debug-interface\" >Enabling the debug interface<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Adding-signals-to-the-ILA\" >Adding signals to the ILA<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Configuring-the-ILA\" >Configuring the ILA<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Managing-clocks-and-capture-windows\" >Managing clocks and capture windows<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Operating-the-ILA-in-Vivado\" >Operating the ILA in Vivado<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Establishing-the-XVC-connection\" >Establishing the XVC connection<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Loading-the-probes-file\" >Loading the probes file<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#Operating-the-ILA\" >Operating the ILA<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\/#To-go-further\" >To go further<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>Debugging an FPGA design can be difficult without clear visibility into the high-speed logic fabric, where signals change at nanosecond scales. Xilinx <strong>Integrated Logic Analyzer (ILA)<\/strong> provides that visibility by acting as an embedded oscilloscope inside the FPGA. It captures internal signals in real time and stores them in dedicated Block RAM (BRAM) for cycle-accurate observation.<\/p>\n\n\n\n<p>To make the ILA practical to use to FPGA sandbox users, imperix supports the <strong>Xilinx Virtual Cable (XVC) protocol<\/strong>. This Ethernet-based protocol acts like a JTAG cable and provides a means to connect to ILAs without opening the enclosure to attach a physical debugger.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"> Xilinx Virtual Cable (XVC) protocol support requires the <strong>imperix firmware IP (IXIP) 3.10 Rev. 3 or later<\/strong>.<br>The latest version of the IP is available on the\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox\">download<\/a>\u00a0page and <a href=\"https:\/\/imperix.com\/doc\/help\/upgrade-of-the-imperix-firmware-ip\">PN174<\/a>\u00a0provides a step-by-step guide on upgrading an existing FPGA design.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Enabling-the-debug-interface\"><\/span>Enabling the debug interface<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Before adding ILA cores to a design, the debug infrastructure must be enabled in the imperix firmware IP. This allows Vivado to communicate with the debug cores over the network via the XVC protocol.<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Enable <strong>BSCAN <\/strong>in the imperix firmware IP. The BSCAN (Boundary Scan) interface is the virtual port that provides access to the FPGA debug chain.\n<ul class=\"wp-block-list\">\n<li>Double-click the <strong>IMPERIX_FW<\/strong> IP in the block design to open the configuration dialog.<\/li>\n\n\n\n<li>Navigate to the <strong>Configuration<\/strong> tab.<\/li>\n\n\n\n<li>Check the <strong>Make BSCAN interface available from the sandbox<\/strong> and click OK. This exposes a BSCAN port on the IP block.<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"666\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_BSCAN-1024x666.png\" alt=\"\" class=\"wp-image-42201\" style=\"aspect-ratio:1.537578606752549;width:664px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_BSCAN-1024x666.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_BSCAN-300x195.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_BSCAN-768x499.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_BSCAN.png 1043w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"2\" class=\"wp-block-list\">\n<li>Add and connect the <strong>Debug Bridge IP<\/strong>. The Debug Bridge acts as a switch, routing commands from the CPU to all connected debug cores.\n<ul class=\"wp-block-list\">\n<li>Right-click in the block design and select <strong>Add IP<\/strong>.<\/li>\n\n\n\n<li>Search for <strong>Debug Bridge<\/strong> and add it to the design.<\/li>\n\n\n\n<li>Double-click the Debug Bridge to configure it and ensure the Bridge Type is set to <strong>From BSCAN to DebugHub<\/strong>.<\/li>\n\n\n\n<li>Connect <code>S_BSCAN<\/code> to the <code>BSCAN<\/code> port of the <code>IMPERIX_FW<\/code> and connect <code>clk<\/code> to <code>clk_250_mhz<\/code>.<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"948\" height=\"367\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connect_debug_bridge.png\" alt=\"\" class=\"wp-image-42202\" style=\"aspect-ratio:2.5832393065955483;width:659px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connect_debug_bridge.png 948w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connect_debug_bridge-300x116.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connect_debug_bridge-768x297.png 768w\" sizes=\"auto, (max-width: 948px) 100vw, 948px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Adding-signals-to-the-ILA\"><\/span>Adding signals to the ILA<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>While the remote XVC network architecture is specific to the controller environment, instantiating and operating the ILA cores relies entirely on standard Xilinx Vivado workflows. The following sections summarize these standard procedures for convenience.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">Since the XVC connection relies on a Debug Bridge, ILA cores must be instantiated directly in the block design. The post-synthesis &#8220;Mark Debug&#8221; flow is not supported in this configuration.<\/div>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>In the block design, <strong>right-click on the signals\/wires<\/strong> to be observed<\/li>\n\n\n\n<li>Select <strong>Debug<\/strong> from the context menu<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"962\" height=\"751\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_mark_debug.png\" alt=\"\" class=\"wp-image-42204\" style=\"aspect-ratio:1.2809766022380469;width:615px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_mark_debug.png 962w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_mark_debug-300x234.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_mark_debug-768x600.png 768w\" sizes=\"auto, (max-width: 962px) 100vw, 962px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"3\" class=\"wp-block-list\">\n<li>A debug marker (small bug icon) appears on the signal, and a green banner appears at the top: <strong>&#8220;Designer Assistance available. Run Connection Automation&#8221;<\/strong><\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"722\" height=\"322\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_automatic_connection.png\" alt=\"\" class=\"wp-image-42205\" style=\"aspect-ratio:2.242263483642794;width:582px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_automatic_connection.png 722w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_automatic_connection-300x134.png 300w\" sizes=\"auto, (max-width: 722px) 100vw, 722px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"4\" class=\"wp-block-list\">\n<li>Click <strong>Run Connection Automation<\/strong><\/li>\n\n\n\n<li>In the dialog, configure the ILA options:\n<ul class=\"wp-block-list\">\n<li><strong>Probe Type<\/strong>: Select &#8220;Data and Trigger&#8221; to use the signal for both capture and triggering<\/li>\n\n\n\n<li><strong>Source Clock<\/strong>: Select the clock for the signal&#8217;s domain (typically <code>\/IXIP\/clk_250_mhz<\/code>)<\/li>\n\n\n\n<li><strong>System ILA<\/strong>: Leave as &#8220;Auto&#8221; to let Vivado create a new ILA<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"532\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_ILA_config-1024x532.png\" alt=\"\" class=\"wp-image-42207\" style=\"aspect-ratio:1.9248671991439599;width:710px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_ILA_config-1024x532.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_ILA_config-300x156.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_ILA_config-768x399.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_ILA_config.png 1050w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Some signals\/wires are already associated to a clock domain by default<\/figcaption><\/figure>\n<\/div>\n\n\n<ol start=\"6\" class=\"wp-block-list\">\n<li>Click <strong>OK<\/strong>. Vivado automatically creates a System ILA and connects everything.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"629\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connection_ila-1024x629.png\" alt=\"\" class=\"wp-image-42208\" style=\"aspect-ratio:1.6280302540565001;width:635px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connection_ila-1024x629.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connection_ila-300x184.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connection_ila-768x472.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_connection_ila.png 1053w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">To add more signals to the same ILA, repeat the process and leave &#8220;System ILA&#8221; set to &#8220;Auto&#8221;. Vivado will automatically connect the signal to an existing ILA that uses the same clock domain. Alternatively, multiple signals can be selected via right-click before running connection automation to add them all at once.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"Configuring-the-ILA\"><span class=\"ez-toc-section\" id=\"Configuring-the-ILA\"><\/span>Configuring the ILA<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>After creating the System ILA, double-click the block to open the configuration dialog. Depending on whether individual wires or full AXI interfaces are being monitored, the dialog displays up to three main tabs:<\/p>\n\n\n\n<p><strong>1. General Options tab<\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"642\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_general_options-1024x642.png\" alt=\"\" class=\"wp-image-42209\" style=\"aspect-ratio:1.5950850302435318;width:763px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_general_options-1024x642.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_general_options-300x188.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_general_options-768x482.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_general_options-1536x963.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_general_options.png 1556w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Sample Data Depth<\/strong>: Sets the number of samples to capture. Increasing this value extends the capture window but consumes more Block RAM.<\/li>\n\n\n\n<li><strong>Number of Probes<\/strong>: Total number of individual signal ports. This value can be increased to manually add probes beyond those created by automation.<\/li>\n\n\n\n<li><strong>Number of Comparators<\/strong>: Sets the comparison units per probe for trigger conditions. One is usually sufficient unless complex logic is required.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Probe_Ports tab<\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"435\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_options-1024x435.png\" alt=\"\" class=\"wp-image-42210\" style=\"aspect-ratio:2.354084875677697;width:765px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_options-1024x435.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_options-300x127.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_options-768x326.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_options-1536x653.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_options.png 1556w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Probe Width<\/strong>: Defined in bits. With &#8220;Native Probe width propagation&#8221; set to AUTO, this matches the connected signal automatically.<\/li>\n\n\n\n<li><strong>Data and\/or Trigger<\/strong>: Sets whether a probe is used for data capture, triggering, or both.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"376\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_interface_options-1024x376.png\" alt=\"\" class=\"wp-image-42211\" style=\"aspect-ratio:2.7234778847193684;width:760px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_interface_options-1024x376.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_interface_options-300x110.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_interface_options-768x282.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_interface_options-1536x565.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_interface_options.png 1556w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p><strong>3. Interface Options tab<\/strong> This tab appears when full interfaces (such as AXI4-Stream) are connected to the ILA. It enables the configuration of specific slots and signals within the interface for use in triggering or data storage.<\/p>\n\n\n\n<p>The <strong>Resources<\/strong> panel on the left provides real-time estimates of Block RAM usage, helping to balance capture depth against available hardware resources.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Managing-clocks-and-capture-windows\"><\/span>Managing clocks and capture windows<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>The ILA must be clocked by the same source driving the signals under observation; using a different clock will result in unstable or incorrect data. For most sandbox designs, connect the ILA clock input to <code>clk_250_mhz<\/code>.<\/p>\n\n\n\n<p>The duration of the capture window is determined by the sample depth and the clock frequency. At a standard 250 MHz frequency, the capture times are as follows:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><td><strong>Sample Depth<\/strong><\/td><td><strong>Capture Time at 250 MHz<\/strong><\/td><td><strong>Approximate BRAM Usage<\/strong><\/td><\/tr><\/thead><tbody><tr><td>1024<\/td><td>4.1 \u00b5s<\/td><td>1 BRAM per 36-bit probe<\/td><\/tr><tr><td>2048<\/td><td>8.2 \u00b5s<\/td><td>2 BRAM per 36-bit probe<\/td><\/tr><tr><td>4096<\/td><td>16.4 \u00b5s<\/td><td>4 BRAM per 36-bit probe<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Operating-the-ILA-in-Vivado\"><\/span>Operating the ILA in Vivado<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Once the bitstream is generated and loaded into the controller using Cockpit, signals can be accessed through the Vivado Hardware Manager.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Establishing-the-XVC-connection\"><\/span>Establishing the XVC connection<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li><strong>Open Hardware Manager<\/strong> in Vivado (Flow Navigator \u2192 Program and Debug \u2192 Open Hardware Manager)<\/li>\n\n\n\n<li>Click <strong>Open Target \u2192 Open New Target<\/strong><\/li>\n\n\n\n<li>In the Hardware Server Settings, select <strong>Local server<\/strong> and click <strong>Next<\/strong><\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"381\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_server-1024x381.png\" alt=\"\" class=\"wp-image-42221\" style=\"aspect-ratio:2.687726787620064;width:759px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_server-1024x381.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_server-300x112.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_server-768x285.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_server.png 1052w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"4\" class=\"wp-block-list\">\n<li>In the Select Hardware Target screen, click <strong>Add Xilinx Virtual Cable (XVC)<\/strong><\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"696\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_target-1024x696.png\" alt=\"\" class=\"wp-image-42222\" style=\"aspect-ratio:1.4712858561663842;width:760px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_target-1024x696.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_target-300x204.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_target-768x522.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_target.png 1052w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"5\" class=\"wp-block-list\">\n<li>Enter the <strong>IP address<\/strong> of the imperix device and port <strong>2542<\/strong> (default XVC port), then click <strong>OK<\/strong><\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"691\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_connect-1024x691.png\" alt=\"\" class=\"wp-image-42223\" style=\"aspect-ratio:1.4819348005178299;width:758px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_connect-1024x691.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_connect-300x202.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_connect-768x518.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_hardware_connect.png 1046w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"6\" class=\"wp-block-list\">\n<li>Click <strong>Next<\/strong> and <strong>Finish<\/strong> to complete the connection. Vivado will detect the debug bridge and ILA core.<\/li>\n<\/ol>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"Loading-the-probes-file\"><span class=\"ez-toc-section\" id=\"Loading-the-probes-file\"><\/span>Loading the probes file<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>After connecting, the ILA appears but shows &#8220;No probes exist&#8221;. The probes file that was generated during bitstream implementation must be loaded.<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>In the Hardware panel, click on <strong>debug_bridge_0<\/strong><\/li>\n\n\n\n<li>In the <strong>Hardware Device Properties<\/strong> panel below, locate the <strong>Probes file<\/strong> field<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"525\" height=\"726\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_debug_bridge_properties.png\" alt=\"\" class=\"wp-image-42226\" style=\"width:319px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_debug_bridge_properties.png 525w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_debug_bridge_properties-217x300.png 217w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"3\" class=\"wp-block-list\">\n<li>Click the <strong>&#8230;<\/strong> button and navigate to the Vivado project folder <code>vivado\/&lt;PROJECT_NAME&gt;\/&lt;PROJECT_NAME&gt;.runs\/impl_1\/<\/code><\/li>\n\n\n\n<li>Select the <strong>top_wrapper.ltx<\/strong> file (or similar <code>.ltx<\/code> file) and click <strong>OK<\/strong><\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"877\" height=\"370\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_load_ltx.png\" alt=\"\" class=\"wp-image-42227\" style=\"aspect-ratio:2.3703703703703702;width:636px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_load_ltx.png 877w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_load_ltx-300x127.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_load_ltx-768x324.png 768w\" sizes=\"auto, (max-width: 877px) 100vw, 877px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"5\" class=\"wp-block-list\">\n<li>The probes are now loaded and visible in the waveform viewer<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"840\" height=\"628\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_ila.png\" alt=\"\" class=\"wp-image-42228\" style=\"aspect-ratio:1.337582324198003;width:580px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_ila.png 840w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_ila-300x224.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_probe_ila-768x574.png 768w\" sizes=\"auto, (max-width: 840px) 100vw, 840px\" \/><\/figure>\n<\/div>\n\n\n<h3 class=\"wp-block-heading\" id=\"Operating-the-ILA\"><span class=\"ez-toc-section\" id=\"Operating-the-ILA\"><\/span>Operating the ILA<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p><strong>Immediate trigger<\/strong>: Click the <strong>Run Trigger Immediate<\/strong> button (&gt;&gt;) to capture data immediately without waiting for a trigger condition.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"544\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_simple_capture-1024x544.png\" alt=\"\" class=\"wp-image-42229\" style=\"aspect-ratio:1.882423291101394;width:747px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_simple_capture-1024x544.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_simple_capture-300x159.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_simple_capture-768x408.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_simple_capture-1536x816.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_simple_capture.png 1717w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p><strong>Conditional trigger<\/strong>:<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>In the Trigger Setup window, add the probes to be used as trigger sources<\/li>\n\n\n\n<li>Set the trigger condition (e.g., <code>probe0 == 1<\/code> or <code>probe1 rising edge<\/code>)<\/li>\n\n\n\n<li>Click &#8220;Run Trigger&#8221; (\u25b6 with T) to arm the ILA and wait for the condition<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"545\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_conditionnal_capture-1024x545.png\" alt=\"\" class=\"wp-image-42230\" style=\"aspect-ratio:1.8789823173916287;width:735px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_conditionnal_capture-1024x545.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_conditionnal_capture-300x160.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_conditionnal_capture-768x409.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_conditionnal_capture-1536x818.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/PN129_conditionnal_capture.png 1731w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\" id=\"PN134:GettingstartedwithACGSDKonSimulink-Furtherreadings\"><span class=\"ez-toc-section\" id=\"To-go-further\"><\/span>To go further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The example at the end of <a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a> demonstrates how an ILA can be used to verify a PWM modulator implemented in the FPGA sandbox.<\/p>\n\n\n\n<p>The latest section of the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">FPGA-based control of a grid-tied inverter<\/a> example shows how to use an <em>AXI4-Stream Broadcaster<\/em> to split a stream and route it to the CPU. This allows connecting the result to a probe and observe it from Cockpit, which is sometimes more convenient than using an ILA.<\/p>\n\n\n\n<p><br><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Debugging an FPGA design can be difficult without clear visibility into the high-speed logic fabric, where signals change at nanosecond scales. Xilinx Integrated Logic Analyzer&#8230;<\/p>\n","protected":false},"author":31,"featured_media":40156,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[142],"coauthors":[173],"class_list":["post-40126","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","user-manuals-going-further-with-fpga-programming"],"acf":[],"yoast_head":"<!-- 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