{"id":40131,"date":"2026-01-21T08:28:23","date_gmt":"2026-01-21T08:28:23","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=40131"},"modified":"2026-04-16T09:19:40","modified_gmt":"2026-04-16T09:19:40","slug":"access-the-usr-pins-in-the-fpga-sandbox","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox","title":{"rendered":"Accessing the USR pins in the FPGA sandbox"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\/#Physical-location-of-the-USR-pins\" >Physical location of the USR pins<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\/#Using-the-USR-pins\" >Using the USR pins<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\/#To-go-further\" >To go further<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>Most imperix controllers feature 36 bidirectional 3.3V I\/O lines, commonly known as USR pins. Driven directly from the FPGA, these custom-application I\/Os are ideal for various uses, including communicating with digital encoders, interfacing with additional ADCs, and connecting to other peripheral devices.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Note on FPGA development for imperix controllers<\/strong><br>Customizing the FPGA firmware involves instantiating the <a href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\">imperix firmware IP<\/a> within AMD\/Xilinx Vivado to edit the surrounding programmable logic, known as the sandbox. For step-by-step instructions on creating the required FPGA sandbox template, refer to the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development?currentThread=getting-started-with-fpga-programming\">getting started<\/a>\u00a0guide.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Physical-location-of-the-USR-pins\"><\/span>Physical location of the USR pins<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The following table details the physical locations of USR pins on imperix controllers.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th class=\"has-text-align-left\" data-align=\"left\"><strong>imperix controller<\/strong><\/th><th class=\"has-text-align-left\" data-align=\"left\"><strong>Location of the USR pins<\/strong><\/th><th class=\"has-text-align-left\" data-align=\"left\"><strong>Related datasheet<\/strong>\/page<\/th><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">B-Box 4<\/td><td class=\"has-text-align-left\" data-align=\"left\">VHDCI connector B (*)<\/td><td class=\"has-text-align-left\" data-align=\"left\"><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_4_Datasheet.pdf\">B-Box 4 datasheet<\/a><\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">B-Box RCP 3.0<\/td><td class=\"has-text-align-left\" data-align=\"left\">VHDCI connector B (*)<\/td><td class=\"has-text-align-left\" data-align=\"left\"><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_Datasheet.pdf\">B-Box RCP datasheet<\/a><\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">B-Box Micro<\/td><td class=\"has-text-align-left\" data-align=\"left\">VHDCI connector (*)<\/td><td class=\"has-text-align-left\" data-align=\"left\"><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_micro_Datasheet.pdf\">B-Box Micro datasheet<\/a><\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">B-Board PRO on its Eval-Board<\/td><td class=\"has-text-align-left\" data-align=\"left\">36-pin 2.54 mm header<\/td><td class=\"has-text-align-left\" data-align=\"left\"><a href=\"https:\/\/imperix.com\/doc\/help\/b-board-pro-carrier-board\">Carrier Board description page<\/a><\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">B-Board PRO<\/td><td class=\"has-text-align-left\" data-align=\"left\">JX2 connector<\/td><td class=\"has-text-align-left\" data-align=\"left\"><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Board_Datasheet.pdf\">B-Board PRO datasheet<\/a>&nbsp;<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Programmable inverter (TPI8032)<\/td><td class=\"has-text-align-left\" data-align=\"left\" colspan=\"5\"><em>Not available.<\/em><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>(*) Accessible via a breakout board such as the <a href=\"https:\/\/imperix.com\/products\/control\/accessories\/#adapter_boards\">VHDCI breakout board<\/a>.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Using-the-USR-pins\"><\/span>Using the USR pins<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>There are two specific cases where the USR pins are reserved by the imperix system and remain unavailable for custom applications:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The target is a <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">TPI8032<\/a>.<\/li>\n\n\n\n<li>A <a href=\"https:\/\/imperix.com\/products\/control\/accessories\/#motor-interface\">motor interface<\/a> is connected to the VHDCI connector.<\/li>\n<\/ul>\n\n\n\n<p>If neither of these conditions applies, the default USR interface port can be safely deleted to free up the pins.<\/p>\n\n\n\n<p><strong>Delete the existing USR interface port<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Right-click on the existing USR interface.<\/li>\n\n\n\n<li>Click <strong>Delete<\/strong>.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"793\" height=\"486\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_vivado_delete_external_port-1.png\" alt=\"\" class=\"wp-image-44756\" style=\"aspect-ratio:1.6317221718284307;width:411px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_vivado_delete_external_port-1.png 793w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_vivado_delete_external_port-1-300x184.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_vivado_delete_external_port-1-768x471.png 768w\" sizes=\"auto, (max-width: 793px) 100vw, 793px\" \/><figcaption class=\"wp-element-caption\">Delete the existing USR interface port<\/figcaption><\/figure>\n<\/div>\n\n\n<p><strong>Create new interface ports<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Right-click, then <strong>Create Port&#8230;<\/strong><\/li>\n\n\n\n<li>Give it a <strong>name<\/strong>, select a <strong>direction<\/strong>, and click <strong>OK<\/strong>.<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image\"><a class=\"firelight-lightbox fancybox image\" href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2023\/03\/image-1-1024x372.png\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"372\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2023\/03\/image-1-1024x372.png\" alt=\"\" class=\"wp-image-14478\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2023\/03\/image-1-1024x372.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2023\/03\/image-1-300x109.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2023\/03\/image-1-768x279.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2023\/03\/image-1.png 1218w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><figcaption class=\"wp-element-caption\">Create new interface ports<\/figcaption><\/figure>\n\n\n\n<p><strong>Edit the constraints<\/strong><\/p>\n\n\n\n<p>The&nbsp;<code>constraints\\sandbox_pins.xdc<\/code>&nbsp;must be edited accordingly. As shown below, we recommend commenting (#) the unused pins to avoid generated unnecessary warning the Vivado. For more information on constraints in Xilinx FPGA please refer to the&nbsp;<a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2021_1\/ug903-vivado-using-constraints.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">using constraints in Vivado Design Suite<\/a>&nbsp;user guide.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter\"><a class=\"firelight-lightbox fancybox image\" href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2022\/04\/image-38.png\"><img decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2022\/04\/image-38.png\" alt=\"\"\/><\/a><figcaption class=\"wp-element-caption\">Edit the constraints<\/figcaption><\/figure>\n<\/div>\n\n\n<p><strong>Update the block design wrapper<\/strong><\/p>\n\n\n\n<p>Whenever top level ports are modified, it is required to updated the block design wrapper to reflect the changes. The recommended procedure is the following:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Remove the existing wrapper by right-clicking on <strong>top_wrapper<\/strong> and select <strong>Remove File from Project<\/strong>.<\/li>\n\n\n\n<li>Check the <strong>Also delete the project file from disk<\/strong> option, then <strong>OK<\/strong>.<\/li>\n\n\n\n<li>In the <strong>Design sources<\/strong> of the <strong>Sources<\/strong> panel on the left, right-click on <strong>top (top.bd)<\/strong> and select <strong>Create HDL wrapper<\/strong>.<\/li>\n\n\n\n<li>Check <strong>Copy generated wrapper to allow user edits<\/strong>. Press <strong>OK<\/strong>.<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"459\" height=\"309\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_remove_top_level_wrapper.png\" alt=\"\" class=\"wp-image-44778\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_remove_top_level_wrapper.png 459w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_remove_top_level_wrapper-300x202.png 300w\" sizes=\"auto, (max-width: 459px) 100vw, 459px\" \/><figcaption class=\"wp-element-caption\">Delete the outdated HDL wrapper<\/figcaption><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"429\" height=\"295\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_create_top_level_wrapper.png\" alt=\"\" class=\"wp-image-44779\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_create_top_level_wrapper.png 429w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn179_create_top_level_wrapper-300x206.png 300w\" sizes=\"auto, (max-width: 429px) 100vw, 429px\" \/><figcaption class=\"wp-element-caption\">Re-create an up-to-date HDL wrapper<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"To-go-further\"><\/span>To go further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The following application notes illustrate practical uses of the 3.3V USR pins for communicating with external peripherals:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-spi-communication-ip\">TN130<\/a>: SPI communication with an <strong>LTC2314<\/strong> ADC chip<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-delta-sigma-modulator\">TN149<\/a>: decoding Delta-Sigma modulation from an <strong>AMC1035<\/strong> ADC<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Most imperix controllers feature 36 bidirectional 3.3V I\/O lines, commonly known as USR pins. Driven directly from the FPGA, these custom-application I\/Os are ideal for&#8230;<\/p>\n","protected":false},"author":17,"featured_media":2995,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,92,166,110],"guidedreadings":[],"tutorials":[],"user-manuals":[142],"coauthors":[82],"class_list":["post-40131","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","user-manuals-going-further-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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