{"id":40524,"date":"2026-02-02T13:28:57","date_gmt":"2026-02-02T13:28:57","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=40524"},"modified":"2026-02-02T12:00:00","modified_gmt":"2026-02-02T12:00:00","slug":"sfp-communication-with-third-party-devices","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices","title":{"rendered":"SFP communication with third-party devices"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#SFP-Aurora-and-imperix\" >SFP, Aurora, and imperix<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#Setup-overview\" >Setup overview<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#Supported-devices\" >Supported devices<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#User-application-template\" >User application template<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#Bitstream-generation\" >Bitstream generation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#Startup-procedure\" >Startup procedure<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#Address-mapping\" >Address mapping<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#To-go-further\" >To go further<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#How-to-exchange-more-signals\" >How to exchange more signals<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\/#How-to-assign-a-different-SFP-port\" >How to assign a different SFP port<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n\n<p class=\"wp-block-paragraph\">Imperix controllers typically have their CPU programmed from Simulink or PLECS. Additionally, the controllers also offer user-programmable FPGA resources in a dedicated area called <em>Sandbox<\/em>. <\/p>\n\n\n\n<p class=\"wp-block-paragraph\">In this context, users can also access the multi-gigabit transceivers connected to the devices&#8217; SFP+  sockets. This enables a wide range of applications, including communication with major HIL simulator vendors such as <strong>OPAL-RT<\/strong>, <strong>Plexim<\/strong>, <strong>Typhoon HIL<\/strong>, and <strong>RTDS<\/strong>, over the widely used Xilinx\/AMD Aurora protocol.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">This page explains how to set up such communication by combining a user application running on the CPU with additional logic in the FPGA sandbox. For quick integration, a ready-to-use user template is also provided, along with generation scripts to easily generate bitstreams for several vendors.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">This page applies to the following imperix controllers: <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box 3 (RCP)<\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board 3 (PRO)<\/a>, <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">Programmable Inverter (TPI8032)<\/a>. The same approach also applies to the <a href=\"https:\/\/imperix.com\/products\/control\/rcp-controller\/\">B-Box 4<\/a> &#8211; then over QSFP+ sockets &#8211; with minor adaptations.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"SFP-Aurora-and-imperix\"><\/span>SFP, Aurora, and imperix<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">With three Small Form-factor Pluggable (SFP) ports, the imperix controllers are naturally built for multi-device topologies, such as wide multi-master and master-slave <a href=\"https:\/\/imperix.com\/technology\/low-latency-communication\/\">RealSync<\/a> networks.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">To fully leverage these high-speed SFP connections, Xilinx&#8217;s&nbsp;Aurora protocol&nbsp;provides a lightweight, high-throughput option. By using native transceivers with minimal overhead, Aurora delivers low latency and near line-rate performance without the complexity of protocols like Ethernet, making it an efficient and practical choice for high-bandwidth, point-to-point links.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Although simple, Aurora requires identical configurations at both ends of the link. This usually makes interoperability between devices from different vendors challenging.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Through the sandbox, its FPGA development environment, imperix provides unrestricted access to the SFP ports of its controllers. This allows instantiating a configurable Aurora IP and implementing the logic needed to match the configuration and frame structure of any third-party manufacturer.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">For a quick start, synthesis-ready Vivado projects are provided for several vendors including OPAL-RT, Plexim, Typhoon, and RTDS. These projects implement the FPGA logic depicted in the next section, including an Aurora IP with the same configuration as the targeted third-party simulator, a driver to encode and decode the Aurora frames, and SBI\/SBO registers to exchange data with the user application running in the CPU.<\/p>\n\n\n\n<h2 id=\"setup-overview\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Setup-overview\"><\/span>Setup overview<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The setup for exchanging data with a third-party device is depicted below. It is composed of three main parts: the <strong>user application<\/strong>, the <strong>FPGA bitstream<\/strong>, and the <strong>third-party application<\/strong>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"482\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/03\/pn112_driver_communication_chain_4-1024x482.png\" alt=\"\" class=\"wp-image-43922\" style=\"aspect-ratio:2.1201330134276213;width:470px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/03\/pn112_driver_communication_chain_4-1024x482.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/03\/pn112_driver_communication_chain_4-300x141.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/03\/pn112_driver_communication_chain_4-768x362.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/03\/pn112_driver_communication_chain_4-1536x724.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/03\/pn112_driver_communication_chain_4-2048x965.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">The <strong>user application<\/strong> runs on the CPU of the imperix controller and contains user-designed code, typically a control algorithm. This application has no special requirements, except that it contains <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> blocks to send data to the driver and <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> blocks to access incoming data from the SFP connection.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The <strong>FPGA bitstream<\/strong> defines the logic executed on the imperix controller\u2019s FPGA. Together with the controller firmware, it implements the functionality required for Aurora communication. The core components of this communication are the <strong>driver<\/strong>, <strong>FIFOs,<\/strong> and the Xilinx <strong>Aurora IP<\/strong>:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>driver<\/strong> receives the outgoing data from the user application through the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> blocks, packages it into frames compatible with the third-party simulator, and transfers the frames to the Aurora IP. In parallel, it receives incoming frames from the Aurora IP, decodes them, and makes the values available to the user application via <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> blocks.<\/li>\n\n\n\n<li>The <strong>FIFOs<\/strong> are essential for clock-domain crossing. They bridge the main clock domain of imperix controllers, running at 250 MHz, to the clock domain of the Aurora IP. The Aurora IP frequency depends on the Aurora channel configuration and therefore differs by vendor.<\/li>\n\n\n\n<li>The <strong>Aurora IP<\/strong> is provided by Xilinx. As explained on the <a href=\"https:\/\/www.amd.com\/en\/products\/adaptive-socs-and-fpgas\/intellectual-property\/aurora8b10b.html\">presentation page<\/a>, the IP enables easy transceiver implementation and provides a lightweight user interface on top of which designers can build a serial link.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">Because major market vendors use different Aurora channel configurations and, in some cases, specific frame structures, the bitstream is <strong>vendor-specific<\/strong> and must be generated using the corresponding generation scripts.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Finally, the <strong>third-party application<\/strong> runs on a third-party device and is not directly related to imperix products. In this example, the application must enable Aurora communication on an SFP port of the third-party simulator.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">More information about CPU-FPGA communication over the SBIO bus is available <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development#SBIO_BUS\">here<\/a>.<\/div>\n\n\n\n<h2 id=\"supported-devices\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Supported-devices\"><\/span>Supported devices<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The supported devices are listed below. Devices marked in <strong>bold<\/strong> have been expressly tested and validated.<\/p>\n\n\n\n<figure id=\"supported-devices-projects-table\" class=\"wp-block-table\"><table><tbody><tr><th><strong>Vendor<\/strong><\/th><th><strong>Compatible devices<\/strong><\/th><th>Related page(s)<\/th><\/tr><tr><td>OPAL-RT<\/td><td><strong>OP4510<\/strong>, OP4512<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-opal-rt-via-sfp\">Aurora link with OPAL-RT via SFP<\/a><\/td><\/tr><tr><td>Plexim<\/td><td><strong>RT-Box 1<\/strong>, RT-Box 2, RT-Box 3<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-plexim-via-sfp\">Aurora link with Plexim via SFP<\/a><\/td><\/tr><tr><td>Typhoon<\/td><td>HIL101, HIL404, <strong>HIL506<\/strong>, HIL606<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/aurora-link-with-typhoon-via-sfp\">Aurora link with Typhoon via SFP<\/a><\/td><\/tr><tr><td>RTDS<\/td><td><strong>GTSOC V2<\/strong><\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-an-rtds-mmc-simulator\">SFP communication with an RTDS MMC simulator<\/a> (*)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\"><em>(*) <\/em>The communication chain, driver, and address mapping implemented on this page are very specific in order to match the frame structure expected by the MMC model running on the GTSOC V2.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"207\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_third_parties-1024x207.png\" alt=\"\" class=\"wp-image-40623\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_third_parties-1024x207.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_third_parties-300x61.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_third_parties-768x156.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_third_parties-1536x311.png 1536w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_third_parties.png 1679w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">The following table summarizes the Aurora configuration applied by each vendor.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th><strong>Vendor<\/strong><\/th><th><strong>Aurora protocol<\/strong><\/th><th><strong>Line rate (Gbps)<\/strong><\/th><th><strong>Endianness<\/strong><\/th><th><strong>CRC check<\/strong><\/th><th><strong>Frame structure<\/strong><\/th><\/tr><tr><td>OPAL-RT<\/td><td>Aurora 8B10B<\/td><td>5<\/td><td>Little<\/td><td>Yes<\/td><td>&#8211;<\/td><\/tr><tr><td>Plexim<\/td><td>Aurora 64B66B<\/td><td>6.25<\/td><td>Big<\/td><td>Yes<\/td><td>Custom<\/td><\/tr><tr><td>Typhoon<\/td><td>Aurora 8B10B<\/td><td>5<\/td><td>Big<\/td><td>No<\/td><td>&#8211;<\/td><\/tr><tr><td>RTDS<\/td><td>Aurora 8B10B<\/td><td>2<\/td><td>Little<\/td><td>No<\/td><td>Custom<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 id=\"user-application-template\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"User-application-template\"><\/span>User application template<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">As mentioned, the user application has no special requirements, except that it contains <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> and <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> blocks to communicate with the driver running in the FPGA.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">For a quick start, a user application template, either in Simulink or PLECS, that sends and receives three signals via SFP is provided below:<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/aurora_ix_template.slx\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>aurora_ix_template.slx<\/strong><\/a><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/aurora_ix_template.plecs\" class=\"wp-block-file__button wp-element-button\" download>Download <strong>aurora_ix_template.plecs<\/strong><\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\" id=\"user-application-template-simulink-plecs-screenshots\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"436\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_simulink-1024x436.png\" alt=\"User application in Simulink for the SFP communication with third-party simulators.\" class=\"wp-image-40606\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_simulink-1024x436.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_simulink-300x128.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_simulink-768x327.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_simulink.png 1233w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"922\" height=\"478\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_plecs.png\" alt=\"\" class=\"wp-image-41118\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_plecs.png 922w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_plecs-300x156.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_user_application_plecs-768x398.png 768w\" sizes=\"auto, (max-width: 922px) 100vw, 922px\" \/><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p class=\"wp-block-paragraph\">The <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development#SBIO_BUS\">SBIO bus<\/a> handles communication between the CPU and the FPGA. Thanks to the related <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> and <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> blocks, the CPU generates read and write requests on the SBIO bus and interacts with the registers located in the FPGA.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Because the SBIO bus carries 16-bit data, the 32-bit values are split into two 16-bit words for transfer over the bus. The single2sbo&nbsp;and&nbsp;sbi2single&nbsp;Matlab\/C-Script functions handle the conversion.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The address mapping is detailed in the <a href=\"#address-mapping\">dedicated section<\/a> below.<\/div>\n\n\n\n<p class=\"wp-block-paragraph\">To build the user application, make sure that the <strong>Automated Code Generation<\/strong> mode is selected in the <strong>CONFIG<\/strong> block and press <code>Ctrl+B<\/code> (Simulink) or <code>Ctrl+Alt+B<\/code> and then <strong>Build <\/strong>(PLECS).<\/p>\n\n\n\n<h2 id=\"generate-the-bitstream\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Bitstream-generation\"><\/span>Bitstream generation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">To generate the bitstream running in the imperix controller, please follow the steps outlined below:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Install the <strong>Vivado Design Suite<\/strong>. Version <strong>2023.2<\/strong> is recommended, except for the Plexim Gen 4 scripts, which require version 2024.1. The step-by-step installation procedure is detailed in <a href=\"https:\/\/imperix.com\/doc\/help\/vivado-design-suite-installation?currentThread=getting-started-with-fpga-programming\">Installation of AMD Xilinx Vivado Design Suite<\/a>.<\/li>\n\n\n\n<li>Download the <strong>imperix source files<\/strong> (version <strong>3.10 Rev. 0 or later<\/strong> is mandatory). The source files are available for free at <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox?currentThread=getting-started-with-fpga-programming\">Download of the imperix firmware IP for FPGA sandbox<\/a>.<\/li>\n\n\n\n<li>Download the generation scripts for the targeted vendor in the table below, then follow <a type=\"link\" href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox#starting-from-generation-scripts\" id=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox#starting-from-generation-scripts\">this procedure<\/a> to generate the bitstream from the scripts.<\/li>\n<\/ol>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td><strong>Vendor<\/strong><\/td><td><strong>Compatible devices<\/strong><\/td><td><strong>Generation scripts<\/strong><\/td><\/tr><tr><td>OPAL-RT<\/td><td>OP4510, OP4512<\/td><td><strong><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_opalrt_gen3_scripts.zip\">aurora_ix_opalrt_gen3_scripts.zip<\/a><\/strong><br><strong><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_opalrt_gen4_scripts.zip\" data-type=\"link\" data-id=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_opalrt_gen4_scripts.zip\">aurora_ix_opalrt_gen4_scripts.zip<\/a><\/strong><\/td><\/tr><tr><td>Plexim<\/td><td>RT-Box 1, RT-Box 2, RT-Box 3<\/td><td><strong><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_plexim_gen3_scripts.zip\" data-type=\"link\" data-id=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_plexim_gen3_scripts.zip\">aurora_ix_plexim_gen3_scripts.zip<\/a><\/strong><br><strong><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_plexim_gen4_scripts.zip\">aurora_ix_plexim_gen4_scripts.zip<\/a><\/strong> (*)<\/td><\/tr><tr><td>Typhoon<\/td><td>HIL101, HIL404, HIL506, HIL606<\/td><td><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_typhoon_gen3_scripts.zip\"><strong>aurora_ix_typhoon_gen3_scripts.zip<\/strong><\/a><br><a href=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/02\/aurora_ix_typhoon_gen4_scripts.zip\"><strong>aurora_ix_typhoon_gen4_scripts.zip<\/strong><\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">(*) <strong>Important<\/strong>: Plexim Gen 4 scripts are only compatible with <strong>Vivado 2024.1<\/strong>.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The provided FPGA logic connects to\u00a0SFP 0 (UP)\u00a0and supports\u00a0<strong>up to 32 signals<\/strong> in each direction. To extend the number of signals or assign another SFP port, refer to the <a href=\"#how-to-exchange-more-signals\">How to exchange more signals<\/a> and <a href=\"#how-to-assign-a-different-sfp-port\">How to assign a different SFP port<\/a> sections below.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Startup-procedure\"><\/span>Startup procedure<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">To start using the setup and exchange data with the third-party device:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Connect the imperix controller to the third-party simulator with an SFP cable. By default, the Aurora communication is connected to the SFP 0 (UP) port on the controller.<\/li>\n\n\n\n<li>Generate the bitstream, as explained in the <a href=\"#generate-the-bitstream\">dedicated section<\/a> above.<\/li>\n\n\n\n<li>Load the bitstream on the imperix controller via Cockpit.<\/li>\n\n\n\n<li>Download the <a href=\"#user-application-template\">user application template<\/a> in Simulink or PLECS (or use your own model). If you use your own model, add&nbsp;probes&nbsp;to the exchanged signals as in the provided user application.<\/li>\n\n\n\n<li>Build the model and launch it on the imperix controller via Cockpit.<\/li>\n\n\n\n<li>Compile\/build the code for the third-party simulator and launch it.<br>Applications are provided for several vendors in the pages listed in the <a href=\"#supported-devices\">Supported devices<\/a> section above. Refer to the vendor&#8217;s documentation for advanced guidance and details.<\/li>\n\n\n\n<li>Use Cockpit to monitor the exchanged signals.<\/li>\n<\/ol>\n\n\n\n<h2 id=\"address-mapping\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Address-mapping\"><\/span>Address mapping<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">As introduced in the <a href=\"#setup-overview\">setup overview<\/a>, the internal CPU-FPGA communication in imperix controllers is managed by the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development#SBIO_BUS\">SBIO bus<\/a>.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Because they correspond to 16-bit words, SBI and SBO addresses are grouped in pairs to transfer 32-bit payload words, starting at address 0. For instance, the first word to be transmitted must be written in SBO 1 (MSB) and SBO 0 (LSB), and the first word received from the simulator is available in SBI 1 (MSB) and SBI 0 (LSB).<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">SBO 255 specifies the number of signals to transmit to the third-party device. Similarly, SBI 255 contains the number of received signals.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th class=\"has-text-align-center\" data-align=\"center\" colspan=\"2\"><strong>SBO address<\/strong><\/th><th class=\"has-text-align-center\" data-align=\"center\"><strong>Transmitted signals<\/strong><br>(tx payload)<\/th><th class=\"has-text-align-center\" data-align=\"center\" colspan=\"2\"><strong>SBI address<\/strong><\/th><th class=\"has-text-align-center\" data-align=\"center\"><strong>Received signals<\/strong><br>(rx payload)<\/th><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">1<\/td><td class=\"has-text-align-center\" data-align=\"center\">0<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>tx_signal_00<\/code><\/td><td class=\"has-text-align-center\" data-align=\"center\">1<\/td><td class=\"has-text-align-center\" data-align=\"center\">0<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>rx_signal_00<\/code><\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">3<\/td><td class=\"has-text-align-center\" data-align=\"center\">2<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>tx_signal_01<\/code><\/td><td class=\"has-text-align-center\" data-align=\"center\">3<\/td><td class=\"has-text-align-center\" data-align=\"center\">2<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>rx_signal_01<\/code><\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"3\">\u2026<\/td><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"3\">\u2026<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">63<\/td><td class=\"has-text-align-center\" data-align=\"center\">62<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>tx_signal_31<\/code><\/td><td class=\"has-text-align-center\" data-align=\"center\">63<\/td><td class=\"has-text-align-center\" data-align=\"center\">62<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>rx_signal_31<\/code><\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"3\">(free for extension)<\/td><td class=\"has-text-align-center\" data-align=\"center\" colspan=\"3\">(free for extension)<\/td><\/tr><tr><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">255<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>n_tx_signals<\/code><\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">255<\/td><td class=\"has-text-align-center\" data-align=\"center\"><code>n_rx_signals<\/code><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"To-go-further\"><\/span>To go further<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 id=\"how-to-exchange-more-signals\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How-to-exchange-more-signals\"><\/span>How to exchange more signals<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The current implementation supports exchanging 32 signals in each direction. This section describes how to extend the number of signals.<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li><strong>Change the number of ports of the provided VHDL driver<\/strong>.<br>The driver is located in <code>&lt;folder&gt;\/hdl\/sfp_aurora_rtbox.vhd<\/code> and the instructions are clearly indicated at the top of the file. These changes consist of adding more ports, inserting them into the interfaces, and linking their values to the two internal arrays.<\/li>\n\n\n\n<li><strong>Adapt the surrounding modules<\/strong>.<br>Make sure that the surrounding modules support the desired number of signals, namely the <code>sbio_256_registers<\/code>, <code>convert_16b_to_32b<\/code> and <code>convert_32b_to_16b<\/code> modules. Do not forget to extend the length of the axis_data_fifo_0 FIFO.<\/li>\n\n\n\n<li><strong>Regenerate the bitstream<\/strong>.<\/li>\n\n\n\n<li><strong>Adapt the Simulink model<\/strong>.<br>Add the corresponding SBI and SBO blocks in the Simulink model.<\/li>\n\n\n\n<li><strong>Make sure that the third-party device is configured accordingly<\/strong>.<\/li>\n<\/ol>\n\n\n\n<h3 id=\"how-to-assign-a-different-sfp-port\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How-to-assign-a-different-SFP-port\"><\/span>How to assign a different SFP port<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">In the provided implementation, the communication with the RT-Box is configured on the SFP port 0 (UP). To assign the SFP communication to another SFP port (e.g., SFP 1 (DOWN0)):<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li><strong>Open the Vivado project<\/strong>.<\/li>\n\n\n\n<li><strong>Change the enabled SFP port.<\/strong><br>Double-click on the IX IP block in the block diagram to open the configuration panel. In the&nbsp;Using SFP from sandbox&nbsp;tab, select the desired SFP port and uncheck&nbsp;SFP 0. This will re-enable RealSync on port 0 (UP)and disable it on the selected port, removing the txn_0, txp_0, rxn_0, rxp_0 ports of the imperix firmware IP and exposing the ports of the selected SFP port instead.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"876\" height=\"566\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_config_1.png\" alt=\"Vivado screenshot showing how to assign another SFP port for the communication with third-party simulators (1\/2).\" class=\"wp-image-40699\" style=\"aspect-ratio:1.5477368404879697;width:587px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_config_1.png 876w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_config_1-300x194.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_config_1-768x496.png 768w\" sizes=\"auto, (max-width: 876px) 100vw, 876px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"3\" class=\"wp-block-list\">\n<li><strong>Connect the ports.<\/strong><br>Connect the four ports exposed during step 3 to the Aurora IP, as illustrated below.<\/li>\n<\/ol>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"948\" height=\"684\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_ixip_sfp_ports_1.png\" alt=\"Vivado screenshot showing how to assign another SFP port for the communication with third-party simulators (2\/2).\" class=\"wp-image-40697\" style=\"aspect-ratio:1.3859827742769875;width:575px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_ixip_sfp_ports_1.png 948w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_ixip_sfp_ports_1-300x216.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2026\/01\/pn109_vivado_ixip_sfp_ports_1-768x554.png 768w\" sizes=\"auto, (max-width: 948px) 100vw, 948px\" \/><\/figure>\n<\/div>\n\n\n<ol start=\"4\" class=\"wp-block-list\">\n<li><strong>Regenerate the bitstream.<\/strong><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"<p>Imperix controllers typically have their CPU programmed from Simulink or PLECS. Additionally, the controllers also offer user-programmable FPGA resources in a dedicated area called Sandbox&#8230;.<\/p>\n","protected":false},"author":17,"featured_media":44904,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,166,110],"guidedreadings":[],"tutorials":[174],"user-manuals":[],"coauthors":[82],"class_list":["post-40524","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-rcp-3-0","related-products-tpi","tutorials-sfp-communication-with-third-party-devices"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.1 - 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