{"id":4212,"date":"2021-07-14T12:33:25","date_gmt":"2021-07-14T12:33:25","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=4212"},"modified":"2025-05-07T13:06:22","modified_gmt":"2025-05-07T13:06:22","slug":"fpga-based-dq-current-control","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control","title":{"rendered":"DQ current control using FPGA-based PI controllers"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\/#Overview-of-the-dq-current-control-module\" >Overview of the dq current control module<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\/#FPGA-based-dq-current-control-using-Model-Composer\" >FPGA-based dq current control using Model Composer<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\/#Testbench-of-the-Model-Composer-implementation\" >Testbench of the Model Composer implementation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\/#FPGA-based-dq-current-control-using-Xilinx-Vitis-HLS\" >FPGA-based dq current control using Xilinx Vitis HLS<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\/#Testbench-of-the-Vitis-HLS-implementation\" >Testbench of the Vitis HLS implementation<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\/#Testbench-results\" >Testbench results<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-dq-current-control\/#Further-readings\" >Further readings<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>Control algorithms for power electronics converters often rely on PI controllers executed on the CPU of the controller. That&#8217;s the technique used in most of the application notes on this knowledge. However, in some situations, it could be desired to run the control loop on an FPGA (e.g. to offload the CPU, or achieve much faster control rates). In that case, it is required to develop an FPGA-based PI controller.<\/p>\n\n\n\n<p>The implementation of an <strong>FPGA-based PI controller<\/strong> is given as an example in the introductory notes to <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a> and <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a>. These are the two recommended approaches to develop FPGA-based control routines. In most realizations, however, the control of three-phase AC variables requires two PI controllers running in a synchronous reference frame (dq), as introduced in the note about <a href=\"https:\/\/imperix.com\/doc\/implementation\/vector-current-control\">CPU-based vector current control<\/a>.<\/p>\n\n\n\n<p>This page gives an example of an<strong> FPGA-based dq PI controller for current control of a grid-tied three-phase inverter<\/strong> using both <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a> and <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a> approaches. Testbenches are also presented and help to validate that the implemented code or model behaves as expected, before even executing it on a real-time controller.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">For traditional CPU-based dq current control, please refer to <a href=\"https:\/\/imperix.com\/doc\/implementation\/vector-current-control\">vector current control<\/a>.<br><br>To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-overview-of-the-dq-current-control-module\"><span class=\"ez-toc-section\" id=\"Overview-of-the-dq-current-control-module\"><\/span>Overview of the dq current control module<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The implemented algorithm is a traditional <a href=\"https:\/\/imperix.com\/doc\/implementation\/vector-current-control\">vector (dq) current control<\/a>, including a PI controller on each axis and a decoupling network. The measured grid voltages are feedforwarded right after the current controllers, giving voltage quantities \\(E_{g,dq0}\\) that the converter should generate to induce the desired current. The zero-sequence voltage is here set to zero but can be used for instance for third-harmonic injection, as done in the <a href=\"https:\/\/imperix.com\/doc\/implementation\/svpwm-vs-spwm-modulation-techniques\">TN146<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"283\" height=\"210\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/07\/dq_current_control_v2_100pc.png\" alt=\"Block diagram of traditional dq current control\" class=\"wp-image-10274\"\/><figcaption>Traditional dq current control algorithm<\/figcaption><\/figure><\/div>\n\n\n\n<p>The following sections detail how to pack that algorithm into the FPGA IP shown below, using both High-Level Synthesis tools <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">Vitis HLS<\/a> and <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">Model Composer<\/a>. That IP uses <em>AXI4-Stream<\/em> inputs and outputs to be compatible with other IPs developed on other pages, as well as with <a href=\"https:\/\/imperix.com\/doc\/implementation\/axi4-stream-ip-from-xilinx\">Xilinx IP cores for Vivado<\/a>. In particular, this IP is meant to be connected to the grid synchronization IP developed in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-implementation-pll\">FPGA-based grid synchronization<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dq_current_ctrl.png\" alt=\"Generated FPGA IP implementing the dq current control\" class=\"wp-image-10273\" width=\"310\" height=\"212\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dq_current_ctrl.png 394w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/01\/dq_current_ctrl-300x206.png 300w\" sizes=\"auto, (max-width: 310px) 100vw, 310px\" \/><figcaption>Generated IP implementing the dq current control<\/figcaption><\/figure><\/div>\n\n\n\n<p>Further details on integrating a Vivado IP in the FPGA are presented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">High-Level Synthesis integration into the FPGA<\/a>. A complete converter control algorithm that uses that IP is presented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">FPGA-based converter control<\/a>.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-fpga-based-dq-current-control-using-model-composer\"><span class=\"ez-toc-section\" id=\"FPGA-based-dq-current-control-using-Model-Composer\"><\/span>FPGA-based dq current control using Model Composer<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The Model Composer implementation of the FPGA-based vector current controller is shown below.<\/p>\n\n\n\n<p>For more details on how to generate an IP and how to integrate it to the FPGA of imperix controllers, please refer to the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-model-composer\">introductory note to Model Composer<\/a>.<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/07\/TN144_FPGA_DQ_Current_Control_Model_Composer.zip\" class=\"wp-block-file__button\" download>Download <strong>TN144_FPGA_DQ_Current_Control_Model_Composer.zip<\/strong><\/a><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_dq_current_control.png\" alt=\"\" class=\"wp-image-12215\" width=\"546\" height=\"477\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_dq_current_control.png 610w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_dq_current_control-300x262.png 300w\" sizes=\"auto, (max-width: 546px) 100vw, 546px\" \/><figcaption>Implementation of the FPGA-based PI controller using Model Composer<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/tn144_PI.png\" alt=\"\" class=\"wp-image-12217\" width=\"720\" height=\"324\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/tn144_PI.png 827w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/tn144_PI-300x135.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/tn144_PI-768x346.png 768w\" sizes=\"auto, (max-width: 720px) 100vw, 720px\" \/><figcaption>PI_d and PI_q subsystems<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/tn144_saturation.png\" alt=\"\" class=\"wp-image-12218\" width=\"635\" height=\"266\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/tn144_saturation.png 722w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2022\/05\/tn144_saturation-300x125.png 300w\" sizes=\"auto, (max-width: 635px) 100vw, 635px\" \/><figcaption>saturation subsystem<\/figcaption><\/figure><\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-testbench-of-the-model-composer-implementation\"><span class=\"ez-toc-section\" id=\"Testbench-of-the-Model-Composer-implementation\"><\/span>Testbench of the Model Composer implementation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Model Composer allows the user to test his implementation directly from within Simulink in an offline simulation. For comparison purposes with the Vitis HLS approach, the same inputs as the Vitis testbench are fed to the Model Composer model.<\/p>\n\n\n\n<p>A previously-validated Simulink implementation of the vector current controller serves as a reference for both Vitis HLS and Model Composer testbenches.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_toplvl-775x1024.png\" alt=\"\" class=\"wp-image-12219\" width=\"581\" height=\"768\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_toplvl-775x1024.png 775w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_toplvl-227x300.png 227w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_toplvl-768x1015.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/tn144_toplvl.png 778w\" sizes=\"auto, (max-width: 581px) 100vw, 581px\" \/><figcaption>Simulink testbench with reference model (top) and Model Composer implementation (bottom)<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-272.png\" alt=\"Vector current control implemented in Simulink\" class=\"wp-image-4117\" width=\"575\" height=\"418\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-272.png 767w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-272-300x218.png 300w\" sizes=\"auto, (max-width: 575px) 100vw, 575px\" \/><figcaption>Reference model<\/figcaption><\/figure><\/div>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-273-1024x665.png\" alt=\"FPGA-baed PI controller implementation using Model Composer\" class=\"wp-image-4119\" width=\"578\" height=\"375\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-273-1024x665.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-273-300x195.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-273-768x499.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-273.png 1124w\" sizes=\"auto, (max-width: 578px) 100vw, 578px\" \/><figcaption>Model under test (Model Composer)<\/figcaption><\/figure><\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-fpga-based-dq-current-control-using-xilinx-vitis-hls\"><span class=\"ez-toc-section\" id=\"FPGA-based-dq-current-control-using-Xilinx-Vitis-HLS\"><\/span>FPGA-based dq current control using Xilinx Vitis HLS<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The complete Vitis HLS sources of the FPGA-based vector current controller can be downloaded below:<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<div class=\"wp-block-file aligncenter\"><a href=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/07\/TN144_FPGA_DQ_Current_Control_Vitis_HLS.zip\" class=\"wp-block-file__button\" download>Download <strong>TN144_FPGA_DQ_Current_Control_Vitis_HLS.zip<\/strong><\/a><\/div>\n\n\n\n<p>Below is the C++ code of the algorithm used in this example, for reference. From there, this code can be used to generate an IP and integrate it into the FPGA of an imperix controller, following the instructions of the <a href=\"https:\/\/imperix.com\/doc\/help\/xilinx-vitis-hls\">introductory note to Vitis HLS<\/a>.<br><\/p>\n\n\n<style>.kt-accordion-id_f9bd05-37 .kt-accordion-inner-wrap{column-gap:var(--global-kb-gap-md, 2rem);row-gap:1px;}.kt-accordion-id_f9bd05-37 .kt-accordion-panel-inner{border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;padding-top:20px;padding-right:20px;padding-bottom:20px;padding-left:20px;}.kt-accordion-id_f9bd05-37 > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > 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.kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active{color:var(--global-palette3, #1A202C);background:var(--global-palette9, #ffffff);border-top-color:var(--global-palette6, #718096);border-right-color:var(--global-palette6, #718096);border-bottom-color:var(--global-palette6, #718096);border-left-color:var(--global-palette6, #718096);}.kt-accordion-id_f9bd05-37:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_f9bd05-37:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id_f9bd05-37:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id_f9bd05-37:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_f9bd05-37:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette9, #ffffff);}@media all and (max-width: 767px){.kt-accordion-id_f9bd05-37 .kt-accordion-inner-wrap{display:block;}.kt-accordion-id_f9bd05-37 .kt-accordion-inner-wrap .kt-accordion-pane:not(:first-child){margin-top:1px;}}<\/style>\n<div class=\"wp-block-kadence-accordion alignnone\"><div class=\"kt-accordion-wrap kt-accordion-wrap kt-accordion-id_f9bd05-37 kt-accordion-has-4-panes kt-active-pane-0 kt-accordion-block kt-pane-header-alignment-left kt-accodion-icon-style-arrow kt-accodion-icon-side-left\" style=\"max-width:none\"><div class=\"kt-accordion-inner-wrap\" data-allow-multiple-open=\"false\" data-start-open=\"none\">\n<div class=\"wp-block-kadence-pane kt-accordion-pane kt-accordion-pane-1 kt-pane_840780-60\"><div class=\"kt-accordion-header-wrap\"><button class=\"kt-blocks-accordion-header kt-acccordion-button-label-show\"><span class=\"kt-blocks-accordion-title-wrap\"><span class=\"kt-blocks-accordion-title\"><strong>Vitis HLS source of the dq current controller<\/strong> (C++)<\/span><\/span><span class=\"kt-blocks-accordion-icon-trigger\"><\/span><\/button><\/div><div class=\"kt-accordion-panel kt-accordion-panel-hidden\"><div class=\"kt-accordion-panel-inner\"><pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"dq_current_ctrl.h\"<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_stream.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdint.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_math.h&gt;<\/span><\/span>\n\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">float<\/span> <span class=\"hljs-title\">saturation<\/span><span class=\"hljs-params\">(<span class=\"hljs-keyword\">float<\/span> in, <span class=\"hljs-keyword\">bool<\/span>&amp; sat)<\/span>\n<\/span>{\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INLINE<\/span>\n\n  <span class=\"hljs-keyword\">if<\/span>(in &gt; MAX_SAT) {\n    sat = <span class=\"hljs-number\">1<\/span>;\n    <span class=\"hljs-keyword\">return<\/span> MAX_SAT;\n  } <span class=\"hljs-keyword\">else<\/span> <span class=\"hljs-keyword\">if<\/span>(in &lt; MIN_SAT) {\n    sat = <span class=\"hljs-number\">1<\/span>;\n    <span class=\"hljs-keyword\">return<\/span> MIN_SAT;\n  } <span class=\"hljs-keyword\">else<\/span> {\n    sat = <span class=\"hljs-number\">0<\/span>;\n    <span class=\"hljs-keyword\">return<\/span> in;\n    }\n}\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">pi_d<\/span><span class=\"hljs-params\">(<span class=\"hljs-keyword\">float<\/span> kp, <span class=\"hljs-keyword\">float<\/span> kiTs, <span class=\"hljs-keyword\">float<\/span> Id, <span class=\"hljs-keyword\">float<\/span> Id_ref, <span class=\"hljs-keyword\">float<\/span>&amp; pi_out_d)<\/span>\n<\/span>{\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INLINE<\/span>\n\n  <span class=\"hljs-keyword\">static<\/span> <span class=\"hljs-keyword\">float<\/span> accum_d = <span class=\"hljs-number\">0<\/span>;\n  <span class=\"hljs-keyword\">static<\/span> <span class=\"hljs-keyword\">bool<\/span> sat_d = <span class=\"hljs-number\">0<\/span>;\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS RESET variable=accum_d<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS RESET variable=sat_d<\/span>\n\n  <span class=\"hljs-keyword\">float<\/span> err_d,P_d,I_d,next_out_d;\n  <span class=\"hljs-keyword\">bool<\/span> clamp_d;\n\n  err_d = Id_ref - Id;\n  P_d = kp*err_d;\n  I_d = kiTs*err_d;\n\n  clamp_d = (hls::signbit(accum_d) == hls::signbit(err_d)) &amp; sat_d;\n  <span class=\"hljs-keyword\">if<\/span>(!clamp_d) {\n    accum_d += I_d;\n  }\n\n  next_out_d = accum_d + P_d;\n  pi_out_d = saturation(next_out_d,sat_d);\n}\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">pi_q<\/span><span class=\"hljs-params\">(<span class=\"hljs-keyword\">float<\/span> kp, <span class=\"hljs-keyword\">float<\/span> kiTs, <span class=\"hljs-keyword\">float<\/span> Iq, <span class=\"hljs-keyword\">float<\/span> Iq_ref, <span class=\"hljs-keyword\">float<\/span>&amp; pi_out_q)<\/span>\n<\/span>{\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INLINE<\/span>\n\n  <span class=\"hljs-keyword\">static<\/span> <span class=\"hljs-keyword\">float<\/span> accum_q = <span class=\"hljs-number\">0<\/span>;\n  <span class=\"hljs-keyword\">static<\/span> <span class=\"hljs-keyword\">bool<\/span> sat_q = <span class=\"hljs-number\">0<\/span>;\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS RESET variable=accum_q<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS RESET variable=sat_q<\/span>\n\n  <span class=\"hljs-keyword\">float<\/span> err_q = Iq_ref - Iq;\n  <span class=\"hljs-keyword\">float<\/span> P_q = kp*err_q;\n  <span class=\"hljs-keyword\">float<\/span> I_q = kiTs*err_q;\n\n  <span class=\"hljs-keyword\">bool<\/span> clamp_q = (hls::signbit(accum_q) == hls::signbit(err_q)) &amp; sat_q;\n  <span class=\"hljs-keyword\">if<\/span>(!clamp_q) {\n    accum_q += I_q;\n  }\n\n  <span class=\"hljs-keyword\">float<\/span> next_out_q = accum_q + P_q;\n  pi_out_q = saturation(next_out_q,sat_q);\n}\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">void<\/span> <span class=\"hljs-title\">vitis_dq_current_ctrl<\/span><span class=\"hljs-params\">(\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Id_ref,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Iq_ref,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Id,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Iq,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Ud,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_Uq,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_kp,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; in_kiTs,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; out_Ed_ref,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; out_Eq_ref,\n  hls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt;&amp; out_E0_ref)<\/span>\n<\/span>{\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Id_ref<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Iq_ref<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Id<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Iq<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Ud<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_Uq<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_kp<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=in_kiTs<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=out_Ed_ref<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=out_Eq_ref<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS INTERFACE axis port=out_E0_ref<\/span>\n  <span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">pragma<\/span> HLS interface ap_ctrl_none port=return<\/span>\n\n  <span class=\"hljs-keyword\">float<\/span> Id_ref = in_Id_ref.read();\n  <span class=\"hljs-keyword\">float<\/span> Iq_ref = in_Iq_ref.read();\n  <span class=\"hljs-keyword\">float<\/span> Id = in_Id.read();\n  <span class=\"hljs-keyword\">float<\/span> Iq = in_Iq.read();\n  <span class=\"hljs-keyword\">float<\/span> Ud = in_Ud.read();\n  <span class=\"hljs-keyword\">float<\/span> Uq = in_Uq.read();\n  <span class=\"hljs-keyword\">float<\/span> kp = in_kp.read();\n  <span class=\"hljs-keyword\">float<\/span> kiTs = in_kiTs.read();\n\n  <span class=\"hljs-keyword\">float<\/span> pi_out_d, pi_out_q,Ed_ref,Eq_ref,E0_ref;\n\n  pi_d(kp, kiTs, Id, Id_ref, pi_out_d);\n  pi_q(kp, kiTs, Iq, Iq_ref, pi_out_q);\n\n  Ed_ref = -Iq*wL + Ud + pi_out_d;\n  Eq_ref = Id*wL + Uq + pi_out_q;\n  E0_ref = <span class=\"hljs-number\">0<\/span>;\n\n  out_Ed_ref.write(Ed_ref);\n  out_Eq_ref.write(Eq_ref);\n  out_E0_ref.write(E0_ref);\n}\n<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre><\/div><\/div><\/div>\n<\/div><\/div><\/div>\n\n\n\n<p>Note that the integrators are represented as accumulators, using static variables. The directive <code>#pragma HLS RESET<\/code> is used to control the reset of integrators (e.g. when the control is not active, the integrator should be kept at reset). Since the polarity of the reset signal will be automatically set to active low when using AXI4, it is not necessary to specify it explicitly.<\/p>\n\n\n\n<p>Note also that in the codes above, the integral gain is \\(K_{i}T_{s} \\) instead of \\(K_{i} \\), which means that in the Vivado project, a floating-point multiplier is needed to compute \\(K_{i}\\cdot T_{s} \\) before this module. The reason to do this is not technical, but just to be consistent with the Model Composer implementation (see below), which is limited to 8 input\/output ports.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-testbench-of-the-vitis-hls-implementation\"><span class=\"ez-toc-section\" id=\"Testbench-of-the-Vitis-HLS-implementation\"><\/span>Testbench of the Vitis HLS implementation<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>Simulating the closed-loop control behavior of the developed current controller in Vitis HLS is uneasy since it would require a model of the control process (i.e. model of the PWM modulators, of the power converter, and of the acquisition of the measurements). Instead, we can run the Vitis HLS controller using the same input signals as an already-validated Simulink model, and validate the implementation by comparing the results.<\/p>\n\n\n\n<p>The input signals of this testbench are the following two sine signals (the other inputs are kept constant for simplification):<\/p>\n\n\n\n<p>$$ \\begin{aligned} &amp;I_{d}=5\\sin(100\\pi \\cdot nT_{s}) \\\\ &amp;I_{q}=5\\sin(100\\pi \\cdot nT_{s}+\\frac{\\pi}{2}) \\\\ &amp;n=0,1,2,\u2026,999 \\\\ &amp;T_s=5\\times 10^{-5} \\end{aligned} $$<\/p>\n\n\n\n<p>The simulation results are stored in a CSV file and plotted with MATLAB on top of the results of the Simulink (and Model Composer) models for comparison. The comparison is done at the bottom of this page.<\/p>\n\n\n\n<p>The testbench is executed using the following code:<br><\/p>\n\n\n<style>.kt-accordion-id_06db77-e5 .kt-accordion-inner-wrap{column-gap:var(--global-kb-gap-md, 2rem);row-gap:1px;}.kt-accordion-id_06db77-e5 .kt-accordion-panel-inner{border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;padding-top:20px;padding-right:20px;padding-bottom:20px;padding-left:20px;}.kt-accordion-id_06db77-e5 > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header{border-top-color:#f2f2f2;border-right-color:#f2f2f2;border-bottom-color:#f2f2f2;border-left-color:#f2f2f2;border-top-width:2px;border-right-width:2px;border-bottom-width:2px;border-left-width:2px;border-top-left-radius:2px;border-top-right-radius:2px;border-bottom-right-radius:2px;border-bottom-left-radius:2px;background:#ffffff;font-size:16px;line-height:24px;letter-spacing:0px;font-weight:bold;text-transform:none;color:var(--global-palette3, #1A202C);padding-top:12px;padding-right:10px;padding-bottom:8px;padding-left:16px;}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle )  > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id_06db77-e5 > .kt-accordion-inner-wrap > .wp-block-kadence-pane > .kt-accordion-header-wrap > .kt-blocks-accordion-header:hover, \n\t\t\t\tbody:not(.hide-focus-outline) .kt-accordion-id_06db77-e5 .kt-blocks-accordion-header:focus-visible{color:#444444;background:#ffffff;border-top-color:#eeeeee;border-right-color:#eeeeee;border-bottom-color:#eeeeee;border-left-color:#eeeeee;}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion--visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basiccircle ):not( .kt-accodion-icon-style-xclosecircle ):not( .kt-accodion-icon-style-arrowcircle ) .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#444444;}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger, body:not(.hide-focus-outline) .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger{background:#444444;}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:hover .kt-blocks-accordion-icon-trigger:before, body:not(.hide-focus-outline) .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:after, body:not(.hide-focus-outline) .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible .kt-blocks-accordion-icon-trigger:before{background:#ffffff;}.kt-accordion-id_06db77-e5 .kt-accordion-header-wrap .kt-blocks-accordion-header:focus-visible,\n\t\t\t\t.kt-accordion-id_06db77-e5 > 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.kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette3, #1A202C);}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger{background:var(--global-palette3, #1A202C);}.kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:after, .kt-accordion-id_06db77-e5:not( .kt-accodion-icon-style-basic ):not( .kt-accodion-icon-style-xclose ):not( .kt-accodion-icon-style-arrow ) .kt-blocks-accordion-header.kt-accordion-panel-active .kt-blocks-accordion-icon-trigger:before{background:var(--global-palette9, #ffffff);}@media all and (max-width: 767px){.kt-accordion-id_06db77-e5 .kt-accordion-inner-wrap{display:block;}.kt-accordion-id_06db77-e5 .kt-accordion-inner-wrap .kt-accordion-pane:not(:first-child){margin-top:1px;}}<\/style>\n<div class=\"wp-block-kadence-accordion alignnone\"><div class=\"kt-accordion-wrap kt-accordion-wrap kt-accordion-id_06db77-e5 kt-accordion-has-4-panes kt-active-pane-0 kt-accordion-block kt-pane-header-alignment-left kt-accodion-icon-style-arrow kt-accodion-icon-side-left\" style=\"max-width:none\"><div class=\"kt-accordion-inner-wrap\" data-allow-multiple-open=\"false\" data-start-open=\"none\">\n<div class=\"wp-block-kadence-pane kt-accordion-pane kt-accordion-pane-4 kt-pane_c6858c-21\"><div class=\"kt-accordion-header-wrap\"><button class=\"kt-blocks-accordion-header kt-acccordion-button-label-show\"><span class=\"kt-blocks-accordion-title-wrap\"><span class=\"kt-blocks-accordion-title\"><strong>Vitis HLS dq current controller<\/strong> testbench<\/span><\/span><span class=\"kt-blocks-accordion-icon-trigger\"><\/span><\/button><\/div><div class=\"kt-accordion-panel kt-accordion-panel-hidden\"><div class=\"kt-accordion-panel-inner\"><pre class=\"wp-block-code\" aria-describedby=\"shcb-language-2\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"dq_current_ctrl.h\"<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"ap_fixed.h\"<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">\"math.h\"<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;hls_stream.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdint.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdint.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdio.h&gt;<\/span><\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">include<\/span> <span class=\"hljs-meta-string\">&lt;stdlib.h&gt;<\/span><\/span>\n\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">define<\/span> ITERATIONS 1000<\/span>\n<span class=\"hljs-meta\">#<span class=\"hljs-meta-keyword\">define<\/span> two_pi 6.283185307f<\/span>\n\n<span class=\"hljs-function\"><span class=\"hljs-keyword\">int<\/span> <span class=\"hljs-title\">main<\/span><span class=\"hljs-params\">()<\/span>\n<\/span>{\n\t<span class=\"hljs-comment\">\/* Test signals *\/<\/span>\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_Id_ref;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_Iq_ref;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_Id;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_Iq;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_Ud;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_Uq;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_kp;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_in_kiTs;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_out_Ed_ref;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_out_Eq_ref;\n\thls::stream&lt;<span class=\"hljs-keyword\">float<\/span>&gt; tb_out_E0_ref;\n\n\t<span class=\"hljs-comment\">\/* Test inputs*\/<\/span>\n\t<span class=\"hljs-keyword\">float<\/span> in_Id_ref = <span class=\"hljs-number\">0<\/span>;\n\t<span class=\"hljs-keyword\">float<\/span> in_Iq_ref = <span class=\"hljs-number\">0<\/span>;\n\t<span class=\"hljs-keyword\">float<\/span> in_Id;\n\t<span class=\"hljs-keyword\">float<\/span> in_Iq;\n\t<span class=\"hljs-keyword\">float<\/span> in_Ud = <span class=\"hljs-number\">0<\/span>;\n\t<span class=\"hljs-keyword\">float<\/span> in_Uq = <span class=\"hljs-number\">0<\/span>;\n\t<span class=\"hljs-keyword\">float<\/span> in_kp = <span class=\"hljs-number\">10<\/span>;\n\t<span class=\"hljs-keyword\">float<\/span> in_kiTs = <span class=\"hljs-number\">0.05<\/span>;\n\n\t<span class=\"hljs-keyword\">float<\/span> angle = <span class=\"hljs-number\">0<\/span>;\n\t<span class=\"hljs-keyword\">float<\/span> Ts = <span class=\"hljs-number\">0.00005<\/span>;\t\t<span class=\"hljs-comment\">\/\/ fs = 20kHz<\/span>\n\t<span class=\"hljs-keyword\">float<\/span> wt = two_pi*<span class=\"hljs-number\">50<\/span>*Ts;\t<span class=\"hljs-comment\">\/\/ fgrid = 50Hz<\/span>\n\n\t<span class=\"hljs-comment\">\/* Test outputs *\/<\/span>\n\t<span class=\"hljs-keyword\">float<\/span> out_Ed_ref;\n\t<span class=\"hljs-keyword\">float<\/span> out_Eq_ref;\n\n\t<span class=\"hljs-comment\">\/* Create csv file to store simulation data*\/<\/span>\n\tFILE *outputs;\n\toutputs = fopen (<span class=\"hljs-string\">\"outputs.csv\"<\/span>, <span class=\"hljs-string\">\"w+\"<\/span>);\n\t<span class=\"hljs-built_in\">fprintf<\/span>(outputs,<span class=\"hljs-string\">\"%s\"<\/span>,<span class=\"hljs-string\">\"Ed_ref,Eq_ref\\n\"<\/span>);\n\n\t<span class=\"hljs-comment\">\/* Run model *\/<\/span>\n\t<span class=\"hljs-keyword\">for<\/span> (<span class=\"hljs-keyword\">int<\/span> i = <span class=\"hljs-number\">0<\/span>; i &lt; ITERATIONS; i++)\n\t{\n\t\tangle = remainder((angle+wt),two_pi);\n\t\tin_Id = <span class=\"hljs-number\">5<\/span>*<span class=\"hljs-built_in\">sin<\/span>(angle);\n\t\tin_Iq = <span class=\"hljs-number\">2<\/span>*<span class=\"hljs-built_in\">sin<\/span>(angle+two_pi\/<span class=\"hljs-number\">4<\/span>);\n\n\t\ttb_in_Id_ref.write(in_Id_ref);\n\t\ttb_in_Iq_ref.write(in_Iq_ref);\n\t\ttb_in_Id.write(in_Id);\n\t\ttb_in_Iq.write(in_Iq);\n\t\ttb_in_Ud.write(in_Ud);\n\t\ttb_in_Uq.write(in_Uq);\n\t\ttb_in_kp.write(in_kp);\n\t\ttb_in_kiTs.write(in_kiTs);\n\n\t\tvitis_dq_current_ctrl(tb_in_Id_ref,tb_in_Iq_ref,tb_in_Id,tb_in_Iq,tb_in_Ud,tb_in_Uq,tb_in_kp,tb_in_kiTs,tb_out_Ed_ref,tb_out_Eq_ref,tb_out_E0_ref);\n\n\t\tout_Ed_ref = tb_out_Ed_ref.read();\n\t\tout_Eq_ref = tb_out_Eq_ref.read();\n\n\t\t<span class=\"hljs-built_in\">fprintf<\/span>(outputs,<span class=\"hljs-string\">\"%f,%f %s\"<\/span>,out_Ed_ref,out_Eq_ref,<span class=\"hljs-string\">\"\\n\"<\/span>);\n\t}\n\n\tfclose(outputs);\n\n\t<span class=\"hljs-built_in\">printf<\/span>(<span class=\"hljs-string\">\"------ Test Passed ------\\n\"<\/span>);\n\n\t<span class=\"hljs-comment\">\/* End *\/<\/span>\n\t<span class=\"hljs-keyword\">return<\/span> <span class=\"hljs-number\">0<\/span>;\n}\n<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-2\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre><\/div><\/div><\/div>\n<\/div><\/div><\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-testbench-results\"><span class=\"ez-toc-section\" id=\"Testbench-results\"><\/span>Testbench results<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The graph below shows that all three implementations have the same behavior, which validates that the Vitis HLS and Model Composer implementations are correct.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"300\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/dq_outputs-1.png\" alt=\"Testbench result of FPGA-based PI controller\" class=\"wp-image-3949\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/dq_outputs-1.png 800w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/dq_outputs-1-300x113.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/06\/dq_outputs-1-768x288.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><figcaption>Testbench results with reference model (cpu), Vitis HLS (vitis), and Model Composer (xmc)<\/figcaption><\/figure><\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-further-readings\"><span class=\"ez-toc-section\" id=\"Further-readings\"><\/span>Further readings<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>A similar approach is used in the implementation of a <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-implementation-pll\">grid synchronization module for the FPGA<\/a>. Both these IPs are used in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">FPGA-based converter control<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Control algorithms for power electronics converters often rely on PI controllers executed on the CPU of the controller. That&#8217;s the technique used in most of&#8230;<\/p>\n","protected":false},"author":10,"featured_media":10471,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[4],"tags":[17],"software-environments":[106],"provided-results":[107],"related-products":[31,32,92,166,110],"guidedreadings":[],"tutorials":[129],"user-manuals":[],"coauthors":[72],"class_list":["post-4212","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-implementation","tag-fpga-programming","software-environments-fpga","provided-results-simulation","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-tpi","tutorials-fpga-based-control-of-a-grid-tied-inverter"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - 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