{"id":5313,"date":"2021-08-13T13:31:17","date_gmt":"2021-08-13T13:31:17","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=5313"},"modified":"2025-05-07T13:48:33","modified_gmt":"2025-05-07T13:48:33","slug":"fixed-point-vs-floating-point-in-fpga","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/implementation\/fixed-point-vs-floating-point-in-fpga","title":{"rendered":"Fixed point vs floating point arithmetic in FPGA"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/implementation\/fixed-point-vs-floating-point-in-fpga\/#Integers-and-fixed-point-arithmetic-in-FPGA\" >Integers and fixed-point arithmetic in FPGA<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/implementation\/fixed-point-vs-floating-point-in-fpga\/#Floating-point-arithmetic-in-FPGA\" >Floating-point arithmetic in FPGA<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/implementation\/fixed-point-vs-floating-point-in-fpga\/#How-to-typecast-in-MATLAB-Simulink\" >How to typecast in MATLAB Simulink<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>The choice of <strong>fixed vs floating-point<\/strong> arithmetic for an FPGA algorithm is a decision that has a significant impact on the FPGA resources usage, computation latency, as well as data precision. This page provides a comparison between fixed-point vs floating-point arithmetic and gives advantages and drawbacks for each approach. Then, it shows how to use the typecast MATLAB function in MATLAB Simulink to transform a floating-point value into an integer without changing the underlying bits, which is useful when exchanging data between the CPU and FPGA of an imperix <a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">power converter controller<\/a>.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">To find all FPGA-related notes, you can visit\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a>.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-integers-and-fixed-point-arithmetic-in-fpga\"><span class=\"ez-toc-section\" id=\"Integers-and-fixed-point-arithmetic-in-FPGA\"><\/span>Integers and fixed-point arithmetic in FPGA <span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>A fixed-point number is represented with a fixed number of digits before and after the radix point. In FPGA, a fixed-point number is stored as an integer that is scaled by a specific implicit factor. For example, the common notation&nbsp;<em>fix16_10&nbsp;<\/em> used by Xilinx stands for a 16-bit integer scaled by \\(2^{10}\\). In other words, 10 out of the 16 bits are used to represent the fractional part and 6 bits for the integer part.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-27-768x130.png\" alt=\"\" width=\"647\" height=\"110\"\/><\/figure><\/div>\n\n\n\n<p>Fixed-point arithmetic is widely used in FPGA-based algorithms because it usually runs faster and uses fewer resources when compared to floating-point arithmetic.<\/p>\n\n\n\n<p>However, one drawback of fixed-point arithmetic is that the user has to anticipate the range of the data and choose the scaling factor accordingly (the size of the fractional part), making the design more prone to errors.<\/p>\n\n\n\n<p>The <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-pwm-modulator\">custom FPGA PWM modulator<\/a> is a good example where it makes sense to use fixed-point arithmetic, given that the range of the duty-cycle parameter is restricted between 0.0 and 1.0.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-floating-point-arithmetic-in-fpga\"><span class=\"ez-toc-section\" id=\"Floating-point-arithmetic-in-FPGA\"><\/span>Floating-point arithmetic in FPGA<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>A floating-point number is represented with a fixed number of&nbsp;significant digits and scaled using an exponent in some fixed base. There are three formats supported by Xilinx tools: half (16 bit), single (32 bit), and double (64 bit). For example, a single format number is represented as:<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.imperix.com\/doc\/wp-content\/uploads\/2021\/06\/image-35.png\" alt=\"\" width=\"441\" height=\"142\"\/><\/figure><\/div>\n\n\n\n<p>Floating-point-based algorithms are more complex to handle than fixed-point, especially when using HDL languages (VHDL, Verilog). Fortunately, various Xilinx tools (such as the Vivado Floating-Point IP and other High-Level Synthesis (HLS) tools) make the development of floating-point-based algorithms much more convenient. Indeed, these tools add an abstraction level so that the user does not need to handle data representations to their binary representation level.<\/p>\n\n\n\n<p>We recommend starting a design by using the single format everywhere and then switching to fixed-point arithmetic, where necessary, to improve latency and resource utilization.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-how-to-typecast-in-matlab-simulink\"><span class=\"ez-toc-section\" id=\"How-to-typecast-in-MATLAB-Simulink\"><\/span>How to typecast in MATLAB Simulink<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p>To typecast a floating point to an integer in MATLAB Simulink, the following <a href=\"https:\/\/mathworks.com\/help\/simulink\/slref\/matlabfunction.html\">MATLAB Function<\/a> can be used. It uses the <a href=\"https:\/\/mathworks.com\/help\/matlab\/ref\/typecast.html\">typecast<\/a> instruction to alter the type of a variable without modifying the underlying binary number. As FPGA registers are 16-bits, this transformation is required in order to transform a 32-bit floating-point value into two 16-bit registers and transfer it from the CPU to the FPGA using.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"384\" height=\"104\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image.png\" alt=\"\" class=\"wp-image-4303\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image.png 384w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-300x81.png 300w\" sizes=\"auto, (max-width: 384px) 100vw, 384px\" \/><\/figure><\/div>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"Matlab\" data-shcb-language-slug=\"matlab\"><span><code class=\"hljs language-matlab\"><span class=\"hljs-function\"><span class=\"hljs-keyword\">function<\/span> <span class=\"hljs-params\">&#091;y1,y2]<\/span> = <span class=\"hljs-title\">single2sbo<\/span><span class=\"hljs-params\">(u)<\/span><\/span>\n  temp = typecast(single(u),<span class=\"hljs-string\">'uint16'<\/span>);\n  y1 = temp(<span class=\"hljs-number\">1<\/span>);\n  y2 = temp(<span class=\"hljs-number\">2<\/span>);<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">Matlab<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">matlab<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<p>Typecasting an integer to a floating point in MATLAB Simulink is the reverse operation. It consists of concatenating two <code>uint16<\/code> values and interpreting the result as single-precision data using the typecast MATLAB function.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-1.png\" alt=\"\" class=\"wp-image-4304\" width=\"405\" height=\"96\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-1.png 405w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/07\/image-1-300x71.png 300w\" sizes=\"auto, (max-width: 405px) 100vw, 405px\" \/><\/figure><\/div>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-2\" data-shcb-language-name=\"Matlab\" data-shcb-language-slug=\"matlab\"><span><code class=\"hljs language-matlab\"><span class=\"hljs-function\"><span class=\"hljs-keyword\">function<\/span> <span class=\"hljs-title\">y<\/span> = <span class=\"hljs-title\">sbi2single<\/span><span class=\"hljs-params\">(u1,u2)<\/span><\/span>\n  y = single(<span class=\"hljs-number\">0<\/span>); <span class=\"hljs-comment\">% sets compiled size of output<\/span>\n  y = typecast(&#091;uint16(u1) uint16(u2)], <span class=\"hljs-string\">'single'<\/span>);<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-2\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">Matlab<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">matlab<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<p>A use-case example of the MATLAB typecast function can be seen in the <a href=\"https:\/\/imperix.com\/doc\/implementation\/high-level-synthesis-for-fpga\">High-Level Synthesis for FPGA developments<\/a> example.<\/p>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-dark\" role=\"alert\">Back to\u00a0<a href=\"https:\/\/imperix.com\/doc\/help\/fpga-development-on-imperix-controllers\">FPGA development homepage<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>The choice of fixed vs floating-point arithmetic for an FPGA algorithm is a decision that has a significant impact on the FPGA resources usage, computation&#8230;<\/p>\n","protected":false},"author":4,"featured_media":7246,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[4],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,92,166,51,110],"guidedreadings":[],"tutorials":[],"user-manuals":[],"coauthors":[70],"class_list":["post-5313","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-implementation","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-cpp-sdk","related-products-tpi"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Fixed point vs floating point arithmetic in FPGA - imperix<\/title>\n<meta name=\"description\" content=\"This page compares the advantages and drawbacks of fixed vs floating-point. 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