{"id":826,"date":"2021-03-26T14:21:13","date_gmt":"2021-03-26T14:21:13","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=826"},"modified":"2025-05-07T07:19:12","modified_gmt":"2025-05-07T07:19:12","slug":"setting-up-the-fpga-development-toolchain","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain","title":{"rendered":"Setting up the FPGA development toolchain"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain\/#Software-resources\" >Software resources<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain\/#Installing-Vivado-SDK\" >Installing Vivado SDK<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain\/#Creating-a-sandbox-template-project\" >Creating a sandbox template project<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain\/#Adding-custom-logic-to-the-sandbox-project\" >Adding custom logic to the sandbox project<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain\/#Using-the-USR-pins\" >Using the USR pins<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain\/#Loading-the-bitstream-into-the-device\" >Loading the bitstream into the device<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/setting-up-the-fpga-development-toolchain\/#Update-the-imperix-firmware-IP-sources\" >Update the imperix firmware IP sources<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>This note provides step-by-step guidance to create a Xilinx Vivado project, add customized logic, generate a bitstream, and load it into the B-Box\/B-Board.<\/p>\n\n\n\n<p>The required software and sources files are:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Vivado HL Design Suite (available for free as the WebPACK edition)<\/li><li>Sandbox sources<\/li><\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">This page covers the installation of an older version of the Vivado SDK (2019.2). We recommend reading the newest pages:<br>&#8211;  <a href=\"https:\/\/imperix.com\/doc\/help\/vivado-design-suite-installation\">PN168: Xilinx Vivado Design Suite installation<\/a><br>&#8211;  <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">PN159: Getting started with FPGA control development<\/a><\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-software-resources\"><span class=\"ez-toc-section\" id=\"Software-resources\"><\/span>Software resources<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-installing-vivado-sdk\"><span class=\"ez-toc-section\" id=\"Installing-Vivado-SDK\"><\/span>Installing Vivado SDK<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>A Xilinx account is needed to download and install the Vivado SDK. It can be created by following the link <a href=\"https:\/\/www.xilinx.com\/registration\/create-account.html.\">https:\/\/www.xilinx.com\/registration\/create-account.html.<\/a><\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Go to Xilinx download page: <a href=\"https:\/\/www.xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/vivado-design-tools.html\">https:\/\/www.xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/vivado-design-tools.html<\/a><\/li><li>Download the installer. (for the free Windows version select &#8221; Vivado HLx: WebPACK and Editions&#8221;)<\/li><li>Run the downloaded file<\/li><li>Enter your login credentials and select <strong>Download and Install Now<\/strong><\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"869\" height=\"666\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-141.png\" alt=\"Xilinx Unified installer dialog\" class=\"wp-image-830\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; install_vivado_2019.2_2.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-141.png 869w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-141-300x230.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-141-768x589.png 768w\" sizes=\"auto, (max-width: 869px) 100vw, 869px\" \/><\/figure><\/div>\n\n\n\n<p>1. Select <strong>Vivado<\/strong><\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"869\" height=\"666\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-142.png\" alt=\"Xilinx Vivado installer dialog\" class=\"wp-image-831\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; install_vivado_2019.2_4.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-142.png 869w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-142-300x230.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-142-768x589.png 768w\" sizes=\"auto, (max-width: 869px) 100vw, 869px\" \/><\/figure><\/div>\n\n\n\n<p>2. Select <strong>Vivado HL WebPACK<\/strong><\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"869\" height=\"666\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-143.png\" alt=\"Vivado HL WebPACK installer dialog\" class=\"wp-image-832\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; install_vivado_2019.2_5.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-143.png 869w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-143-300x230.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-143-768x589.png 768w\" sizes=\"auto, (max-width: 869px) 100vw, 869px\" \/><\/figure><\/div>\n\n\n\n<p>3. The only mandatory item is <strong>Zynq-7000 support<\/strong><\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"869\" height=\"666\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-144.png\" alt=\"Zynq-7000 support\" class=\"wp-image-833\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; install_vivado_2019.2_6.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-144.png 869w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-144-300x230.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-144-768x589.png 768w\" sizes=\"auto, (max-width: 869px) 100vw, 869px\" \/><\/figure><\/div>\n\n\n\n<p>4. We recommend keeping the default installation directory<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"869\" height=\"666\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-145.png\" alt=\"Xilinx Unified installer destination folder\" class=\"wp-image-834\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; install_vivado_2019.2_7.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-145.png 869w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-145-300x230.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-145-768x589.png 768w\" sizes=\"auto, (max-width: 869px) 100vw, 869px\" \/><\/figure><\/div>\n\n\n\n<p>5. Hit <strong>Install<\/strong><\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-creating-a-sandbox-template-project\"><span class=\"ez-toc-section\" id=\"Creating-a-sandbox-template-project\"><\/span>Creating a sandbox template project<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Download the required sources to use the sandbox:<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Download the archive <strong>sandbox_sources_3.x_xxxx.x.zip<\/strong> from imperix\u2019s website, under <strong>Support<\/strong> \u2192 <strong>Downloads<\/strong> (<a href=\"https:\/\/imperix.com\/downloads\">https:\/\/imperix.com\/downloads<\/a>)<\/li><li>Unzip it and save the content somewhere on your PC, for instance in <code>C:\\imperix\\<\/code>.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-146.png\" alt=\"Save folder of sandbox resources\" class=\"wp-image-835\" width=\"615\" height=\"251\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-146.png 740w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-146-300x122.png 300w\" sizes=\"auto, (max-width: 615px) 100vw, 615px\" \/><\/figure><\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The sandbox sources 3.4 are compatible with the SDK version 3.4.x and 3.5.x<\/div>\n\n\n\n<p>To create a sandbox project:<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Open Vivado<\/li><li>Click <strong>Create Project<\/strong><\/li><li>Chose a name and a location.<\/li><li>Select project type <strong>RTL Project <\/strong>and check the box <strong>Do not specify sources at this time<\/strong>.<\/li><li>Select the part <strong>xc7z030fbg676-3<\/strong>.<\/li><li>Hit <strong>Finish<\/strong>. The project should open.<\/li><li>In <strong>Settings<\/strong>, the preferred <strong>Target Language<\/strong> can be set (VHDL or Verilog).<\/li><li>Go to the <strong>IP Catalog<\/strong>, right-click on <strong>Vivado Repository<\/strong>, hit <strong>Add repository&#8230;<\/strong><br>Select <code>C:\/imperix\/sandbox_sources\/ix_repository\/<\/code>.<br>The <em>IMPERIX_FW<\/em> IP, <em>clock_gen, <\/em>and <em>user_regs <\/em>interfaces should be found.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"486\" height=\"377\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-147.png\" alt=\"Add a Vivado repository\" class=\"wp-image-836\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-147.png 486w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-147-300x233.png 300w\" sizes=\"auto, (max-width: 486px) 100vw, 486px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"9\"><li>Click on <strong>Create block design,<\/strong> name it &#8220;top&#8221; and click <strong>OK<\/strong><\/li><li>Open the freshly created block design, do a right-click, select <strong>Add IP&#8230;<\/strong> and search for &#8220;IMPERIX_FW&#8221; and hit ENTER.<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-148.png\" alt=\"Vivado block of imperix IP\" class=\"wp-image-837\" width=\"415\" height=\"502\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-148.png 582w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-148-248x300.png 248w\" sizes=\"auto, (max-width: 415px) 100vw, 415px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"11\"><li>Keep the [Ctrl] key pressed and select the IP pins <code>flt<\/code>, <code>gpi<\/code>, <code>private_in<\/code>, <code>DDR<\/code>, <code>FIXED_IO<\/code>, <code>gpo<\/code>, <code>pwm<\/code> and <code>private_out<\/code>.<br>Hit [Ctrl+T] to create top-level ports.<\/li><li>Remove the &#8220;_0&#8221; from every port name generated. For instance &#8220;<code>flt_0[15:0]<\/code>&#8221; becomes &#8220;<code>flt[15:0]<\/code>&#8220;.<\/li><li>The <code>user_fw_id<\/code> input may be used to identify the firmware version. We recommend instantiating a Constant IP (Right-click, <strong>Add IP&#8230;<\/strong>, search for <em>Constant<\/em>) to give an identification number to the design.<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"570\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-149-1024x570.png\" alt=\"Firmware ID of imperix IP\" class=\"wp-image-838\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-149-1024x570.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-149-300x167.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-149-768x427.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-149.png 1303w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<ol class=\"wp-block-list\" start=\"14\"><li>Go to the <strong>Sources <\/strong>tab, right-click on the block design file (top.bd) and select <strong>Create HDL Wrapper&#8230;<\/strong><br>In the dialog box choose <strong>Let Vivado manager wrapper and auto-update<\/strong> and hit <strong>OK<\/strong>.<\/li><li>Right-click on <strong>Design Sources<\/strong> folder<br>Choose <strong>Add Sources\u2026<\/strong><br>Check <strong>Add or create constraint<\/strong><br>Click on <strong>Add Files<\/strong><br>Select <code>C:\/imperix\/sandbox_sources\/constraints\/sandbox_pins.xdc<\/code><br>Uncheck <strong>Copy sources into the project<\/strong><br>Hit <strong>Finish<\/strong><\/li><\/ol>\n\n\n\n<p>From this point the project is synthesizable. The next chapter covers how to add custom logic to the design.<\/p>\n\n\n\n<p>Information on how to use the imperix firmware IP can be found in the product note about <a href=\"https:\/\/imperix.com\/doc\/help\/editing-the-fpga-firmware-using-the-sandbox\">editing the FPGA firmware<\/a>.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-adding-custom-logic-to-the-sandbox-project\"><span class=\"ez-toc-section\" id=\"Adding-custom-logic-to-the-sandbox-project\"><\/span>Adding custom logic to the sandbox project<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The following steps use the file <code>sandbox_template.vhd<\/code> as an example to illustrate how to add a VHDL entity to the project and interface it to the imperix firmware IP.<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Right-click on <strong>Design Sources<\/strong> and choose <strong>Add Sources&#8230;<\/strong>. Check <strong>Add or create design sources<\/strong>.<\/li><li>Select <code>imperix_sandbox_sources\/hdl\/sandbox_template.vhd<\/code>.<br>We recommend unchecking &#8220;Copy sources into project&#8221; and working directly from the files in the folder <code>imperix_sandbox_sources\/hdl\/<\/code> so the sources can be shared across multiple projects.<\/li><li>Right-click somewhere in the block design and chose <strong>Add module&#8230;<\/strong> Select the <em>SandboxTemplate <\/em>module. Alternatively, you can drag the file listed in the <em>Design Sources<\/em> and drop it on your diagram.<\/li><li>Connect the pins as follows:<\/li><\/ol>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"438\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-150-1024x438.png\" alt=\"Interfacing of Sandbox module and imperix IP\" class=\"wp-image-839\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; vivado_ip_v2_2.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-150-1024x438.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-150-300x128.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-150-768x328.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-150.png 1445w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>The imperix firmware IP provides 64 SBI registers, 64 SBO registers, and 24 ADC registers which are grouped in interfaces for better readability. The sandbox_template.vhd illustrates how to use X_INTERFACE_INFO attributes to infer the ADC, SBI, and SBO interfaces.<\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"VHDL\" data-shcb-language-slug=\"vhdl\"><span><code class=\"hljs language-vhdl\"><span class=\"hljs-keyword\">library<\/span> IEEE;\n<span class=\"hljs-keyword\">use<\/span> IEEE.STD_LOGIC_1164.<span class=\"hljs-keyword\">ALL<\/span>;\n<span class=\"hljs-keyword\">use<\/span> IEEE.NUMERIC_STD.<span class=\"hljs-keyword\">ALL<\/span>;\n\n<span class=\"hljs-keyword\">entity<\/span> SandboxTemplate <span class=\"hljs-keyword\">is<\/span>\n  <span class=\"hljs-keyword\">Port<\/span> ( \n\n    <span class=\"hljs-comment\">-- Analog-to-digital conversion results in 2's complement format <\/span>\n    adc_00_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>);\n    adc_01_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_02_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_03_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_04_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_05_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_06_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_07_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_08_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_09_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_10_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_11_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_12_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_13_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_14_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    adc_15_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>);\n \n    <span class=\"hljs-comment\">-- Output to the sandbox for CPU to FPGA communication<\/span>\n    sbo_reg_00_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    sbo_reg_01_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    sbo_reg_02_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">15<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>) := (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n    <span class=\"hljs-comment\">-- you can add more registers here <\/span>\n\n    <span class=\"hljs-comment\">-- Timing pulses <\/span>\n    sampling_pulse_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic<\/span>; \n    adc_done_pulse_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic<\/span>; \n    read_pulse_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic<\/span>; \n    data_valid_pulse_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic<\/span>; \n\n    <span class=\"hljs-comment\">-- Sandbox PWM <\/span>\n    sb_pwm_out : <span class=\"hljs-keyword\">out<\/span> <span class=\"hljs-built_in\">std_logic_vector<\/span>(<span class=\"hljs-number\">31<\/span> <span class=\"hljs-keyword\">downto<\/span> <span class=\"hljs-number\">0<\/span>); \n\n    <span class=\"hljs-comment\">-- Main clock running at 250 MHz <\/span>\n    clk_in : <span class=\"hljs-keyword\">in<\/span> <span class=\"hljs-built_in\">std_logic<\/span> \n  ); \n<span class=\"hljs-keyword\">end<\/span> SandboxTemplate; \n\n<span class=\"hljs-keyword\">architecture<\/span> impl <span class=\"hljs-keyword\">of<\/span> SandboxTemplate <span class=\"hljs-keyword\">is<\/span> \n  \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO : <span class=\"hljs-built_in\">STRING<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_PARAMETER : <span class=\"hljs-built_in\">STRING<\/span>; \n\n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> clk: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"xilinx.com:signal:clock:1.0 clk CLK\"<\/span>; \n  \n  <span class=\"hljs-comment\">-- Informations to infer the SBI interface <\/span>\n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> sbi_reg_00_out: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 SBI reg_00\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> sbi_reg_01_out: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 SBI reg_01\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> sbi_reg_02_out: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 SBI reg_02\"<\/span>; \n\n  <span class=\"hljs-comment\">-- Informations to infer the SBO interface <\/span>\n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> sbo_reg_00_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 SBO reg_00\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> sbo_reg_01_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 SBO reg_01\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> sbo_reg_02_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 SBO reg_02\"<\/span>; \n  \n  <span class=\"hljs-comment\">-- Informations to infer the ADC interface <\/span>\n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_00_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_00\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_01_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_01\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_02_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_02\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_03_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_03\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_04_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_04\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_05_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_05\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_06_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_06\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_07_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_07\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_08_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_08\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_09_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_09\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_10_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_10\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_11_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_11\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_12_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_12\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_13_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_13\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_14_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_14\"<\/span>; \n  <span class=\"hljs-keyword\">ATTRIBUTE<\/span> X_INTERFACE_INFO <span class=\"hljs-keyword\">of<\/span> adc_15_in: <span class=\"hljs-keyword\">SIGNAL<\/span> <span class=\"hljs-keyword\">is<\/span> <span class=\"hljs-string\">\"imperix.ch:ix:user_regs_rtl:1.0 ADC reg_15\"<\/span>; \n\n<span class=\"hljs-keyword\">begin<\/span> \n\n  sb_pwm_out &lt;= (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n\n  sbi_reg_00_out &lt;= (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n  sbi_reg_00_out &lt;= (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n  sbi_reg_00_out &lt;= (<span class=\"hljs-keyword\">others<\/span> =&gt; <span class=\"hljs-string\">'0'<\/span>); \n\n  MY_PROCESS : <span class=\"hljs-keyword\">process<\/span>(clk_in) \n  <span class=\"hljs-keyword\">begin<\/span> \n    <span class=\"hljs-keyword\">if<\/span> rising_edge(clk_in) <span class=\"hljs-keyword\">then<\/span> \n\n      <span class=\"hljs-keyword\">if<\/span> adc_done_pulse_in = <span class=\"hljs-string\">'1'<\/span> <span class=\"hljs-keyword\">then<\/span> \n        <span class=\"hljs-comment\">-- sampled value are available in ADC registers <\/span>\n      <span class=\"hljs-keyword\">end<\/span> <span class=\"hljs-keyword\">if<\/span>; \n\n      <span class=\"hljs-keyword\">if<\/span> data_valid_pulse_in = <span class=\"hljs-string\">'1'<\/span> <span class=\"hljs-keyword\">then<\/span> \n        <span class=\"hljs-comment\">-- new data has been written to SBO registers <\/span>\n      <span class=\"hljs-keyword\">end<\/span> <span class=\"hljs-keyword\">if<\/span>; \n\n    <span class=\"hljs-keyword\">end<\/span> <span class=\"hljs-keyword\">if<\/span>; \n  <span class=\"hljs-keyword\">end<\/span> <span class=\"hljs-keyword\">process<\/span> MY_PROCESS; \n\n<span class=\"hljs-keyword\">end<\/span> impl;  <\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">VHDL<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">vhdl<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The use of interfaces is optional. The user can instead expand an IP interface by clicking on the &#8220;+&#8221; and directly use the ports which can be useful if the registers from a single bus have to be connected to multiple modules.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-using-the-usr-pins\"><span class=\"ez-toc-section\" id=\"Using-the-USR-pins\"><\/span>Using the USR pins<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The file <code>sandbox_pins.xdc<\/code> contains the constraints for the 36 USR pins.<\/p>\n\n\n\n<p>To use USR pins:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>un-comment the line of the pins to use<\/li><li>create the corresponding ports in the Vivado block design (right click, Create Port&#8230;)<\/li><\/ul>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-2\" data-shcb-language-name=\"Tcl\" data-shcb-language-slug=\"tcl\"><span><code class=\"hljs language-tcl\"><span class=\"hljs-comment\">#### <\/span>\n=========================================================================== \n<span class=\"hljs-comment\">#### USR <\/span>\n<span class=\"hljs-comment\">#### <\/span>\n=========================================================================== \n\nset_property -<span class=\"hljs-keyword\">dict<\/span> {PACKAGE_PIN AE10 IOSTANDARD LVCMOS33} &#91;get_ports {usr_0}] \nset_property -<span class=\"hljs-keyword\">dict<\/span> {PACKAGE_PIN AF10 IOSTANDARD LVCMOS33} &#91;get_ports {usr_1}] \nset_property -<span class=\"hljs-keyword\">dict<\/span> {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} &#91;get_ports {usr_2}] \n<span class=\"hljs-comment\">#set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} &#91;get_ports {usr_3}] <\/span>\n<span class=\"hljs-comment\">#set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} &#91;get_ports {usr_4}] <\/span>\n<span class=\"hljs-comment\">#set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} &#91;get_ports {usr_5}] <\/span>\n...<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-2\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">Tcl<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">tcl<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-151-1024x439.png\" alt=\"Ports in Vivado block design\" class=\"wp-image-846\" width=\"638\" height=\"273\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; vivado_usr_pins.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-151-1024x439.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-151-300x128.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-151-768x329.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-151.png 1032w\" sizes=\"auto, (max-width: 638px) 100vw, 638px\" \/><\/figure><\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-loading-the-bitstream-into-the-device\"><span class=\"ez-toc-section\" id=\"Loading-the-bitstream-into-the-device\"><\/span>Loading the bitstream into the device<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Generate and export the bitstream:<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Click <strong>Generate bitstream<\/strong>. It will launch the synthesis, implementation and bitstream generation<\/li><li>Click on <strong>File <\/strong>\u2192 <strong>Export <\/strong>\u2192 <strong>Export Bitstream File&#8230;<\/strong><\/li><\/ol>\n\n\n\n<p>Using BB Control, the bitstream can be loaded using the following procedure:<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Go to the <strong>Configuration <\/strong>tab<\/li><li>Click on the \u201cimport bitstream\u201d button, it will upload the bitstream into the B-Board SD card<\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"426\" height=\"119\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-152.png\" alt=\"\" class=\"wp-image-849\" title=\"Product notes &gt; PN120: Setting up the FPGA development toolchain &gt; BB_Control_load_bitstream_1.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-152.png 426w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-152-300x84.png 300w\" sizes=\"auto, (max-width: 426px) 100vw, 426px\" \/><\/figure><\/div>\n\n\n\n<p>A check in the <strong>load at startup<\/strong> checkbox indicates that the device will load the imported customized bitstream at the next power-cycle instead of the standard one.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"426\" height=\"89\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-153.png\" alt=\"\" class=\"wp-image-850\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-153.png 426w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-153-300x63.png 300w\" sizes=\"auto, (max-width: 426px) 100vw, 426px\" \/><\/figure><\/div>\n\n\n\n<p>In the <strong>Versions<\/strong> section is indicated if the device has a customized bitstream loaded.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"418\" height=\"146\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-154.png\" alt=\"\" class=\"wp-image-851\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-154.png 418w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-154-300x105.png 300w\" sizes=\"auto, (max-width: 418px) 100vw, 418px\" \/><\/figure><\/div>\n\n\n\n<p>The information is also available from the Message Log.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"920\" height=\"746\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-155.png\" alt=\"Message log tab of BB Control\" class=\"wp-image-852\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-155.png 920w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-155-300x243.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-155-768x623.png 768w\" sizes=\"auto, (max-width: 920px) 100vw, 920px\" \/><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-update-the-imperix-firmware-ip-sources\"><span class=\"ez-toc-section\" id=\"Update-the-imperix-firmware-IP-sources\"><\/span>Update the imperix firmware IP sources<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The version of the imperix IP currently in use is found in the block properties of the IP (by clicking on the IP)<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-156.png\" alt=\"Block properties of the IP\" class=\"wp-image-854\" width=\"376\" height=\"164\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-156.png 442w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-156-300x131.png 300w\" sizes=\"auto, (max-width: 376px) 100vw, 376px\" \/><\/figure><\/div>\n\n\n\n<p>To update the sources of the imperix IP<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Replace the sandbox sources by the ones of the targeted version.<\/li><li>Do a right click on <strong>Design Sources<\/strong> and click on<strong> Refresh Hierarchy<\/strong><\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151057.png\" alt=\"Refresh Hierarchy menu\" class=\"wp-image-864\" width=\"425\" height=\"374\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151057.png 498w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151057-300x264.png 300w\" sizes=\"auto, (max-width: 425px) 100vw, 425px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"3\"><li>An information message should appear, click on&nbsp;<strong>Refresh IP Catalog<\/strong><\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151216.png\" alt=\"Refresh IP Catalog\" class=\"wp-image-865\" width=\"528\" height=\"106\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151216.png 595w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151216-300x60.png 300w\" sizes=\"auto, (max-width: 528px) 100vw, 528px\" \/><\/figure><\/div>\n\n\n\n<ol class=\"wp-block-list\" start=\"4\"><li>Finally, under the&nbsp;<strong>IP Status<\/strong> tab, select the IXIP and click&nbsp;<strong>Upgrade Selected<\/strong><\/li><\/ol>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"191\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151400-1024x191.png\" alt=\"Upgrade Selected IP\" class=\"wp-image-866\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151400-1024x191.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151400-300x56.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151400-768x143.png 768w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-20200817-151400.png 1332w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure><\/div>\n","protected":false},"excerpt":{"rendered":"<p>This note provides step-by-step guidance to create a Xilinx Vivado project, add customized logic, generate a bitstream, and load it into the B-Box\/B-Board. The required&#8230;<\/p>\n","protected":false},"author":4,"featured_media":2997,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,92,166,51,110],"guidedreadings":[],"tutorials":[],"user-manuals":[],"coauthors":[70],"class_list":["post-826","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-cpp-sdk","related-products-tpi"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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