{"id":877,"date":"2021-03-26T15:19:05","date_gmt":"2021-03-26T15:19:05","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=877"},"modified":"2026-04-16T13:35:54","modified_gmt":"2026-04-16T13:35:54","slug":"imperix-ip-user-guide","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide","title":{"rendered":"Product guide of the imperix firmware IP"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Architecture-overview\" >Architecture overview<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Execution-timing-signals\" >Execution timing &amp; signals<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Differences-between-Gen-3-and-Gen-4-for-FPGA-development\" >Differences between Gen 3 and Gen 4 for FPGA development<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Imperix-firmware-IP-interfaces-description\" >Imperix firmware IP interfaces description<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Disabling-features-to-save-FPGA-resources\" >Disabling features to save FPGA resources<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>This page documents the <strong>imperix firmware IP<\/strong> for AMD Xilinx Vivado, which is mandatory for programming the FPGA of imperix controllers. The IP encapsulates the imperix proprietary FPGA logic and offers various interfaces allowing users to add their own custom logic around it.<\/p>\n\n\n\n<p>This document details the IP signals and associated timings. For guides on using specific features, the product notes linked in the table below may be consulted.<\/p>\n\n\n<style>.wp-block-kadence-spacer.kt-block-spacer-877_a1070e-a2 .kt-block-spacer{height:60px;}.wp-block-kadence-spacer.kt-block-spacer-877_a1070e-a2 .kt-divider{border-top-width:1px;height:1px;border-top-color:#eee;width:80%;border-top-style:solid;}<\/style>\n<div class=\"wp-block-kadence-spacer aligncenter kt-block-spacer-877_a1070e-a2\"><div class=\"kt-block-spacer kt-block-spacer-halign-center\"><hr class=\"kt-divider\"\/><\/div><\/div>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td><strong>Interface<\/strong><\/td><td><strong>Feature<\/strong><\/td><td><strong>Product&nbsp;note<\/strong><\/td><\/tr><tr><td>ADC<\/td><td>Retrieving ADC conversion results as soon as they are available.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126<\/a><\/td><\/tr><tr><td>SBIO<\/td><td>Exchanging data between the user code running in the CPU and the FPGA.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128<\/a><\/td><\/tr><tr><td>SB-PWM<\/td><td>Driving the PWM output chain, comprised of a dead-time generation system and the hardware protection mechanisms.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a><\/td><\/tr><tr><td>USR<\/td><td>Accessing physical 3V3 I\/O pins.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\">PN179<\/a><\/td><\/tr><tr><td>GT<\/td><td>Accessing Gigabit Transceivers (GT), enabling support of protocols such as Aurora on SFP ports.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">PN118<\/a><\/td><\/tr><tr><td>BSCAN<\/td><td> U sing ILAs to observe FPGA signals in real-time for debugging purposes.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\">PN129<\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-top is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-top is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"430\" height=\"648\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_imperix_fw_ip.png\" alt=\"\" class=\"wp-image-40175\" style=\"aspect-ratio:0.6635902168897093;width:303px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_imperix_fw_ip.png 430w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_imperix_fw_ip-199x300.png 199w\" sizes=\"auto, (max-width: 430px) 100vw, 430px\" \/><figcaption class=\"wp-element-caption\">imperix firmware IP<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The imperix firmware IP can be acquired from the <a href=\"https:\/\/imperix.com\/doc\/help\/download-and-update-imperix-ip-for-fpga-sandbox\">download<\/a> page. For developers beginning a new design, the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">getting started with FPGA<\/a> guide provides the instructions for creating the Vivado sandbox template project and starting the development of custom FPGA logic.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"Overview\"><span class=\"ez-toc-section\" id=\"Architecture-overview\"><\/span>Architecture overview<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Because FPGA development operates at the hardware level, a proper understanding of the underlying system architecture and real-time execution behavior is essential to successfully integrating custom logic in an imperix controller FPGA.<\/p>\n\n\n\n<p>Imperix is currently supporting two generations of controller, both based on AMD Xilinx System-on-Chips (SoCs):<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Gen 3<\/strong> controllers (<a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box RCP<sup>3.0<\/sup><\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/power-inverter-controller\/\">B-Box Micro<\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a>, <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">TPI8032<\/a>) are based on a <strong>AMD Xilinx Zynq&nbsp;7000<\/strong><\/li>\n\n\n\n<li><strong>Gen 4<\/strong> controller (<a href=\"https:\/\/imperix.com\/products\/control\/rcp-controller\/\">B-Box 4<\/a>) is based of an <strong>AMD <strong>Xilinx <\/strong>Zynq Ultrascale+<\/strong><\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">While the specific components (number of CPUs, CPU clock speeds, available FPGA resources, etc.) vary between the two generations, the core working principles and control workflow remain identical. Specific generational differences regarding FPGA development are detailed later in this guide.<\/div>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"528\" height=\"506\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-353.png\" alt=\"\" class=\"wp-image-44098\" style=\"aspect-ratio:1.0434796034956613;width:492px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-353.png 528w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-353-300x288.png 300w\" sizes=\"auto, (max-width: 528px) 100vw, 528px\" \/><figcaption class=\"wp-element-caption\">Architecture of imperix controllers<\/figcaption><\/figure>\n<\/div>\n\n\n<p>The image above depicts the overall architecture of imperix controllers. The key components are:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>supervisor CPU<\/strong> runs on Linux. It is responsible for loading the application code, supervising system execution and managing data logging.<\/li>\n\n\n\n<li>The <strong>user app CPU<\/strong> runs on <a href=\"https:\/\/imperix.com\/software\/bbos\/\">BBOS<\/a>. It executes the application-level control code developed by the user using the <a href=\"https:\/\/imperix.com\/software\/acg-sdk\/\">ACG SDK<\/a> (Simulink or PLECS ) or the <a href=\"https:\/\/imperix.com\/software\/cpp-sdk\/\">CPP SDK<\/a> (C\/C++).<\/li>\n\n\n\n<li>The <strong>imperix firmware IP<\/strong> encapsulates the mandatory pre-implemented FPGA peripherals.<\/li>\n<\/ul>\n\n\n\n<p>The illustration above shows a simplified breakdown of the core modules contained within the imperix firmware IP.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>data acquisition<\/strong> <strong>module<\/strong> (documented in <a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126<\/a>)  pilots the ADC chips and makes the analog input measurement available to both the CPU user app and the user-programmable FPGA area.<\/li>\n\n\n\n<li>The <strong>pulse-width modulation<\/strong> (documented in <a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a>) contains the pre-implemented PWM modulators (<a href=\"https:\/\/imperix.com\/doc\/software\/carrier-based-pwm\">CB<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/sv-pwm\">SV<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/direct-output-pwm\">DO<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/sort-select-multilevel-pwm\">SS<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/programmed-pattern-pwm\">PP<\/a>) and allows driving the PWM outputs from a custom modulator through the SB-PWM input.<\/li>\n\n\n\n<li>The <strong>CLK <\/strong>module manages the main clock CLK0 (configured via the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> block), and the optional CLK1, CLK2 and CLK3 (configured via <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> block).<\/li>\n\n\n\n<li>The <strong>DMA<\/strong> is in charge of transferring the data between the FPGA and the CPU <strong>read\/write buffers<\/strong>. The <em>read<\/em> and <em>write<\/em> phases are detailed in the next section.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Execution-timing-signals\"><\/span>Execution timing &amp; signals<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The following figure illustrates the phases involved in the <strong>CPU control path<\/strong> (acquisition, read, CPU task and write) and the <strong>FPGA control path<\/strong> (acquisition and FPGA task).<\/p>\n\n\n\n<p>The execution phases are defined as follow:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Acquisition<\/strong>: covers the physical Analog-to-Digital conversion (ADC) and the subsequent acquisition of the results to the FPGA fabric.<\/li>\n\n\n\n<li><strong>Read<\/strong>: data flagged as real-time are transferred from the FPGA to the CPU read buffer.<\/li>\n\n\n\n<li><strong>CPU task<\/strong>: the CPU reads the buffer and executes the main control task (the user&#8217;s application control code). At the conclusion of this phase, the CPU write buffer is updated with new control values.<\/li>\n\n\n\n<li><strong>Write<\/strong>: data flagged as real-time is transferred from the CPU write buffer back to the FPGA peripherals via DMA.<\/li>\n\n\n\n<li><strong>FPGA task<\/strong>: control algorithm fully executed in the FPGA,  such as the FPGA-based control of a grid-tied inverter presented in the <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">TN147<\/a> example.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"545\" height=\"452\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-352.png\" alt=\"\" class=\"wp-image-44082\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-352.png 545w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-352-300x249.png 300w\" sizes=\"auto, (max-width: 545px) 100vw, 545px\" \/><figcaption class=\"wp-element-caption\">Phases of the CPU and FPGA control paths<\/figcaption><\/figure>\n<\/div>\n\n\n<p>As illustrated in the schematic below, the imperix firmware IP provides several signals designed to monitor and synchronize logic with the execution of these different phases.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"633\" height=\"284\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-342.png\" alt=\"\" class=\"wp-image-42997\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-342.png 633w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-342-300x135.png 300w\" sizes=\"auto, (max-width: 633px) 100vw, 633px\" \/><figcaption class=\"wp-element-caption\">Execution timing signals<\/figcaption><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th class=\"has-text-align-left\" data-align=\"left\">Port name<\/th><td><strong>Clk domain<\/strong><\/td><th class=\"has-text-align-left\" data-align=\"left\">Description<\/th><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code><code>sampling_pulse<\/code><\/code><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Corresponds to the rising edge of the sampling clock <strong>SCLK<\/strong> and indicates the ADC sampling instant and the start of the&nbsp;<strong>acquisition<\/strong> phase.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code><code>adc_done_pulse<\/code>&nbsp;<\/code><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Indicates that the <strong>acquisition<\/strong> phases finished and new ADC values are available at the&nbsp;<code>ADC<\/code>&nbsp;interface.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>adc_done_cpu_pulse<\/code><strong>&nbsp;<\/strong><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">When the sampling rate differs from the CPU rate, this signal is a decimated version of <strong><code>adc_done_pulse<\/code><\/strong>. It is set when the CPU control path stages are scheduled to execute. The following section describes this scenario in more details.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code><code>reading<\/code><strong>&nbsp;<\/strong><\/code><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Indicates that the system is in the&nbsp;<strong>read&nbsp;<\/strong>phase, in which data flagged as real-time (SBI registers, ADC, GPI, etc.) are sent to the CPU read buffer.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>data_valid_pulse<\/code>&nbsp;<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Asserted at the end of the <strong>write<\/strong> phase, notifying that new data were written (SBO registers, PWM duty-cycles, GPO, etc.) .<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">Handling different execution rates<\/h3>\n\n\n\n<p>In many applications, FPGA-based control algorithms execute at a higher rate than the CPU task. In such case, a <strong>postscaler <\/strong>can be configured in the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> block to reduce the execution rate of the CPU task relative to the sampling frequency.<\/p>\n\n\n\n<p>When a postscaler is used, the&nbsp;<strong><code>adc_done_cpu_pulse<\/code>&nbsp;<\/strong>signal acts as the decimated version of <strong><code>adc_done_pulse<\/code><\/strong>. It is asserted when the CPU control path stages are scheduled to run.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"633\" height=\"404\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-343.png\" alt=\"\" class=\"wp-image-42998\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-343.png 633w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-343-300x191.png 300w\" sizes=\"auto, (max-width: 633px) 100vw, 633px\" \/><figcaption class=\"wp-element-caption\">Execution timing with postscaler = 4<\/figcaption><\/figure>\n<\/div>\n\n\n<p>By default, the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC<\/a> block or driver only provides only the most recently sampled value. However, it is still possible to retrieve all ADC samples within the CPU using the  <strong>ADC history<\/strong> feature, as illustrated below. This feature allows the retrieval of the <em>N<\/em> most recent samples (up to a maximum of 64).<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"360\" height=\"416\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-361.png\" alt=\"\" class=\"wp-image-44746\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-361.png 360w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-361-260x300.png 260w\" sizes=\"auto, (max-width: 360px) 100vw, 360px\" \/><figcaption class=\"wp-element-caption\">Retrieving multiple values per CPU cycle in Simulink<\/figcaption><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"360\" height=\"416\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-362.png\" alt=\"\" class=\"wp-image-44748\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-362.png 360w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-362-260x300.png 260w\" sizes=\"auto, (max-width: 360px) 100vw, 360px\" \/><figcaption class=\"wp-element-caption\">Retrieving multiple values per CPU cycle in PLECS<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>CPP SDK users can implement this using the <code>Adc_ConfigureHistory<\/code> and <code>Adc_GetHistory<\/code> functions, as illustrated in the code snippet below:<\/p>\n\n\n<pre class=\"wp-block-code\" aria-describedby=\"shcb-language-1\" data-shcb-language-name=\"C++\" data-shcb-language-slug=\"cpp\"><span><code class=\"hljs language-cpp\"><span class=\"hljs-function\">tUserSafe <span class=\"hljs-title\">UserInit<\/span><span class=\"hljs-params\">(<span class=\"hljs-keyword\">void<\/span>)<\/span> <\/span>{\n\n  <span class=\"hljs-comment\">\/\/ Sets CLK0 at 50 kHz<\/span>\n  Clock_SetFrequency(CLOCK_0, <span class=\"hljs-number\">50e3<\/span>);\n\n  <span class=\"hljs-comment\">\/\/ Sets a CPU postscaler of 4<\/span>\n  ConfigureMainInterrupt(UserInterrupt, CLOCK_0, <span class=\"hljs-number\">0.5<\/span>, <span class=\"hljs-number\">4<\/span>)\n   \n  <span class=\"hljs-comment\">\/\/ Setup a history of 4 samples for ADC0<\/span>\n  Adc_ConfigureHistory(ADC0, <span class=\"hljs-number\">4<\/span>);\n   \n  <span class=\"hljs-comment\">\/\/ some other code...<\/span>\n   \n  <span class=\"hljs-keyword\">return<\/span> SAFE\n}\n \ntUserSafe UserInit(<span class=\"hljs-keyword\">void<\/span>) {\n \n  <span class=\"hljs-keyword\">float<\/span> s0, s1, s2, s3;\n   \n  s0 = Adc_GetHistory(ADC0, <span class=\"hljs-number\">0<\/span>); <span class=\"hljs-comment\">\/\/ most recent sample<\/span>\n  s1 = Adc_GetHistory(ADC0, <span class=\"hljs-number\">1<\/span>);\n  s2 = Adc_GetHistory(ADC0, <span class=\"hljs-number\">2<\/span>);\n  s3 = Adc_GetHistory(ADC0, <span class=\"hljs-number\">3<\/span>);\n  \n  <span class=\"hljs-keyword\">return<\/span> SAFE;\n}<\/code><\/span><small class=\"shcb-language\" id=\"shcb-language-1\"><span class=\"shcb-language__label\">Code language:<\/span> <span class=\"shcb-language__name\">C++<\/span> <span class=\"shcb-language__paren\">(<\/span><span class=\"shcb-language__slug\">cpp<\/span><span class=\"shcb-language__paren\">)<\/span><\/small><\/pre>\n\n\n<h2 class=\"wp-block-heading\" id=\"Differences-between-Gen-3-and-Gen-4-for-FPGA-development\"><span class=\"ez-toc-section\" id=\"Differences-between-Gen-3-and-Gen-4-for-FPGA-development\"><\/span>Differences between Gen 3 and Gen 4 for FPGA development<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The Gen 4 introduces several key enhancements, including access to analog measurement in floating point format, faster transceivers, and expanded FPGA resources. The table below summaries the key differences between the two generations. <\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td class=\"has-text-align-left\" data-align=\"left\"><strong>Component<\/strong><\/td><td class=\"has-text-align-left\" data-align=\"left\"><strong>Gen 3<\/strong><\/td><td class=\"has-text-align-left\" data-align=\"left\"><strong>Gen 4<\/strong><\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">FPGA<\/td><td class=\"has-text-align-left\" data-align=\"left\">Kintex 7 125K<\/td><td class=\"has-text-align-left\" data-align=\"left\">Kintex US+ 504K<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Logic<\/td><td class=\"has-text-align-left\" data-align=\"left\">LUTs: 78600<br>Registers: 157200<\/td><td class=\"has-text-align-left\" data-align=\"left\">LUTs: 230400<br>Registers: 460800<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Logic used by imperix IP*<\/td><td class=\"has-text-align-left\" data-align=\"left\">min:<br>LUTs: 25482 (32.4%)<br>Registers: 46374 (29.5%)<br><br>max:<br>LUTs: 39143 (49.8%)<br>Registers: 67203 (42.7%)<\/td><td class=\"has-text-align-left\" data-align=\"left\">min:<br>LUTs 70733 (30.7%)<br>Registers 108749 (23.6%)<br><br>max:<br>LUTs: 94233 (40.9%)<br>Registers: 140636 (30.5%)<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Usable logic left*<\/td><td class=\"has-text-align-left\" data-align=\"left\">max:<br>LUTs: 53118 (67.6%)<br>Registers: 110826 (70.5%)<br><br>min:<br>LUTs: 39457 (50.2%)<br>Registers: 89997 (57.3%)<\/td><td class=\"has-text-align-left\" data-align=\"left\">max:<br>LUTs: 159667 (69.3%)<br>Registers: 352051 (76.4%)<br><br>min:<br>LUTs: 136167 (59.1%)<br>Registers: 320164 (60.5%)<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Gigabit Transceivers available from the sandbox<\/td><td class=\"has-text-align-left\" data-align=\"left\">3x GTX (3x SFP connectors)<br>Up to 6.6 Gbps<\/td><td class=\"has-text-align-left\" data-align=\"left\">4x GTH (1x QSFP connector)<br>Up to 16.3 Gbps<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Bidirectional direct FPGA I\/Os (USR)<\/td><td class=\"has-text-align-left\" data-align=\"left\">36x<\/td><td class=\"has-text-align-left\" data-align=\"left\">36x<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">PWM outputs<\/td><td class=\"has-text-align-left\" data-align=\"left\">32x<\/td><td class=\"has-text-align-left\" data-align=\"left\">48x<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">ADC interface<\/td><td class=\"has-text-align-left\" data-align=\"left\">16x (int16)<\/td><td class=\"has-text-align-left\" data-align=\"left\">24x (int16, or float)<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">RS485\/RS422<\/td><td class=\"has-text-align-left\" data-align=\"left\">&#8211;<\/td><td class=\"has-text-align-left\" data-align=\"left\">&nbsp;2x<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Acquisition delay<\/td><td class=\"has-text-align-left\" data-align=\"left\">2 \u03bcs (B-Box RCP 3.0)<br>500 ns (B-Box Micro, B-Board, TPI8032)<\/td><td class=\"has-text-align-left\" data-align=\"left\">&nbsp;200 ns \/ 368 ns**<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>* The logic used by the imperix IP depends on the enabled features, as explained in the <em>Disabling Features to Save FPGA Resources<\/em> section.<\/p>\n\n\n\n<p>** When channels A12-A23 are used.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Imperix-firmware-IP-interfaces-description\"><\/span>Imperix firmware IP interfaces description<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"ADC-interface-to-retrieve-analog-measurements\">ADC interface<\/h3>\n\n\n\n<p class=\"has--font-size\">The&nbsp;ADC<strong>&nbsp;<\/strong>interface returns the raw&nbsp;16-bit signed integer&nbsp;result from the ADC chips.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126<\/a> further describe how to retrieving ADC measurements from the FPGA sandbox.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_fixed16_0.svg\" alt=\"\" class=\"wp-image-40187\" style=\"aspect-ratio:3.5716919585874343;width:647px;height:auto\"\/><figcaption class=\"wp-element-caption\">Format: 16-bit signed integer (two&#8217;s complement, range: -32768 to +32767)<\/figcaption><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th class=\"has-text-align-left\" data-align=\"left\">Port Name<\/th><th class=\"has-text-align-left\" data-align=\"left\">Direction<\/th><th class=\"has-text-align-left\" data-align=\"left\">Width<\/th><td><strong>Clk domain<\/strong><\/td><th class=\"has-text-align-left\" data-align=\"left\">Description<\/th><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>ADC_reg_XX<\/code><\/td><td class=\"has-text-align-left\" data-align=\"left\">Output<\/td><td class=\"has-text-align-left\" data-align=\"left\">16bits<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">ADC 16-bit result in 2\u2019s complement format.<br>XX = channel<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>adc_done_pulse<\/code><\/td><td class=\"has-text-align-left\" data-align=\"left\">Output<\/td><td class=\"has-text-align-left\" data-align=\"left\">1 bit<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Indicates that new ADC samples are available.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>adc_done_cpu_pulse<\/code><\/td><td class=\"has-text-align-left\" data-align=\"left\">Output<\/td><td class=\"has-text-align-left\" data-align=\"left\">1 bit<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Decimated version of <code>adc_done_pulse<\/code> when a postscaler is used. Set when the CPU control path stages are scheduled to run.<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Description of signals related to the ADC interface<\/figcaption><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">ADC_FLOAT interface<\/h4>\n\n\n\n<p>Available exclusively on the B-Box 4 platform, this interface provides the real physical values in single-precision floating-point format. The rescaling from the raw 16-bit ADC value is configured by setting the sensor sensitivity and offset from the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC<\/a> block. Results from this interface are delayed by 192 ns compared to the 16-bit ADC interface.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_float.svg\" alt=\"\" class=\"wp-image-40193\" style=\"aspect-ratio:3.571511291256514;width:655px;height:auto\"\/><figcaption class=\"wp-element-caption\">Format: 32-bit IEEE 754 single-precision floating-point<\/figcaption><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>ADC_FLOAT_reg_XX<\/code><\/td><td>Output<\/td><td>32bits<\/td><td>clk_250_mhz<\/td><td>ADC floating-point result post rescaling.<br>XX = channel<\/td><\/tr><tr><td><code>adc_done_float_pulse<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Indicates that new ADC_FLOAT samples are available.<\/td><\/tr><tr><td><code>adc_done_cpu_float_pulse<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Decimated version of <code><code>adc_done_float_pulse<\/code><\/code> when a postscaler is used. Set when the CPU task is schedule.<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Description of signals related to the ADC_FLOAT interface<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">SBIO interface<\/h3>\n\n\n\n<p>The <strong>SBIO_BUS <\/strong>(<strong>S<\/strong>and<strong>B<\/strong>ox <strong>IO Bus<\/strong>) is a 16-bit memory-mapped bus allowing the CPU to address up to 1024 registers in the FPGA.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a> block is used to read on the bus (FPGA \u2192 CPU) <\/li>\n\n\n\n<li>The <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> block to write (CPU \u2192 FPGA).<\/li>\n<\/ul>\n\n\n\n<p>Direct interaction with the bus signals is usually not required since the imperix FPGA Sandbox template includes a suite of helper modules that abstract the bus complexity.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128<\/a> further describe how to exchange data between the CPU and the FPGA.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>SBIO_BUS_sb_addr<\/code><\/td><td>Output<\/td><td>10 bits<\/td><td>clk_250_mhz<\/td><td>Address of the accessed register<\/td><\/tr><tr><td><code>SBIO_BUS_sb_we<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Write enable<\/td><\/tr><tr><td><code>SBIO_BUS_sb_wdata<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Write data<\/td><\/tr><tr><td><code>SBIO_BUS_sb_rdata<\/code><\/td><td>Input<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Read data<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Description of the SBIO interface signals<\/figcaption><\/figure>\n\n\n\n<p>The bus performs <strong>read <\/strong>operations by setting the requested address on <code>sb_addr<\/code> and expects the corresponding data on <code>sb_rdata<\/code> exactly four cycles later.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_timing_sbio.svg\" alt=\"\" class=\"wp-image-40195\"\/><figcaption class=\"wp-element-caption\">Read operation<\/figcaption><\/figure>\n\n\n\n<p>A <strong>write<\/strong> occurs on each rising edge of <code>clk <\/code>when <code>sb_we<\/code> is asserted. The target location is given by <code>sb_addr<\/code> and the value written is <code>sb_wdata<\/code>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_timing_sbio_writing.svg\" alt=\"\" class=\"wp-image-40196\"\/><figcaption class=\"wp-element-caption\">Write operation<\/figcaption><\/figure>\n\n\n\n<p>The two additional signals listed below are provided to help synchronize custom logic with the SBIO bus operations:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Signal<\/th><td><strong>Direction<\/strong><\/td><td><strong>Width<\/strong><\/td><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>reading<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Asserted high while data (ADC, SBI, GPI) are being read by the CPU.<\/td><\/tr><tr><td><code>data_valid_pulse<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Single-cycle pulse indicating that all SBO registers have been written for the current CPU control task.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">SB-PWM interface<\/h3>\n\n\n\n<p>The SB-PWM (<strong>S<\/strong>and<strong>B<\/strong>ox-<strong>PWM<\/strong>) interface allows driving PWM outputs directly from custom FPGA logic.<\/p>\n\n\n\n<p>The sandbox PWM inputs (<code>sb_pwm<\/code> port from the imperix IP) are considered as an additional PWM source, equivalently to the output of all built-in modulators. This means that the dead-time generation, activation and protection mechanisms are also available when driving the PWM from the sandbox and are configured from the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-pwm\">SB-PWM<\/a> block.<\/p>\n\n\n\n<p><a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a> further describe how to drive PWM outputs from the FPGA.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>sb_pwm<\/code><\/td><td>Input<\/td><td>48 bits (Gen 4)<br>32 bits (Gen 3)<\/td><td>clk_250_mhz<\/td><td>PWM signals driven from sandbox logic.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">CLOCK interfaces<\/h3>\n\n\n\n<p>The CLOCK interface provides access to the 4 clock generator time bases. The main clock CLOCK_0 is configured via the&nbsp;<a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a>&nbsp;block, CLOCK_1, CLOCK_2 and CLOCK_3 are configured via <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> blocks.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>CLOCK_N_period<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Period of the clock in ticks.<\/td><\/tr><tr><td><code>CLOCK_N_prescaler<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Indicates the <code>CLOCK_N_timer<\/code> ticking rate.<br>1 tick = 4 ns * <code><code>CLOCK_prescaler<\/code><\/code>.<\/td><\/tr><tr><td><code>CLOCK_N_timer<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Timer counting from <code>0<\/code> to&nbsp;<code>CLOCK_period-1<\/code> at the ticking rate set by the <code>CLOCK_N_prescaler<\/code>.<\/td><\/tr><tr><td><code>CLOCK_N_clk_en<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Clock enable pulse indicating when <code>CLOCK_N_timer<\/code> is updated.<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">CLOCK interfaces signal description, with N going from 0 to 3<\/figcaption><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<p>The <strong>prescaler <\/strong>extends the achievable frequency range beyond what the 16-bit period <strong>timer <\/strong>counter alone can provide. With <code>CLOCK_N_prescaler<\/code> = 1, the minimum achievable frequency is approximately 3.8 kHz (250 MHz \/ 65535). For lower frequencies, the <code>CLOCK_N_prescaler<\/code> automatically increases and the firmware tries to closely match the requested frequencies.<\/p>\n\n\n\n<p>Example:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>A frequency of 20 kHz results in <code>CLOCK_prescaler = 1<\/code>&nbsp;and <code>CLOCK_period = 12500 ticks<\/code>.<\/li>\n\n\n\n<li>A frequency of 2 kHz results in <code>CLOCK_prescaler = 2<\/code>&nbsp;and <code>CLOCK_period = 62500 ticks<\/code>.<\/li>\n<\/ul>\n\n\n\n<p><strong>When prescaler = 1:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><code>clk_en <\/code>is asserted every <code>clk_250_mhz <\/code>cycle<\/li>\n\n\n\n<li><code>CLOCK_0_timer<\/code>increments on every clock edge<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_Clock_timing_prescaler_1.svg\" alt=\"\" class=\"wp-image-40215\"\/><figcaption class=\"wp-element-caption\">CLOCK_0 with prescaler = 1<\/figcaption><\/figure>\n\n\n\n<p><strong>When prescaler &gt; 1:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><code>clk_en <\/code>is asserted once every X cycles (where X = prescaler value)<\/li>\n\n\n\n<li><code>CLOCK_0_timer<\/code> increments only when <code>clk_en <\/code>is high<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_Clock_timing_prescaler_2.svg\" alt=\"\" class=\"wp-image-40216\" style=\"aspect-ratio:7.60042251395805;width:787px;height:auto\"\/><figcaption class=\"wp-element-caption\">CLOCK_0 with prescaler = 2<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">GT interfaces<\/h3>\n\n\n\n<p>The Gigabit Transceiver (GT) interface provides access to high-speed serial transceivers connected to the <strong>SFP socked<\/strong> of the controller. This enables custom point-to-point communication with external devices such as other controllers, custom hardware etc.<\/p>\n\n\n\n<p>The <a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\"> Aurora communication<\/a> examples details how to use the Aurora 8B\/10B or Aurora 64B\/66B protocol on imperix controllers.<\/p>\n\n\n\n<p>Examples of SFP communication with third-party hardware-in-the-loop (HIL) simulators (OPAL-RT, Plexim and RTDS) are provided in&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\">SFP communication with third-party devices<\/a>.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Feature<\/th><th>Gen 4<\/th><th>Gen 3<\/th><\/tr><tr><td>Available transceivers<\/td><td>4x GTH (1x QSFP connector, lanes 4\u20137)<\/td><td>3x GTX (3x SFP connectors)<\/td><\/tr><tr><td>Maximum line rate<\/td><td>16.3 Gbps<\/td><td>6.6 Gbps<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Accessing GTH transceivers on Gen 4 controller<\/h4>\n\n\n\n<p>On Gen 4, the QSFP lanes 4\u20137 are currently unassigned and can be used freely from the sandbox without affecting other functionalities. Lanes can be exposed to the sandbox from the <strong>Configuration<\/strong> tab in the imperix firmware IP configuration. Each enabled lane exposes the following signals:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>GT_USER_TX_N_txp<\/code><\/td><td>Output<\/td><td>Transmit positive (differential)<\/td><\/tr><tr><td><code>GT_USER_TX_N_txn<\/code><\/td><td>Output<\/td><td>Transmit negative (differential)<\/td><\/tr><tr><td><code>GT_USER_RX_N_rxp<\/code><\/td><td>Input<\/td><td>Receive positive (differential)<\/td><\/tr><tr><td><code>GT_USER_RX_N_rxn<\/code><\/td><td>Input<\/td><td>Receive negative (differential)<\/td><\/tr><tr><td><code>gt_refclk<\/code><\/td><td>Output<\/td><td>250 MHz reference clock (shared across all lanes)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">GT interface on Gen 4, where N is the lane number (4, 5, 6, or 7)<\/figcaption><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Accessing GTX transceivers on Gen 3 controller<\/h4>\n\n\n\n<p>On Gen 3, the SFP ports are used by default for RealSync inter-device communication. Using a port from the sandbox requires disabling RealSync on that specific link, which removes the inter-device communication capability on that port. Lanes can be exposed to the sandbox from the <strong>Configuration<\/strong> tab in the imperix firmware IP configuration. Each enabled lane exposes the following signals:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>txp_N<\/code><\/td><td>Output<\/td><td>Transmit positive (differential)<\/td><\/tr><tr><td><code>txn_N<\/code><\/td><td>Output<\/td><td>Transmit negative (differential)<\/td><\/tr><tr><td><code>rxp_N<\/code><\/td><td>Input<\/td><td>Receive positive (differential)<\/td><\/tr><tr><td><code>rxn_N<\/code><\/td><td>Input<\/td><td>Receive negative (differential)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Transceiver ports on Gen 3, where N is the lane number. 0 = SFP 0 (UP), 1 = SFP 1 (DOWN 0),  2 = SFP 2 (DOWN 1))<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">Serial port interfaces<\/h3>\n\n\n\n<p>The serial port interfaces are exclusive to the B-Box 4 and are typically used by the pre-implemented&nbsp;<a href=\"https:\/\/imperix.com\/doc\/software\/ssi-digital-encoder-input\">SSI<\/a>,&nbsp;<a href=\"https:\/\/imperix.com\/doc\/software\/biss-angle-encoder-input\">BiSS-C<\/a>&nbsp;and <a href=\"https:\/\/imperix.com\/doc\/software\/endat-digital-encoder-input\">EnDat2.2<\/a> FPGA drivers. The imperix IP allows bypassing these built-in drivers by providing direct access to RS485\/RS422 transceiver signals from the sandbox, as illustrated below.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"840\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware.png\" alt=\"\" class=\"wp-image-40229\" style=\"aspect-ratio:1.2190623714209647;width:481px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware-300x246.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware-768x630.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p>The serial ports (A and\/or B) can be made available from the sandbox from the <strong>Configuration<\/strong> tab in the imperix firmware IP configuration. Each enabled serial port exposes the following signals:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>SERIAL_X_rx<\/code><\/td><td>Input<\/td><td>Receive data from external device<\/td><\/tr><tr><td><code>SERIAL_X_tx<\/code><\/td><td>Output<\/td><td>Transmit data to external device<\/td><\/tr><tr><td><code>SERIAL_X_clk<\/code><\/td><td>Output<\/td><td>Clock signal for synchronous protocols<\/td><\/tr><tr><td><code>SERIAL_X_en<\/code><\/td><td>Output<\/td><td>Transceiver enable (active high)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Serial interface, where X is the port identifier (A or B).<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">BSCAN Interface to observe internal signals using ILA<\/h3>\n\n\n\n<p>The BSCAN (Boundary Scan) interface exposes the FPGA&#8217;s debug scan chain to the sandbox and enables the use of Integrated Logic Analyzers (ILAs) and other Xilinx debug cores. Combined with the Xilinx Virtual Cable (XVC) protocol, this allows remote debugging of internal FPGA signals directly from Vivado&#8217;s Hardware Manager over Ethernet.<\/p>\n\n\n\n<p>For detailed instructions on adding ILAs to your design and connecting to them via XVC, refer to <a href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design?currentThread=going-further-with-fpga-programming\">How to debug an FPGA design<\/a>.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Digital I\/Os drivers<\/h3>\n\n\n\n<p>The sandbox exposes various digital I\/O signals. Some ports are available for user logic, while others are reserved for internal system operation and must not be modified.<\/p>\n\n\n\n<p>For detailed pin locations and electrical specifications, refer to the relevant datasheet:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_4_Datasheet.pdf\">B-Box 4<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_Datasheet.pdf\">B-Box RCP<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_micro_Datasheet.pdf\">B-Box Micro<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Board_Datasheet.pdf\">B-Board PRO<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/TPI8032_Datasheet.pdf\">TPI 8032<\/a> datasheet<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\">The USR pins<\/h4>\n\n\n\n<p>The USR pins are 36 user-configurable 3.3V I\/Os that are routed directly to the FPGA, without any resistor or level shifter on the PCB trace. They used for interfacing external peripherals (e.g., SPI ADC).<\/p>\n\n\n\n<p>To learn more refer to the <a href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\">Accessing the USR pins in the FPGA sandbox<\/a> page.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>USR[35:0]<\/code><\/td><td>Tristate<\/td><td>These pins are used by the <a href=\"https:\/\/imperix.com\/products\/control\/accessories\/#motor-interface\">motor interface<\/a> and the <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">programmable inverter<\/a>. When none of these devices are used, the USR pins can freely be accessed from the sandbox.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Private Ports<\/h4>\n\n\n\n<p>These ports are required for internal communication with controller components. Modifying these connections may cause undefined behaviour.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>private_in<\/code><\/td><td>Input<\/td><td>Internal system signals. Width varies by generation.<\/td><\/tr><tr><td><code>private_out<\/code><\/td><td>Output<\/td><td>Internal system signals. Width varies by generation.<\/td><\/tr><tr><td><code>DDR<\/code><\/td><td>&#8211;<\/td><td>DDR memory interface<\/td><\/tr><tr><td><code>FIXED_IO<\/code><\/td><td>&#8211;<\/td><td>Fixed I\/O interface to PS<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Gen 4 ports<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>din[23:0]<\/code><\/td><td>Input<\/td><td>General-purpose or fault feedback inputs (GPI\/FLT)<\/td><\/tr><tr><td><code>dout[47:0]<\/code><\/td><td>Output<\/td><td>General-purpose outputs or PWM outputs (GPO\/PWM)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">Imperix\u00a0<strong>strongly discourages<\/strong>\u00a0the user from modifying the\u00a0<code>dout<\/code> connection, as this would bypass the protection mechanism! Instead, PWM signals from the sandbox should be routed through the\u00a0<code>sb_pwm<\/code>\u00a0input port.<\/div>\n\n\n\n<h4 class=\"wp-block-heading\">Gen 3 ports<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Clock Domain<\/th><th>Description<\/th><\/tr><tr><td><code>flt[15:0]<\/code><\/td><td>Input<\/td><td>clk_250_mhz<\/td><td>Fault inputs<\/td><\/tr><tr><td><code>gpi[15:0]<\/code><\/td><td>Input<\/td><td>clk_250_mhz<\/td><td>General-purpose inputs<\/td><\/tr><tr><td><code>gpo[15:0]<\/code><\/td><td>Output<\/td><td>clk_250_mhz<\/td><td>General-purpose outputs<\/td><\/tr><tr><td><code>pwm[31:0]<\/code><\/td><td>Output<\/td><td>clk_250_mhz<\/td><td>PWM output signals<\/td><\/tr><tr><td><code>BBOX[51:0]<\/code><\/td><td>Tristate<\/td><td>N\/A<\/td><td>Internal B-Box RCP pins. Can be repurposed on B-Board PRO with custom PCB design (see <a href=\"https:\/\/imperix.com\/doc\/help\/b-board-pro-carrier-board?currentThread=b-board-pro\">PN201<\/a>).<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">Imperix\u00a0<strong>strongly discourages<\/strong>\u00a0the user from modifying the\u00a0<code>pwm<\/code> connection, as this would bypass the protection mechanism! Instead, PWM signals from the sandbox should be routed through the\u00a0<code>sb_pwm<\/code>\u00a0input port.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Disabling-features-to-save-FPGA-resources\"><\/span>Disabling features to save FPGA resources<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>The imperix firmware IP includes several optional features that can be disabled to free up FPGA resources for custom sandbox logic. Access the resource-saving options from the <strong>Saving FPGA resources<\/strong> tab in the imperix firmware IP configuration.<\/p>\n\n\n\n<p>Disabling a feature removes it entirely from the FPGA design. If the corresponding functionality is used in the CPU model, an error will be raised in Cockpit.<\/p>\n\n\n\n<p>Unused PWM modulators can be removed to save logic resources. The CB-PWM logic can be disabled in groups of 8 lanes.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Feature<\/th><th>Gen 4<\/th><th>Gen 3<\/th><\/tr><tr><td>CB-PWM lanes 0\u20137<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 8\u201315<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 16\u201323<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 24\u201331<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 32\u201339<\/td><td>\u2713<\/td><td>\u2014<\/td><\/tr><tr><td>CB-PWM lanes 40\u201347<\/td><td>\u2713<\/td><td>\u2014<\/td><\/tr><tr><td>SS-PWM logic<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>PP-PWM logic<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Resource Savings<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Feature<\/th><th><strong>Gen 4<\/strong><\/th><th><strong>Gen 3<\/strong><\/th><\/tr><tr><td><strong>CB-PWM <\/strong>(per 8 lanes)<\/td><td>~2100 LUTs (0.9%)<br>~2800 Registers (0.6%)<\/td><td>~1600 LUTs (2.03%)<br>~2000 Registers (1.27%)<\/td><\/tr><tr><td><strong>SS-PWM<\/strong><\/td><td>~6250 LUTs (2.71%)<br>~5500 Registers (11.93%)<\/td><td>~2700 LUTs (3.43%)<br>~3300 Registers (2.1%)<\/td><\/tr><tr><td><strong>PP-PWM<\/strong><\/td><td>~4400 LUTs (1.9%)<br>~9200 Registers (2%)<\/td><td>~4400 LUTs (5.6%)<br>~9150 Registers (5.82%)<\/td><\/tr><\/tbody><\/table><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>This page documents the imperix firmware IP for AMD Xilinx Vivado, which is mandatory for programming the FPGA of imperix controllers. The IP encapsulates the&#8230;<\/p>\n","protected":false},"author":4,"featured_media":2995,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,51,110],"guidedreadings":[],"tutorials":[],"user-manuals":[141],"coauthors":[70],"class_list":["post-877","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-cpp-sdk","related-products-tpi","user-manuals-getting-started-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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