{"id":877,"date":"2021-03-26T15:19:05","date_gmt":"2021-03-26T15:19:05","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=877"},"modified":"2026-04-20T12:00:00","modified_gmt":"2026-04-20T12:00:00","slug":"imperix-ip-user-guide","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide","title":{"rendered":"Product guide of the imperix firmware IP"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Architecture-overview\" >Architecture overview<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Execution-timing-signals\" >Execution timing &amp; signals<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Differences-between-Gen-3-and-Gen-4-devices\" >Differences between Gen. 3 and Gen. 4 devices<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Interface-description-of-the-firmware-IP\" >Interface description of the firmware IP<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/imperix-ip-user-guide\/#Disabling-features-to-save-FPGA-resources\" >Disabling features to save FPGA resources<\/a><\/li><\/ul><\/nav><\/div>\n\n<p class=\"wp-block-paragraph\">This page documents the <strong>imperix firmware IP<\/strong> for AMD\/Xilinx Vivado, which is required to program the FPGA of <a href=\"\/products\/power-electronic-controllers\/\">imperix controllers<\/a>. This IP encapsulates the imperix proprietary FPGA logic and offers various interfaces allowing users to add their own custom logic around it.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The document details the different signals provided by this IP, along with their associated timings. Separate documentation exists for specific interfaces, as listed in the table below: <\/p>\n\n\n<style>.wp-block-kadence-spacer.kt-block-spacer-877_a1070e-a2 .kt-block-spacer{height:20px;}.wp-block-kadence-spacer.kt-block-spacer-877_a1070e-a2 .kt-divider{border-top-width:1px;height:1px;border-top-color:#eee;width:80%;border-top-style:solid;}<\/style>\n<div class=\"wp-block-kadence-spacer aligncenter kt-block-spacer-877_a1070e-a2\"><div class=\"kt-block-spacer kt-block-spacer-halign-center\"><hr class=\"kt-divider\"\/><\/div><\/div>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td><strong>Interface<\/strong><\/td><td><strong>Feature<\/strong>\/objective<\/td><td><strong>Product&nbsp;note<\/strong><\/td><\/tr><tr><td>ADC<\/td><td>Retrieving ADC conversion results as soon as they are available.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126<\/a><\/td><\/tr><tr><td>SBIO<\/td><td>Exchanging data between the user code running in the CPU and the FPGA.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128<\/a><\/td><\/tr><tr><td>SB-PWM<\/td><td>Driving the PWM output chain, comprised of a dead-time generation system and the hardware protection mechanisms.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a><\/td><\/tr><tr><td>USR<\/td><td>Accessing physical 3V3 I\/O pins.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\">PN179<\/a><\/td><\/tr><tr><td>GT<\/td><td>Accessing Gigabit Transceivers (GT), enabling support of protocols such as Aurora on SFP ports.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">PN118<\/a><\/td><\/tr><tr><td>BSCAN<\/td><td>Using ILAs to observe FPGA signals in real-time for debugging purposes.<\/td><td><a href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design\">PN129<\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-top is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-top is-layout-flow wp-block-column-is-layout-flow\">\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"430\" height=\"648\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_imperix_fw_ip.png\" alt=\"\" class=\"wp-image-40175\" style=\"aspect-ratio:0.6635902168897093;width:303px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_imperix_fw_ip.png 430w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_imperix_fw_ip-199x300.png 199w\" sizes=\"auto, (max-width: 430px) 100vw, 430px\" \/><figcaption class=\"wp-element-caption\">imperix firmware IP<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">For developers beginning a new design, the <a href=\"https:\/\/imperix.com\/doc\/help\/getting-started-with-fpga-control-development\">getting-started guide<\/a> for FPGA-based development provides step-by-step instructions for creating the project and starting in Vivado.<\/div>\n\n\n\n<h2 id=\"Overview\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Architecture-overview\"><\/span>Architecture overview<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Because FPGA development operates at the hardware level, a thorough understanding of the underlying system architecture and real-time execution behavior is essential for successfully integrating custom logic into the FPA of an imperix controller.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The article <a href=\"\/doc\/help\/architecture-of-imperix-controllers\">PN253<\/a> presents the <strong>architecture of imperix controllers<\/strong>, explains their main data paths, and introduces the key subsystems. Fundamental information regarding how the controllers manage control-relevant clocks and timing is also provided.<\/li>\n\n\n\n<li>The article <a href=\"\/doc\/help\/operating-principles-of-imperix-controllers\">PN261<\/a> explains <strong>how imperix controllers operate<\/strong> and details the typical sequence of acquisition \u2192 processing \u2192 modulation through the user-programmable CPU. Information is also provided about the core operating states and the related enabling\/disabling of PWM outputs.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">Imperix actively supports two controller generations, both based on AMD Xilinx System-on-Chips (SoCs):<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Gen 3<\/strong> controllers (<a href=\"https:\/\/imperix.com\/products\/control\/rapid-prototyping-controller\/\">B-Box 3<\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/power-inverter-controller\/\">B-Box Micro<\/a>, <a href=\"https:\/\/imperix.com\/products\/control\/inverter-control-board\/\">B-Board PRO<\/a>, <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">TPI8032<\/a>) are based on an <strong>AMD Zynq&nbsp;7000<\/strong><\/li>\n\n\n\n<li><strong>Gen 4<\/strong> controller (<a href=\"https:\/\/imperix.com\/products\/control\/rcp-controller\/\">B-Box 4<\/a>) is based on an <strong>AMD<strong> <\/strong>Zynq Ultrascale+<\/strong><\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">While the specifics (number of CPUs, clock speeds, FPGA resources, etc.) vary between the generations, the operating principles and control workflow are identical. The global architecture is also similar, as shown below:<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"528\" height=\"506\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-353.png\" alt=\"\" class=\"wp-image-44098\" style=\"aspect-ratio:1.0434796034956613;width:464px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-353.png 528w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-353-300x288.png 300w\" sizes=\"auto, (max-width: 528px) 100vw, 528px\" \/><figcaption class=\"wp-element-caption\">Architecture of imperix controllers (elements common to Gen. 3 and Gen. 4)<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">The core modules contained within the imperix firmware IP are:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The <strong>data acquisition<\/strong> <strong>module<\/strong> (documented in <a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126<\/a>)  pilots the ADC chips and makes the analog input measurement available to both the CPU user app and the user-programmable FPGA area.<\/li>\n\n\n\n<li>The <strong>pulse-width modulation<\/strong> (documented in <a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a>) contains the pre-implemented PWM modulators (<a href=\"https:\/\/imperix.com\/doc\/software\/carrier-based-pwm\">CB<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/sv-pwm\">SV<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/direct-output-pwm\">DO<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/sort-select-multilevel-pwm\">SS<\/a>, <a href=\"https:\/\/imperix.com\/doc\/software\/programmed-pattern-pwm\">PP<\/a>). It allows driving the PWM outputs from a custom modulator using the SB-PWM path.<\/li>\n\n\n\n<li>The <strong>CLK <\/strong>module manages the main clock CLK0 (configured via the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> block) and the optional CLK1, CLK2 and CLK3 (configured via <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> block).<\/li>\n\n\n\n<li>The <strong>DMA<\/strong> is responsible for transferring the data between the FPGA and the CPU <strong>read\/write buffers<\/strong>. The <em>read<\/em> and <em>write<\/em> phases are detailed in the next section.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Execution-timing-signals\"><\/span>Execution timing &amp; signals<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The following figures illustrate the key phases involved along the <strong>CPU control path<\/strong>. These are detailed in <a href=\"\/doc\/help\/operating-principles-of-imperix-controllers\">PN261<\/a>, and summarized below:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Acquisition<\/strong>: covers the physical Analog-to-Digital conversion and data retrieval to the FPGA fabric.<\/li>\n\n\n\n<li><strong>Read<\/strong>: represents the data transfer from the FPGA to the CPU read buffer.<\/li>\n\n\n\n<li><strong>CPU task<\/strong>: contains the execution of the main control task (user-defined control algorithms).<\/li>\n\n\n\n<li><strong>Write<\/strong>: represents the data transfer from the CPU write buffer to the FPGA.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">Interestingly, a second data path exists, associated with the <strong>FPGA task<\/strong>, that permits control algorithms to be fully executed on the FPGA, as in the control example presented in <a href=\"https:\/\/imperix.com\/doc\/implementation\/fpga-based-inverter-control\">TN147<\/a>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"545\" height=\"452\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-352.png\" alt=\"\" class=\"wp-image-44082\" style=\"width:497px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-352.png 545w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-352-300x249.png 300w\" sizes=\"auto, (max-width: 545px) 100vw, 545px\" \/><figcaption class=\"wp-element-caption\">Phases of the CPU and FPGA control paths<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">On the PL side (FPGA), the imperix firmware IP provides several signals to monitor and synchronize logic during the execution of these phases.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"633\" height=\"284\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-342.png\" alt=\"\" class=\"wp-image-42997\" style=\"width:535px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-342.png 633w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-342-300x135.png 300w\" sizes=\"auto, (max-width: 633px) 100vw, 633px\" \/><figcaption class=\"wp-element-caption\">Timing signals related to the CPU control path<\/figcaption><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th class=\"has-text-align-left\" data-align=\"left\">Port name<\/th><td><strong>Clk domain<\/strong><\/td><th class=\"has-text-align-left\" data-align=\"left\">Description<\/th><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code><code>sampling_pulse<\/code><\/code><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Indicates the ADC sampling instant and the start of the&nbsp;<strong>acquisition<\/strong> phase. Corresponds to the rising edge of the sampling clock <strong>SCLK<\/strong>.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code><code>adc_done_pulse<\/code>&nbsp;<\/code><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Indicates that the <strong>acquisition<\/strong> phase is finished and new ADC values are available at the&nbsp;<code>ADC<\/code>&nbsp;interface.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>adc_done_cpu_pulse<\/code><strong>&nbsp;<\/strong><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">When the sampling rate differs from the CPU rate, this signal is a decimated version of <strong><code>adc_done_pulse<\/code><\/strong>. It is set when the CPU control path stages are scheduled to execute. The following section describes this scenario in more detail.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code><code>reading<\/code><strong>&nbsp;<\/strong><\/code><\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Indicates that the system is in the&nbsp;<strong>read&nbsp;<\/strong>phase, in which data flagged as real-time (SBI registers, ADC, GPI, etc.) are sent to the CPU read buffer.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>data_valid_pulse<\/code>&nbsp;<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Asserted at the end of the <strong>write<\/strong> phase, notifying that new data were written (SBO registers, PWM duty-cycles, GPO, etc.).<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">Handling different execution rates<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">FPGA-based control algorithms are often desired to execute at a higher rate than the CPU. In such cases, a <strong>postscaler <\/strong>can be configured in the <a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a> block to reduce the CPU rate relative to the sampling frequency. Then, the&nbsp;<strong><code>adc_done_cpu_pulse<\/code>&nbsp;<\/strong>acts as the decimated version of <strong><code>adc_done_pulse<\/code><\/strong>. It is asserted when the CPU control path stages are scheduled to run.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"633\" height=\"404\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-343.png\" alt=\"\" class=\"wp-image-42998\" style=\"width:525px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-343.png 633w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-343-300x191.png 300w\" sizes=\"auto, (max-width: 633px) 100vw, 633px\" \/><figcaption class=\"wp-element-caption\">Execution timing with postscaler = 4<\/figcaption><\/figure>\n<\/div>\n\n\n<h2 id=\"Differences-between-Gen-3-and-Gen-4-for-FPGA-development\" class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Differences-between-Gen-3-and-Gen-4-devices\"><\/span>Differences between Gen. 3 and Gen. 4 devices<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">For FPGA development, the B-Box 4 offers several key enhancements over its predecessors, such as access to analog measurements in floating-point format, faster transceivers, and expanded FPGA resources. The table below summarizes the key differences between the two generations.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td class=\"has-text-align-left\" data-align=\"left\"><strong>Component<\/strong><\/td><td class=\"has-text-align-left\" data-align=\"left\"><strong>Gen 3<\/strong><\/td><td class=\"has-text-align-left\" data-align=\"left\"><strong>Gen 4<\/strong><\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">FPGA<\/td><td class=\"has-text-align-left\" data-align=\"left\">Kintex 7 125K<\/td><td class=\"has-text-align-left\" data-align=\"left\">Kintex US+ 504K<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Logic<\/td><td class=\"has-text-align-left\" data-align=\"left\">LUTs: 78600<br>Registers: 157200<\/td><td class=\"has-text-align-left\" data-align=\"left\">LUTs: 230400<br>Registers: 460800<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Logic used by imperix IP*<\/td><td class=\"has-text-align-left\" data-align=\"left\">min:<br>LUTs: 25482 (32.4%)<br>Registers: 46374 (29.5%)<br><br>max:<br>LUTs: 39143 (49.8%)<br>Registers: 67203 (42.7%)<\/td><td class=\"has-text-align-left\" data-align=\"left\">min:<br>LUTs 70733 (30.7%)<br>Registers 108749 (23.6%)<br><br>max:<br>LUTs: 94233 (40.9%)<br>Registers: 140636 (30.5%)<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Usable logic left*<\/td><td class=\"has-text-align-left\" data-align=\"left\">max:<br>LUTs: 53118 (67.6%)<br>Registers: 110826 (70.5%)<br><br>min:<br>LUTs: 39457 (50.2%)<br>Registers: 89997 (57.3%)<\/td><td class=\"has-text-align-left\" data-align=\"left\">max:<br>LUTs: 159667 (69.3%)<br>Registers: 352051 (76.4%)<br><br>min:<br>LUTs: 136167 (59.1%)<br>Registers: 320164 (60.5%)<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Gigabit Transceivers available from the sandbox<\/td><td class=\"has-text-align-left\" data-align=\"left\">3x GTX (3x SFP connectors)<br>Up to 6.6 Gbps<\/td><td class=\"has-text-align-left\" data-align=\"left\">4x GTH (1x QSFP connector)<br>Up to 16.3 Gbps<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Bidirectional direct FPGA I\/Os (USR)<\/td><td class=\"has-text-align-left\" data-align=\"left\">36x<\/td><td class=\"has-text-align-left\" data-align=\"left\">36x<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">PWM outputs<\/td><td class=\"has-text-align-left\" data-align=\"left\">32x<\/td><td class=\"has-text-align-left\" data-align=\"left\">48x<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">ADC interface<\/td><td class=\"has-text-align-left\" data-align=\"left\">16x (int16)<\/td><td class=\"has-text-align-left\" data-align=\"left\">24x (int16, or float)<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">RS485\/RS422<\/td><td class=\"has-text-align-left\" data-align=\"left\">&#8211;<\/td><td class=\"has-text-align-left\" data-align=\"left\">&nbsp;2x<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\">Acquisition delay<\/td><td class=\"has-text-align-left\" data-align=\"left\">2 \u03bcs (B-Box RCP 3.0)<br>500 ns (B-Box Micro, B-Board, TPI8032)<\/td><td class=\"has-text-align-left\" data-align=\"left\">&nbsp;200 ns \/ 368 ns**<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">* The logic used by the imperix IP depends on the enabled features, as explained in the <em>Disabling Features to Save FPGA Resources<\/em> section.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">** When channels A12-A23 are used.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Interface-description-of-the-firmware-IP\"><\/span>Interface description of the firmware IP<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 id=\"ADC-interface-to-retrieve-analog-measurements\" class=\"wp-block-heading\">ADC interface<\/h3>\n\n\n\n<p class=\"has--font-size wp-block-paragraph\">The&nbsp;ADC<strong>&nbsp;<\/strong>interface returns the raw&nbsp;16-bit signed integer&nbsp;result from the ADC chips. Practical guidance for retrieving data from ADCs is provided in <a href=\"https:\/\/imperix.com\/doc\/help\/retrieving-adc-measurements-from-the-fpga\">PN126<\/a>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_fixed16_0.svg\" alt=\"\" class=\"wp-image-40187\" style=\"aspect-ratio:3.5716919585874343;width:647px;height:auto\"\/><figcaption class=\"wp-element-caption\">Format: 16-bit signed integer (two&#8217;s complement, range: -32768 to +32767)<\/figcaption><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th class=\"has-text-align-left\" data-align=\"left\">Port Name<\/th><th class=\"has-text-align-left\" data-align=\"left\">Direction<\/th><th class=\"has-text-align-left\" data-align=\"left\">Width<\/th><td><strong>Clk domain<\/strong><\/td><th class=\"has-text-align-left\" data-align=\"left\">Description<\/th><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>ADC_reg_XX<\/code><\/td><td class=\"has-text-align-left\" data-align=\"left\">Output<\/td><td class=\"has-text-align-left\" data-align=\"left\">16bits<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">ADC 16-bit result in 2\u2019s complement format.<br>XX = channel<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>adc_done_pulse<\/code><\/td><td class=\"has-text-align-left\" data-align=\"left\">Output<\/td><td class=\"has-text-align-left\" data-align=\"left\">1 bit<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Indicates that new ADC samples are available.<\/td><\/tr><tr><td class=\"has-text-align-left\" data-align=\"left\"><code>adc_done_cpu_pulse<\/code><\/td><td class=\"has-text-align-left\" data-align=\"left\">Output<\/td><td class=\"has-text-align-left\" data-align=\"left\">1 bit<\/td><td>clk_250_mhz<\/td><td class=\"has-text-align-left\" data-align=\"left\">Decimated version of <code>adc_done_pulse<\/code> when a postscaler is used. Set when the CPU control path stages are scheduled to run.<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Description of signals related to the ADC interface<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">ADC_FLOAT interface<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Available exclusively on the B-Box 4, this interface provides access to the true physical values, in single-precision floating-point format, as they are available at the end of the ADC signal chain. The rescaling from the raw 16-bit ADC value is configured by setting the sensor sensitivity and offset from the <a href=\"https:\/\/imperix.com\/doc\/software\/analog-data-acquisition\">ADC<\/a> block.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_float.svg\" alt=\"\" class=\"wp-image-40193\" style=\"aspect-ratio:3.571511291256514;width:655px;height:auto\"\/><figcaption class=\"wp-element-caption\">Format: 32-bit IEEE 754 single-precision floating-point<\/figcaption><\/figure>\n<\/div>\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>ADC_FLOAT_reg_XX<\/code><\/td><td>Output<\/td><td>32bits<\/td><td>clk_250_mhz<\/td><td>ADC floating-point result post rescaling.<br>XX = channel<\/td><\/tr><tr><td><code>adc_done_float_pulse<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Indicates that new ADC_FLOAT samples are available.<\/td><\/tr><tr><td><code>adc_done_cpu_float_pulse<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Decimated version of <code><code>adc_done_float_pulse<\/code><\/code> when a postscaler is used. Set when the CPU task is scheduled.<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Description of signals related to the ADC_FLOAT interface<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">SBIO interface<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The <strong>SBIO_BUS <\/strong>(<strong>S<\/strong>and<strong>B<\/strong>ox <strong>IO Bus<\/strong>) is a 16-bit memory-mapped bus allowing the CPU to address up to 1024 registers in the FPGA. This bus is dedicated to user-configured data exchanges between the CPU and the FPGA. Its Simulink\/PLECS counterparts are the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-input-from-fpga\">SBI<\/a>\/<a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-output-towards-fpga\">SBO<\/a> blocks. Specific documentation is provided in <a href=\"https:\/\/imperix.com\/doc\/help\/exchanging-data-between-the-cpu-and-the-fpga\">PN128<\/a>. <\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>SBIO_BUS_sb_addr<\/code><\/td><td>Output<\/td><td>10 bits<\/td><td>clk_250_mhz<\/td><td>Address of the accessed register<\/td><\/tr><tr><td><code>SBIO_BUS_sb_we<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Write enable<\/td><\/tr><tr><td><code>SBIO_BUS_sb_wdata<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Write data<\/td><\/tr><tr><td><code>SBIO_BUS_sb_rdata<\/code><\/td><td>Input<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Read data<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Description of the SBIO interface signals<\/figcaption><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">The bus performs <strong>read <\/strong>operations by setting the requested address on <code>sb_addr<\/code> and expects the corresponding data on <code>sb_rdata<\/code> exactly four cycles later.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_timing_sbio.svg\" alt=\"\" class=\"wp-image-40195\"\/><figcaption class=\"wp-element-caption\">Read operation<\/figcaption><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">A <strong>write<\/strong> occurs on each rising edge of <code>clk <\/code>when <code>sb_we<\/code> is asserted. The target location is given by <code>sb_addr<\/code> and the value written is <code>sb_wdata<\/code>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_timing_sbio_writing.svg\" alt=\"\" class=\"wp-image-40196\"\/><figcaption class=\"wp-element-caption\">Write operation<\/figcaption><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">The two additional signals listed below are provided to help synchronize custom logic with the SBIO bus operations:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Signal<\/th><td><strong>Direction<\/strong><\/td><td><strong>Width<\/strong><\/td><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>reading<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Asserted high while data (ADC, SBI, GPI) are being read by the CPU.<\/td><\/tr><tr><td><code>data_valid_pulse<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Single-cycle pulse indicating that all SBO registers have been written for the current CPU control task.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">SB-PWM interface<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The SB-PWM (<strong>S<\/strong>and<strong>B<\/strong>ox-<strong>PWM<\/strong>) interface allows PWM outputs to be driven from custom FPGA logic while still benefiting from the controller&#8217;s <a href=\"\/doc\/help\/hardware-protections-on-imperix-controllers\">hardware protections<\/a>. Additionally, when using the SB-PWM interface, users also benefit from existing dead-time generation and enable\/disable mechanisms similar to driving PWMs from the <a href=\"https:\/\/imperix.com\/doc\/software\/sandbox-pwm\">SB-PWM<\/a> block (or similar). This interface is further documented in <a href=\"https:\/\/imperix.com\/doc\/help\/driving-pwm-outputs-from-the-fpga\">PN127<\/a>.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>sb_pwm<\/code><\/td><td>Input<\/td><td>48 bits (Gen 4)<br>32 bits (Gen 3)<\/td><td>clk_250_mhz<\/td><td>PWM signals driven from sandbox logic.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">CLOCK interfaces<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The CLOCK interface provides access to the four user-configurable time clock generators. More information about these resources is provided in <a href=\"\/doc\/help\/architecture-of-imperix-controllers\">PN253<\/a>. Typical timing configurations are also presented in <a href=\"\/doc\/help\/timing-configuration-on-imperix-controllers\">PN259<\/a>. On the practical side:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The main clock CLOCK_0 must be configured via the&nbsp;<a href=\"https:\/\/imperix.com\/doc\/software\/config-control-task-configuration\">CONFIG<\/a>&nbsp;block<\/li>\n\n\n\n<li>The auxiliary clocks, CLOCK_1, CLOCK_2 and CLOCK_3 must be configured via the <a href=\"https:\/\/imperix.com\/doc\/software\/clock-generators\">CLK<\/a> blocks.<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Width<\/th><td><strong>Clk domain<\/strong><\/td><th>Description<\/th><\/tr><tr><td><code>CLOCK_N_period<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Period of the clock in ticks.<\/td><\/tr><tr><td><code>CLOCK_N_prescaler<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Indicates the <code>CLOCK_N_timer<\/code> ticking rate.<br>1 tick = 4 ns * <code><code>CLOCK_prescaler<\/code><\/code>.<\/td><\/tr><tr><td><code>CLOCK_N_timer<\/code><\/td><td>Output<\/td><td>16 bits<\/td><td>clk_250_mhz<\/td><td>Timer counting from <code>0<\/code> to&nbsp;<code>CLOCK_period-1<\/code> at the ticking rate set by the <code>CLOCK_N_prescaler<\/code>.<\/td><\/tr><tr><td><code>CLOCK_N_clk_en<\/code><\/td><td>Output<\/td><td>1 bit<\/td><td>clk_250_mhz<\/td><td>Clock enable pulse indicating when <code>CLOCK_N_timer<\/code> is updated.<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">CLOCK interfaces signal description, with N going from 0 to 3<\/figcaption><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">Interestingly, the <strong>prescaler <\/strong>extends the achievable frequency range beyond what the 16-bit period <strong>timer <\/strong>counter alone can provide. With <code>CLOCK_N_prescaler<\/code> = 1, the minimum achievable frequency is approximately 3.8 kHz (250 MHz \/ 65535). For lower frequencies, the <code>CLOCK_N_prescaler<\/code> automatically increases, and the firmware tries to closely match the requested frequencies.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Example:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>A frequency of 20 kHz results in <code>CLOCK_prescaler = 1<\/code>&nbsp;and <code>CLOCK_period = 12500 ticks<\/code>.<\/li>\n\n\n\n<li>A frequency of 2 kHz results in <code>CLOCK_prescaler = 2<\/code>&nbsp;and <code>CLOCK_period = 62500 ticks<\/code>.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>When prescaler = 1:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><code>clk_en <\/code>is asserted every <code>clk_250_mhz <\/code>cycle<\/li>\n\n\n\n<li><code>CLOCK_0_timer<\/code>increments on every clock edge<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_Clock_timing_prescaler_1.svg\" alt=\"\" class=\"wp-image-40215\"\/><figcaption class=\"wp-element-caption\">CLOCK_0 with prescaler = 1<\/figcaption><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>When prescaler &gt; 1:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><code>clk_en <\/code>is asserted once every X cycles (where X = prescaler value)<\/li>\n\n\n\n<li><code>CLOCK_0_timer<\/code> increments only when <code>clk_en <\/code>is high<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img decoding=\"async\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_Clock_timing_prescaler_2.svg\" alt=\"\" class=\"wp-image-40216\" style=\"aspect-ratio:7.60042251395805;width:787px;height:auto\"\/><figcaption class=\"wp-element-caption\">CLOCK_0 with prescaler = 2<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">GT interfaces<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The Gigabit Transceiver (GT) interface provides access to high-speed serial transceivers connected to the <strong>SFP+, respectively QSFP+ sockets<\/strong>. This enables custom point-to-point communication with external devices such as other controllers, custom hardware etc.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><a href=\"\/doc\/help\/example-of-fpga-based-aurora-8b-10b-communication\">PN118<\/a> is an example setting up loopback communication using Xilinx\/AMD Aurora as a communication protocol. Additional examples with third-party hardware-in-the-loop (HIL) simulators (OPAL-RT, Plexim and RTDS) are provided on the page&nbsp;<a href=\"https:\/\/imperix.com\/doc\/help\/sfp-communication-with-third-party-devices\">SFP communication with third-party devices<\/a>.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Feature<\/th><th>Gen 4<\/th><th>Gen 3<\/th><\/tr><tr><td>Available transceivers<\/td><td>4x GTH (1x QSFP connector, lanes 4\u20137)<\/td><td>3x GTX (3x SFP connectors)<\/td><\/tr><tr><td>Maximum line rate<\/td><td>16.3 Gbps<\/td><td>6.6 Gbps<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Accessing GTH transceivers on Gen 4 controller<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">On Gen 4, lanes can be exposed to the sandbox from the <strong>Configuration<\/strong> tab in the imperix firmware IP configuration. Each enabled lane exposes the following signals:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>GT_USER_TX_N_txp<\/code><\/td><td>Output<\/td><td>Transmit positive (differential)<\/td><\/tr><tr><td><code>GT_USER_TX_N_txn<\/code><\/td><td>Output<\/td><td>Transmit negative (differential)<\/td><\/tr><tr><td><code>GT_USER_RX_N_rxp<\/code><\/td><td>Input<\/td><td>Receive positive (differential)<\/td><\/tr><tr><td><code>GT_USER_RX_N_rxn<\/code><\/td><td>Input<\/td><td>Receive negative (differential)<\/td><\/tr><tr><td><code>gt_refclk<\/code><\/td><td>Output<\/td><td>250 MHz reference clock (shared across all lanes)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">GT interface on Gen 4, where N is the lane number (4, 5, 6, or 7)<\/figcaption><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Accessing GTX transceivers on Gen 3 controller<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">On Gen 3, the SFP ports are used by default for RealSync inter-device communication. Using a port from the sandbox requires disabling RealSync on that specific link, which removes the inter-device communication capability on that port. Lanes can be exposed to the sandbox from the <strong>Configuration<\/strong> tab in the imperix firmware IP configuration. Each enabled lane exposes the following signals:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>txp_N<\/code><\/td><td>Output<\/td><td>Transmit positive (differential)<\/td><\/tr><tr><td><code>txn_N<\/code><\/td><td>Output<\/td><td>Transmit negative (differential)<\/td><\/tr><tr><td><code>rxp_N<\/code><\/td><td>Input<\/td><td>Receive positive (differential)<\/td><\/tr><tr><td><code>rxn_N<\/code><\/td><td>Input<\/td><td>Receive negative (differential)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Transceiver ports on Gen 3, where N is the lane number. 0 = SFP 0 (UP), 1 = SFP 1 (DOWN 0),  2 = SFP 2 (DOWN 1))<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">Serial port interfaces<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The serial port interfaces are exclusive to the B-Box 4 and are typically used by the pre-implemented&nbsp;<a href=\"https:\/\/imperix.com\/doc\/software\/ssi-digital-encoder-input\">SSI<\/a>,&nbsp;<a href=\"https:\/\/imperix.com\/doc\/software\/biss-angle-encoder-input\">BiSS-C<\/a>&nbsp;and <a href=\"https:\/\/imperix.com\/doc\/software\/endat-digital-encoder-input\">EnDat2.2<\/a> FPGA drivers. The imperix IP allows bypassing these built-in drivers by providing direct access to RS485\/RS422 transceiver signals from the sandbox, as illustrated below.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"840\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware.png\" alt=\"\" class=\"wp-image-40229\" style=\"aspect-ratio:1.2190623714209647;width:347px;height:auto\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware.png 1024w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware-300x246.png 300w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/PN116_serial_hardware-768x630.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">The serial ports (A and\/or B) can be made available from the sandbox from the <strong>Configuration<\/strong> tab in the imperix firmware IP configuration. Each enabled serial port exposes the following signals:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>SERIAL_X_rx<\/code><\/td><td>Input<\/td><td>Receive data from external device<\/td><\/tr><tr><td><code>SERIAL_X_tx<\/code><\/td><td>Output<\/td><td>Transmit data to external device<\/td><\/tr><tr><td><code>SERIAL_X_clk<\/code><\/td><td>Output<\/td><td>Clock signal for synchronous protocols<\/td><\/tr><tr><td><code>SERIAL_X_en<\/code><\/td><td>Output<\/td><td>Transceiver enable (active high)<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Serial interface, where X is the port identifier (A or B).<\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">BSCAN Interface to observe internal signals using ILA<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The BSCAN (Boundary Scan) interface exposes the FPGA&#8217;s debug scan chain to the sandbox and enables the use of Integrated Logic Analyzers (ILAs) and other Xilinx debug cores. When combined with the Xilinx Virtual Cable (XVC) protocol, this allows remote debugging of internal FPGA signals directly from Vivado&#8217;s Hardware Manager over Ethernet.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">For detailed instructions on adding ILAs to your design and connecting to them via XVC, refer to <a href=\"https:\/\/imperix.com\/doc\/help\/how-to-debug-an-fpga-design?currentThread=going-further-with-fpga-programming\">PN129<\/a>.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Digital I\/Os drivers<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The sandbox exposes various digital I\/O signals. Some ports are available for user logic, while others are reserved for internal system operation and must not be modified. For detailed pin locations and electrical specifications, refer to the relevant datasheet:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_4_Datasheet.pdf\">B-Box 4<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_Datasheet.pdf\">B-Box RCP<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Box_micro_Datasheet.pdf\">B-Box Micro<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/B-Board_Datasheet.pdf\">B-Board PRO<\/a> datasheet<\/li>\n\n\n\n<li><a href=\"https:\/\/imperix.com\/wp-content\/uploads\/document\/TPI8032_Datasheet.pdf\">TPI 8032<\/a> datasheet<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\">The USR pins<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">The USR pins are 36 user-configurable 3.3V I\/Os routed directly to the FPGA, without any resistors or level shifters on the PCB traces. These pins are typically used for interfacing external peripherals (e.g., SPI ADC) but can, in fact, be leveraged for a very broad range of applications, thanks to their bidirectionality and high bandwidth.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"> More information about accessing USR pins is provided in <a href=\"\/doc\/help\/access-the-usr-pins-in-the-fpga-sandbox\">PN179<\/a>.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>USR[35:0]<\/code><\/td><td>Tristate<\/td><td>These pins are used by the <a href=\"https:\/\/imperix.com\/products\/control\/accessories\/#motor-interface\">motor interface<\/a> and the <a href=\"https:\/\/imperix.com\/products\/power\/programmable-inverter\/\">programmable inverter<\/a>. When none of these devices are in use, the USR pins can freely be accessed from the sandbox.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Private Ports<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">These ports are required for internal communication with controller components and are reserved for imperix use. Modifying these connections may cause undefined behavior and must be absolutely avoided.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>private_in<\/code><\/td><td>Input<\/td><td>Internal system signals. Width varies by generation.<\/td><\/tr><tr><td><code>private_out<\/code><\/td><td>Output<\/td><td>Internal system signals. Width varies by generation.<\/td><\/tr><tr><td><code>DDR<\/code><\/td><td>&#8211;<\/td><td>DDR memory interface<\/td><\/tr><tr><td><code>FIXED_IO<\/code><\/td><td>&#8211;<\/td><td>Fixed I\/O interface to PS<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Gen 4 ports<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Description<\/th><\/tr><tr><td><code>din[23:0]<\/code><\/td><td>Input<\/td><td>General-purpose or fault feedback inputs (GPI\/FLT)<\/td><\/tr><tr><td><code>dout[47:0]<\/code><\/td><td>Output<\/td><td>General-purpose outputs or PWM outputs (GPO\/PWM)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">Imperix\u00a0<strong>strongly discourages<\/strong>\u00a0the user from modifying the\u00a0<code>dout<\/code> connection, as this would bypass the protection mechanism! Instead, PWM signals should always be routed through the\u00a0<code>sb_pwm<\/code>\u00a0input port.<\/div>\n\n\n\n<h4 class=\"wp-block-heading\">Gen 3 ports<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Port Name<\/th><th>Direction<\/th><th>Clock Domain<\/th><th>Description<\/th><\/tr><tr><td><code>flt[15:0]<\/code><\/td><td>Input<\/td><td>clk_250_mhz<\/td><td>Fault inputs<\/td><\/tr><tr><td><code>gpi[15:0]<\/code><\/td><td>Input<\/td><td>clk_250_mhz<\/td><td>General-purpose inputs<\/td><\/tr><tr><td><code>gpo[15:0]<\/code><\/td><td>Output<\/td><td>clk_250_mhz<\/td><td>General-purpose outputs<\/td><\/tr><tr><td><code>pwm[31:0]<\/code><\/td><td>Output<\/td><td>clk_250_mhz<\/td><td>PWM output signals<\/td><\/tr><tr><td><code>BBOX[51:0]<\/code><\/td><td>Tristate<\/td><td>N\/A<\/td><td>Internal B-Box RCP pins. Can be repurposed on B-Board PRO with custom PCB design (see <a href=\"https:\/\/imperix.com\/doc\/help\/b-board-pro-carrier-board?currentThread=b-board-pro\">PN201<\/a>).<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-warning\" role=\"alert\">Imperix\u00a0<strong>strongly discourages<\/strong>\u00a0the user from modifying the\u00a0<code>dout<\/code> connection, as this would bypass the protection mechanism! Instead, PWM signals should always be routed through the\u00a0<code>sb_pwm<\/code>\u00a0input port.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Disabling-features-to-save-FPGA-resources\"><\/span>Disabling features to save FPGA resources<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The imperix firmware IP includes several optional features that can be disabled to free up FPGA resources for custom sandbox logic. Access the resource-saving options from the <strong>Saving FPGA resources<\/strong> tab in the imperix firmware IP configuration.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Disabling a feature removes it entirely from the FPGA design. If the corresponding functionality is used in the CPU model, an error will be raised in Cockpit. Additionally, unused modulators can be removed to save logic resources. Notably, the CB-PWM logic can be disabled in groups of 8 lanes.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Feature<\/th><th>Gen 4<\/th><th>Gen 3<\/th><\/tr><tr><td>CB-PWM lanes 0\u20137<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 8\u201315<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 16\u201323<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 24\u201331<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>CB-PWM lanes 32\u201339<\/td><td>\u2713<\/td><td>\u2014<\/td><\/tr><tr><td>CB-PWM lanes 40\u201347<\/td><td>\u2713<\/td><td>\u2014<\/td><\/tr><tr><td>SS-PWM logic<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><tr><td>PP-PWM logic<\/td><td>\u2713<\/td><td>\u2713<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">Resource Savings<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Feature<\/th><th><strong>Gen 4<\/strong><\/th><th><strong>Gen 3<\/strong><\/th><\/tr><tr><td><strong>CB-PWM <\/strong>(per 8 lanes)<\/td><td>~2100 LUTs (0.9%)<br>~2800 Registers (0.6%)<\/td><td>~1600 LUTs (2.03%)<br>~2000 Registers (1.27%)<\/td><\/tr><tr><td><strong>SS-PWM<\/strong><\/td><td>~6250 LUTs (2.71%)<br>~5500 Registers (11.93%)<\/td><td>~2700 LUTs (3.43%)<br>~3300 Registers (2.1%)<\/td><\/tr><tr><td><strong>PP-PWM<\/strong><\/td><td>~4400 LUTs (1.9%)<br>~9200 Registers (2%)<\/td><td>~4400 LUTs (5.6%)<br>~9150 Registers (5.82%)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This page documents the imperix firmware IP for AMD\/Xilinx Vivado, which is required to program the FPGA of imperix controllers. This IP encapsulates the imperix&#8230;<\/p>\n","protected":false},"author":4,"featured_media":2995,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[17],"software-environments":[106],"provided-results":[],"related-products":[50,31,32,51,110],"guidedreadings":[],"tutorials":[],"user-manuals":[141],"coauthors":[70],"class_list":["post-877","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","tag-fpga-programming","software-environments-fpga","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-cpp-sdk","related-products-tpi","user-manuals-getting-started-with-fpga-programming"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.1 - 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