{"id":991,"date":"2021-03-29T12:11:19","date_gmt":"2021-03-29T12:11:19","guid":{"rendered":"https:\/\/imperix.com\/doc\/?p=991"},"modified":"2026-05-01T12:00:00","modified_gmt":"2026-05-01T12:00:00","slug":"discrete-control-delay","status":"publish","type":"post","link":"https:\/\/imperix.com\/doc\/help\/discrete-control-delay","title":{"rendered":"Discrete control delay identification"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 ez-toc-wrap-right-text counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Context\" >Context<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Definitions-of-the-various-delays\" >Definitions of the various delays<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Sensing-delay\" >Sensing delay<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Control-delay\" >Control delay<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Modulator-delay\" >Modulator delay<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Examples-of-delay-calculation\" >Examples of delay calculation<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Single-rate-update-with-synchronous-averaging\" >Single-rate update with synchronous averaging<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Single-rate-update-with-synchronous-sampling\" >Single-rate update with synchronous sampling<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#Double-rate-update-with-synchronous-sampling\" >Double-rate update with synchronous sampling<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/imperix.com\/doc\/help\/discrete-control-delay\/#References\" >References<\/a><\/li><\/ul><\/nav><\/div>\n\n<p class=\"wp-block-paragraph\">This note explains how to compute the discrete control delay of a control algorithm running on an imperix controller, and how to account for it in the controller tuning.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-context\"><span class=\"ez-toc-section\" id=\"Context\"><\/span>Context<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The execution of a digital control algorithm inevitably introduces delays in the control chain. These delays are not only due to the execution time of the algorithm, but also to external factors such as sensor and modulator delays. This overall delay affects the system response and therefore limits the achievable closed-loop control bandwidth. Knowledge of the total delay is therefore crucial for designing and tuning the controller in order to ensure stability and achieve the desired control performance.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">For controller design, the various delays involved in the control loop are often lumped together into an equivalent total delay \\(T_{d,tot}\\) and modeled using a first-order approximation \\(1\/(1+sT_{d,tot})\\). Based on this model, analytical tuning of the controller becomes possible, as further developed in <a href=\"https:\/\/imperix.com\/doc\/implementation\/pi-controller\" type=\"post\" id=\"14806\">PI controller implementation<\/a> and illustrated in <a href=\"https:\/\/imperix.com\/doc\/implementation\/pi-based-current-control\" type=\"post\" id=\"14834\">PI-based current control<\/a>.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">This note explains how to compute \\(T_{d,tot}\\) in the most common cases.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-definitions-of-the-various-delays\"><span class=\"ez-toc-section\" id=\"Definitions-of-the-various-delays\"><\/span>Definitions of the various delays<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The total loop delay is the sum of all the delays involved between the measurement of a state variable and the resulting action of the controller on the controlled plant. The different delays involved are defined below.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Delay<\/th><th>Symbol<\/th><th>Definition<\/th><\/tr><tr><td>Sensing delay<\/td><td>\\(T_{d,sens}\\)<\/td><td>Delay in the measured quantity, due to finite sensor and analog chain bandwidth, and possibly filtering delay<\/td><\/tr><tr><td>Control delay<\/td><td>\\(T_{d,ctrl}\\)<\/td><td>Delay between sampling instant and duty-cycle update instant in the PWM modulator (FPGA peripheral)<\/td><\/tr><tr><td>Modulator delay<\/td><td>\\(T_{d,PWM}\\)<\/td><td>Average delay between duty-cycle update in the PWM modulator and resulting change in modulator output<\/td><\/tr><tr><td>Switching delay<\/td><td>\\(T_{d,tran}\\)<\/td><td>Delay between a change in the modulator output and the actual switching of the power device (can often be neglected)<\/td><\/tr><tr><td>Total loop delay<\/td><td>\\(T_{d,tot}\\)<\/td><td>Sum of the above delays, representing the total delay of the control system<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"274\" height=\"132\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-184.png\" alt=\"Delays along the control loop\" class=\"wp-image-993\" title=\"Product notes &gt; PN142: Identifying the discrete control delay &gt; delays_block_diagram.png\"\/><figcaption class=\"wp-element-caption\">Delays along the control loop<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">The figure below illustrates the different delays involved with a triangular PWM carrier and single-rate update of the duty-cycle (at the bottom of the carrier).<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"558\" height=\"383\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-185.png\" alt=\"Definition of the various delays along the control chain\" class=\"wp-image-994\" title=\"Product notes &gt; PN142: Identifying the discrete control delay &gt; delay_definitions.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-185.png 558w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-185-300x206.png 300w\" sizes=\"auto, (max-width: 558px) 100vw, 558px\" \/><figcaption class=\"wp-element-caption\">Definition of the various delays along the control chain (sensing and switching delay neglected)<\/figcaption><\/figure>\n<\/div>\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Sensing-delay\"><\/span>Sensing delay<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The sensing delay \\(T_{d,sens}\\) includes delays in the sensors as well as in the controller&#8217;s analog front-end.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The sensor delay, of course, depends on the sensor, and particularly on its bandwidth \\(f_{bw}\\). If no value is specified, the delay can typically be assumed to be between \\(1\/(2\\pi f_{bw})\\) and \\(2\/(2\\pi f_{bw})\\).<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">In the controller, the delay introduced by the analog front-end is generally negligible (sub-\u00b5s). However, a significant delay can be introduced depending on the averaging used:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics?currentThread=b-board-pro#Synchronous-averaging\" type=\"post\" id=\"15921\">Synchronous averaging<\/a>: the induced delay on ADC channels for which it is enabled is half of the averaging period (i.e., typically half a control period).<\/li>\n\n\n\n<li>Low-pass filter (B-Box RCP and B-Box 4 only): the induced delay depends on the selected cutoff frequency (see tables below).<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-columns are-vertically-aligned-top is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-vertically-aligned-top is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"573\" height=\"434\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/delay_filter_BB3-1.png\" alt=\"\" class=\"wp-image-43552\" style=\"aspect-ratio:1.3203287671232877;object-fit:cover;width:300px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/delay_filter_BB3-1.png 573w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/delay_filter_BB3-1-300x227.png 300w\" sizes=\"auto, (max-width: 573px) 100vw, 573px\" \/><figcaption class=\"wp-element-caption\">Low-pass filter delay in B-Box RCP 3<\/figcaption><\/figure>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-top is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"569\" height=\"461\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/delay_filter_BB4-1.png\" alt=\"\" class=\"wp-image-43553\" style=\"width:300px\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/delay_filter_BB4-1.png 569w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/delay_filter_BB4-1-300x243.png 300w\" sizes=\"auto, (max-width: 569px) 100vw, 569px\" \/><figcaption class=\"wp-element-caption\">Low-pass filter delay in B-Box 4<\/figcaption><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Control-delay\"><\/span>Control delay<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The control delay \\(T_{d,ctrl}\\)\u200b is defined as the elapsed time between the sampling instant and the duty-cycle update in the PWM modulator.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Due to the discrete nature of the sampling and PWM update processes, the control delay typically takes values that are fractions or multiples of the control period T<sub>s<\/sub>, such as 0.5T<sub>s<\/sub>, T<sub>s<\/sub>, or 1.5T<sub>s<\/sub>, with its value depending on the relative timing between ADC sampling, controller execution, and PWM register update.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">More specifically, its value results from the combination of several delays along the data path, as listed below. The dominant contribution is the <strong>processing delay<\/strong>, i.e., the time required for the control interrupt routine to execute. All these delays are measured at runtime and displayed in the <a href=\"https:\/\/imperix.com\/doc\/help\/cockpit-user-guide#target-timings\" type=\"post\" id=\"11632\">Timings<\/a> tab in Cockpit.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><th>Delay<\/th><th>Symbol<\/th><th>Definition<\/th><\/tr><tr><td>Acquisition delay<\/td><td>\\(T_{acq}\\)<\/td><td>Delay between sampling and data availability in CPU.<br>= ADC conversion time (<em>ADC<\/em>) + FPGA-to-CPU transfer time (<em>Read<\/em>)<\/td><\/tr><tr><td>Processing delay<\/td><td>\\(T_{pr}\\)<\/td><td>CPU processing time (<em>Proc.<\/em>)<\/td><\/tr><tr><td>Write delay<\/td><td>\\(T_{wr}\\)<\/td><td>CPU-to-FPGA transfer time (<em>Write<\/em>)<\/td><\/tr><tr><td>Cycle delay<\/td><td>\\(T_{cy}\\)<\/td><td>Delay between sampling instant and newly computed data available in FPGA (\\(T_{cy}=T_{acq}+T_{pr}+T_{wr}\\), see dedicated section below)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">The post-processing execution time does not impact the control delay, since it includes only tasks that are not directly involved in the control algorithm (datalogging execution, CAN communication, Simulink external mode execution,&#8230;).<\/div>\n\n\n\n<h4 class=\"wp-block-heading\">Acquisition delay<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">The acquisition delay is the time between the sampling instant and the moment the resulting value becomes available to the CPU. It consists of the ADC conversion time and the transfer of the sampled data from the ADC to the CPU.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The ADC conversion time depends on the specific controller in use and is provided in the table below.<\/p>\n\n\n\n<figure class=\"wp-block-table aligncenter\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>Device<\/strong><\/td><td><strong>ADC conversion time<\/strong><\/td><\/tr><tr><td>B-Box 4<\/td><td>0.2 \u00b5s<\/td><\/tr><tr><td>B-Box RCP<\/td><td>2 \u00b5s<\/td><\/tr><tr><td>B-Box Micro<\/td><td>0.5 \u00b5s<\/td><\/tr><tr><td>B-Board PRO<\/td><td>0.5 \u00b5s<\/td><\/tr><tr><td>TPI 8032<\/td><td>0.5 \u00b5s<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">ADC conversion delay of imperix controllers<\/figcaption><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">The ADC-to-CPU transfer delay depends mainly on the number of ADC channels being read. That delay can be observed in the <a href=\"https:\/\/imperix.com\/doc\/help\/cockpit-user-guide#target-timings\">Timings tab<\/a> of Cockpit.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-cycle-delay\">Processing and cycle delays<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">The cycle delay comprises the whole chain of delays: acquisition, processing, and FPGA transfer. For any code running on an imperix controller, its value can be displayed in the <a href=\"https:\/\/imperix.com\/doc\/help\/cockpit-user-guide#target-timings\">Timings tab<\/a> of Cockpit.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Its value depends mainly on processing delay, which depends on the complexity of the executed control algorithm and is thus application-dependent. For example, the control of the <a href=\"https:\/\/imperix.com\/doc\/example\/three-phase-pv-inverter\">PV boost and three-phase grid-tied inverter (AN006)<\/a> gives the following figures:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Acquisition delay \\(T_{acq}\\): 2.072 \u00b5s (includes 2 \u00b5s ADC delay in B-Box RCP)<\/li>\n\n\n\n<li>Processing delay \\(T_{pr}\\): 3.9 \u00b5s<\/li>\n\n\n\n<li>Write delay \\(T_{wr}\\): 0.1 \u00b5s<\/li>\n\n\n\n<li>Cycle delay (total) \\(T_{cy}\\): 6 \u00b5s<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-modulator-delay\"><span class=\"ez-toc-section\" id=\"Modulator-delay\"><\/span>Modulator delay<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Most previously defined delays are straightforward and hardware-dependent. However, the modulator delay requires further clarification, as it varies according to the PWM peripheral parameters. Technically, this delay represents the time elapsed between the moment a new duty cycle is registered and the moment it is reflected in the PWM output pulse. Since this duration varies with the duty cycle itself, a statistical average is typically used for modeling purposes.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-sawtooth-carrier\">Sawtooth carrier<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">It is quite straightforward that the sawtooth carrier introduces a delay that depends on the duty-cycle \\(d\\) and the switching period \\(T_{sw}\\). From the figure below, we can deduce that the delay is<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sawtooth carrier:&nbsp;\\(T_{d,\\text{PWM}}=dT_{sw}\\)<\/li>\n\n\n\n<li>Inverted sawtooth carrier: \\(T_{d,\\text{PWM}}=(1-d)T_{sw}\\)<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">For controller tuning, the average value \\(T_{d,\\text{PWM}}=T_{sw}\/2\\) is generally used, for both sawtooth carrier shapes.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"745\" height=\"181\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-186.png\" alt=\"Modulator delay for sawtooth and inverted sawtooth carriers\" class=\"wp-image-995\" title=\"Product notes &gt; PN142: Identifying the discrete control delay &gt; sawtooth_modulator_delay.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-186.png 745w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-186-300x73.png 300w\" sizes=\"auto, (max-width: 745px) 100vw, 745px\" \/><figcaption class=\"wp-element-caption\">Modulator delay for (left) sawtooth and (right) inverted sawtooth carriers<\/figcaption><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\" id=\"h-triangular-carrier\">Triangular carrier<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">The modulator delay calculation is more complex with a triangular carrier, since both rising and falling edges of the PWM signal are affected by the duty-cycle value.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">A small-signal approximation introduced in [1] and further developed in [2] shows that \\(T_{d,\\text{PWM}}=T_{sw}\/2\\) for single-rate update.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Intuitively, the duty-cycle update has an effect on two PWM edges: before and after the half of the carrier, resulting, on average, in an effect after half a switching period&nbsp;[1]. This also means that the delay is identical for triangular and inverted triangular carriers.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">With double-rate update, the modulator delay is reduced to \\(T_{d,\\text{PWM}}=T_{sw}\/4\\)&nbsp;[1], providing that the sampling is also performed at double rate (double-rate sampling, \\(T_s=T_{sw}\/2\\)).<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"745\" height=\"181\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-187.png\" alt=\"Modulator delay for triangular and inverted triangular carriers\" class=\"wp-image-996\" title=\"Product notes &gt; PN142: Identifying the discrete control delay &gt; triangular_modulator_delay.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-187.png 745w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-187-300x73.png 300w\" sizes=\"auto, (max-width: 745px) 100vw, 745px\" \/><figcaption class=\"wp-element-caption\">Modulator delay for (left) triangular and (right) inverted triangular carriers<\/figcaption><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\" id=\"h-direct-output-pwm\">Direct output PWM<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">If no PWM modulator is used (e.g. when using the <a href=\"https:\/\/imperix.com\/doc\/software\/do-pwm-direct-output-pwm\">DO-PWM &#8211; Direct output PWM<\/a> peripheral), the modulator delay is obviously&nbsp;\\(T_{d,\\text{PWM}}=0\\). In this case, the firing signal is updated as soon as a new value is available at the FPGA level, meaning that \\(T_{d,ctrl}=T_{cy}\\).<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Examples-of-delay-calculation\"><\/span>Examples of delay calculation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Single-rate-update-with-synchronous-averaging\"><\/span>Single-rate update with synchronous averaging<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Let us consider the following configuration, which is the default configuration with imperix controllers:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The switching and sampling periods are the same \\(T_{sw}=T_{s}\\).<\/li>\n\n\n\n<li>The sampling phase is \\(\\phi_{s}=0\\), which also defines when the interrupt is triggered.<\/li>\n\n\n\n<li>All ADC channels use <a href=\"https:\/\/imperix.com\/doc\/help\/sampling-techniques-for-power-electronics?currentThread=b-board-pro#Synchronous-averaging\">synchronous averaging<\/a>.<\/li>\n\n\n\n<li>The PWM modulator uses a triangular carrier with a phase of zero and <strong>single-rate update <\/strong>(i.e. update at the bottom of the carrier).<\/li>\n\n\n\n<li>The current sensor bandwidth is 200 kHz.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">In this case, the total loop delay is computed as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sensing delay: \\(T_{d,sens}= T_s\/2\\) (due to averaging)<\/li>\n\n\n\n<li>Control delay: \\(T_{d,ctrl} = T_s\\)<\/li>\n\n\n\n<li>Modulator delay: \\(T_{d,\\text{PWM}}=T_{sw}\/2\\) (triangular carrier)<\/li>\n\n\n\n<li>Switching delay: neglected, sub-microsecond<\/li>\n\n\n\n<li>Total loop delay: \\(T_{d,tot}=T_{d,sens}+T_{d,ctrl}+T_{d,\\text{PWM}}=2T_s\\)<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"528\" height=\"309\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/sync-avg_example-1.png\" alt=\"\" class=\"wp-image-43544\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/sync-avg_example-1.png 528w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/sync-avg_example-1-300x176.png 300w\" sizes=\"auto, (max-width: 528px) 100vw, 528px\" \/><figcaption class=\"wp-element-caption\">Example of delay calculation with synchronous averaging<\/figcaption><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Controller optimization tip:<\/strong> The total delay can be effectively reduced by increasing the sampling (i.e., interrupt) phase, which reduces the time spent waiting for the next duty-cycle update instant. For example, in the previous illustration, if the interrupt phase had been set to 0.5\u202fT<sub>s<\/sub>, the total loop delay would have been reduced to 1.5\u202fT<sub>s<\/sub>. The optimal sampling phase is the one that triggers the interrupt as late as possible while still leaving enough time for the interrupt to execute before the next duty-cycle update.<\/div>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-single-rate-update\"><span class=\"ez-toc-section\" id=\"Single-rate-update-with-synchronous-sampling\"><\/span>Single-rate update with synchronous sampling<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Let us consider the following standard configuration:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The switching and sampling periods are the same \\(T_{sw}=T_{s}\\).<\/li>\n\n\n\n<li>The sampling phase is \\(\\phi_{s}=0.5\\) to ensure sampling in the middle of the current ripples.<\/li>\n\n\n\n<li>The PWM modulator uses a triangular carrier with a phase of zero and <strong>single-rate update <\/strong>(i.e. update at the bottom of the carrier).<\/li>\n\n\n\n<li>The current sensor bandwidth is 200 kHz.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">In this case, the total loop delay is computed as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sensing delay: neglected (\\(\\approx 800\\,\\text{ns}\\))<\/li>\n\n\n\n<li>Control delay: \\(T_{d,ctrl} = 0.5T_s\\)<\/li>\n\n\n\n<li>Modulator delay: \\(T_{d,\\text{PWM}}=T_{sw}\/2\\) (triangular carrier)<\/li>\n\n\n\n<li>Switching delay: neglected, sub-microsecond<\/li>\n\n\n\n<li>Total loop delay: \\(T_{d,tot}=T_{d,ctrl}+T_{d,\\text{PWM}}=T_s\\)<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-regular-control-algorithm\">Regular control algorithm<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In this first case, we assume that the control algorithm can be executed fast enough, so that the cycle delay is shorter than half a control period (\\(T_{cy} &lt; 0.5T_s\\)). This is the case for most control implementations running on imperix controllers.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">In this case, the total loop delay is computed as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sensing delay: neglected (\\(\\approx 800\\,\\text{ns}\\))<\/li>\n\n\n\n<li>Control delay: \\(T_{d,ctrl} = T_s\/2\\)<\/li>\n\n\n\n<li>Modulator delay: \\(T_{d,\\text{PWM}}=T_{sw}\/2\\) (triangular carrier)<\/li>\n\n\n\n<li>Switching delay: neglected, sub-microsecond<\/li>\n\n\n\n<li>Total loop delay: \\(T_{d,tot}=T_{d,ctrl}+T_{d,\\text{PWM}}=T_s\\)<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"558\" height=\"247\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-188.png\" alt=\"Example of delay calculation for a light control algorithm\" class=\"wp-image-997\" title=\"Product notes &gt; PN142: Identifying the discrete control delay &gt; single-rate_light_example.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-188.png 558w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-188-300x133.png 300w\" sizes=\"auto, (max-width: 558px) 100vw, 558px\" \/><figcaption class=\"wp-element-caption\">Example of delay calculation for a <em>light <\/em>control algorithm<\/figcaption><\/figure>\n<\/div>\n\n\n<h4 class=\"wp-block-heading\" id=\"h-heavy-control-algorithm\">Heavy control algorithm<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Now let&#8217;s assume that the control algorithm is heavy and the cycle delay is longer than half a control period (\\(T_{cy} \\geq 0.5T_s\\)).<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">In this case, the total loop delay is computed as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sensing delay: neglected (\\(\\approx 800\\,\\text{ns}\\))<\/li>\n\n\n\n<li>Control delay: \\(T_{d,ctrl} = 1.5T_s\\)<\/li>\n\n\n\n<li>Modulator delay: \\(T_{d,\\text{PWM}}=T_{sw}\/2\\) (triangular carrier)<\/li>\n\n\n\n<li>Switching delay: neglected, sub-microsecond<\/li>\n\n\n\n<li>Total loop delay: \\(T_{d,tot}=T_{d,ctrl}+T_{d,\\text{PWM}}=2T_s\\)<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"558\" height=\"247\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-189.png\" alt=\"Example of delay calculation for a heavy control algorithm\" class=\"wp-image-1000\" title=\"Product notes &gt; PN142: Identifying the discrete control delay &gt; single-rate_example.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-189.png 558w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/image-189-300x133.png 300w\" sizes=\"auto, (max-width: 558px) 100vw, 558px\" \/><figcaption class=\"wp-element-caption\">Example of delay calculation for a <em>heavy <\/em>control algorithm<\/figcaption><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\"><strong>Controller optimization tip:<\/strong> In that case, setting the sampling phase to zero would reduce the control delay to 1 T<sub>s<\/sub>, which would bring the total loop delay down to 1.5 T<sub>s<\/sub>. The downside of this would be that the sampling instant and the duty-cycle update would occur at the same time. This would mean that the sampling point would no longer be perfectly centered within the PWM pulse. But for light duty-cycle variations, this asymmetry would have almost no effect on performance, and the benefit of a shorter control delay would far outweigh the minor loss of PWM symmetry.<\/div>\n\n\n\n<h4 class=\"wp-block-heading\" id=\"h-general-case\">General case<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">With single-rate update and triangular carrier, the total loop delay can take two values:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>If&nbsp;\\(T_{cy} &lt; (1-\\phi_s)T_s\\), \\(T_{d,ctrl} = (1-\\phi_s)T_s\\) and \\(T_{d,tot}=(1.5-\\phi_s)T_s \\)<\/li>\n\n\n\n<li>If \\(T_{cy} \\geq (1-\\phi_s)T_s\\), \\(T_{d,ctrl} = (2-\\phi_s)T_s\\) and \\(T_{d,tot}=(2.5-\\phi_s)T_s\\)<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">These results suggest that the smaller the sampling phase, the smaller the delay. However, the choice of the sampling phase should also rely on current ripple sampling considerations. Generally speaking, the choice of the sampling phase is a trade-off between control bandwidth and the accuracy of the control.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"h-double-rate-update\"><span class=\"ez-toc-section\" id=\"Double-rate-update-with-synchronous-sampling\"><\/span>Double-rate update with synchronous sampling<span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Now, let us consider the following configuration:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The switching and sampling periods are \\(T_{sw}=2T_{s}\\) (<strong>double-rate sampling<\/strong>).<\/li>\n\n\n\n<li>The sampling phase is \\(\\phi_{s}=0\\).<\/li>\n\n\n\n<li>The PWM modulator uses a triangular carrier with a phase of zero and <strong>double-rate update<\/strong> (update at the top and bottom of the carrier).<\/li>\n\n\n\n<li>The current sensor bandwidth is 200 kHz.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">In this case, the total loop delay does not depend on the execution time of the algorithm, unlike with single-rate update. It is computed as follows:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sensing delay: neglected (\\(\\approx 800\\,\\text{ns}\\))<\/li>\n\n\n\n<li>Control delay:&nbsp;\\(T_{d,ctrl}=T_s\\)<\/li>\n\n\n\n<li>Modulator delay: \\(T_{d,\\text{PWM}}=T_{sw}\/4=T_s\/2\\) (triangular carrier with double-rate update)<\/li>\n\n\n\n<li>Switching delay: neglected, sub-microsecond<\/li>\n\n\n\n<li>Total loop delay: \\(T_{d,tot}=T_{d,ctrl}+T_{d,\\text{PWM}}=1.5T_s\\)<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"558\" height=\"247\" src=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/double-rate_example.png\" alt=\"Example of delay calculation with double-rate sampling and PWM update\" class=\"wp-image-33974\" title=\"Product notes &gt; PN142: Identifying the discrete control delay &gt; double-rate_example.png\" srcset=\"https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/double-rate_example.png 558w, https:\/\/imperix.com\/doc\/wp-content\/uploads\/2021\/03\/double-rate_example-300x133.png 300w\" sizes=\"auto, (max-width: 558px) 100vw, 558px\" \/><figcaption class=\"wp-element-caption\">Example of delay calculation with double-rate sampling and PWM update<\/figcaption><\/figure>\n<\/div>\n\n\n<div class=\"wp-block-simple-alerts-for-gutenberg-alert-boxes sab-alert sab-alert-info\" role=\"alert\">With the ACG SDK library, double-rate sampling can be achieved by connecting the PWM modulator blocks to a clock (CLK) block with a frequency that is half of the CLOCK_0 frequency. More details can be found in <a href=\"https:\/\/imperix.com\/doc\/help\/timing-configuration-on-imperix-controllers\" type=\"post\" id=\"40107\">PN259<\/a>.<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-references\"><span class=\"ez-toc-section\" id=\"References\"><\/span>References<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">[1] D. M. Van de Sype, K. De Gusseme, A. P. Van den Bossche and J. A. Melkebeek, &#8220;Small-signal Laplace-domain analysis of uniformly-sampled pulse-width modulators,&#8221;&nbsp;<em>2004 IEEE 35th Annual Power Electronics Specialists Conference<\/em>, Aachen, Germany, 2004, pp.&nbsp;4292-4298&nbsp;Vol.6.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">[2] S. Buso and P. Mattavelli, \u201cDigital Control in Power Electronics\u201d, 2006.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This note explains how to compute the discrete control delay of a control algorithm running on an imperix controller, and how to account for it&#8230;<\/p>\n","protected":false},"author":2,"featured_media":3072,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[],"software-environments":[],"provided-results":[],"related-products":[50,31,32,92,166,51,110],"guidedreadings":[],"tutorials":[],"user-manuals":[139,138,137,135,143],"coauthors":[63],"class_list":["post-991","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-help","related-products-acg-sdk","related-products-b-board-pro","related-products-b-box-rcp","related-products-b-box-micro","related-products-b-box-rcp-3-0","related-products-cpp-sdk","related-products-tpi","user-manuals-b-board-pro","user-manuals-b-box-micro","user-manuals-b-box-rcp-3-0","user-manuals-going-further-with-acg-sdk","user-manuals-tpi"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - 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