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FPGA programming

Firmware customization

The FPGA programmability allows to easily embed custom firmware into the B-Box RCP or B-Board PRO.

This enables the user to augment the set of available functions, such as new modulation algorithms, interfaces for external peripherals, or offload computation to the FPGA.

OPEN DESIGN FRAMEWORK

The imperix firmware only uses approximately 30% of the FPGA logic resources and 70% of the physical ports. As such, the unused logic represents most of the FPGA area, which is entirely available to the user. In practice, relying on all the Xilinx Vivado Design Suite tools and IPs, working with the B-Box and B-Board is as simple and open as programming any other Xilinx FPGA.
MAIN BENEFITS
  • Complete freedom: The unused FPGA logic and I/O ports can be used as the user sees fit.
  • High performance: The 250 MHz base clock and FPGA parallel architecture allow for very fast algorithms.
  • Easy interfacing: Exchanging data between CPU and FPGA is made easy using the provided drivers.
  • Free of charge: The Vivado software and the FPGA programmability come at no additional cost.
Separate the control between CPU and FPGA, which enables the implementation of faster control loop or custom modulators.

Use your preferred workflow and language. High-level description and synthesis are also possible, e.g. using Matlab HDL Coder or Vivado HLS.

Integrate your design to the existing firmware and have access to the ADC, PWM, I/Os, (and much more) from the FPGA. Communication with the CPU is also facilitated.
Flash your customized firmware using the BB Control utility and an Ethernet connection. No need for additional cable or to open the box.

Simple integration

Only a few steps needed

  • Open the provided template
  • Instantiate your module
  • Connect it to the imperix IP using the Vivado graphical environment

CPU to FPGA communication

The imperix IP provides a set of 128 registers named SBI and SBO. On the CPU side, drivers are provided to read or write in these registers in all simplicity. The communication is completely transparent to the user.

User high-speed I/O interface

To access the outside world, a set of high-speed 3.3V pins can freely be used (USR pins)

 Hover to find out more.

Mixed design approaches

CPU-SIDE WORKFLOW

The B-Board holds a dual-core processor. The first core runs Linux and is in charge of the overall supervision. The second core runs on BBOS and is programmed by the user to execute the application-level control.

The CPU code can be written in C/C++ (CPP SDK) or generated using a graphical environment such as Simulink or PLECS (ACG SDK).

Matlab Simulink
The Simulink blockset allows to program the device without any code and provides an accurate offline simulation.
Plexim PLECS
Imperix provides a blockset for the PLECS software too, which also supports code generation and offline simulation.
C/C++ code
For maximal code optimization and flexibility, the CPU code can be directly coded in C/C++.
FPGA-SIDE WORKFLOW

The standard FPGA firmware contains the pre-implemented peripherals (ADC, PWM,…) and networking logic. The user can customize this firmware by integrating its own design using the Xilinx Vivado Design Suite.

There are many ways to create a FPGA design, from HDL code (VHDL/Verilog) to C++ or even graphical interface blocks.

HDL langages (VHDL/Verilog)
For complete control over the design, VHDL or Verilog can be used to describe the FPGA logic.
Vivado HLS (C++)
To implement complex algorithms, tools such as Vivado HLS can be used to easily generate HDL code from C++.
MATLAB HDL
MATLAB HDL Coder allows generating HDL code directly from MATLAB functions, Simulink models or Stateflow charts.

Transparent networking across devices

Devices pre-addressing
A device ID ranging from 0 to 63 is automatically attributed to each device by the BBOS operating system.
Full-duplex transfers
5 Gbps optical links are using for inter-device communication. Moreover, UP and DOWN traffic works in a full-duplex fashion for maximal performance.
Native synchronization
All the networked devices are synchronized with an accuracy of ±2 ns to imperix Real Sync technology. Absolutely zero clock drift!
No need to worry about device addressing

To increase the I/Os capability, up to 64 devices can be connected, in a totally transparent manner. Indeed, the device addressing is entirely managed by the real-time operating system BBOS.

Furthermore, all units are natively synchronized with an accuracy of ±2 ns thanks to imperix’s Real Sync technology. This allows using all FPGAs and I/Os as if they simply belonged to the same controller hardware!

Slaves can integrate processing tasks

In a multi-device setup, normally only one CPU oversees the overall execution, inside the master. Nevertheless, thanks to the FPGA’s direct access to the ADC results and PWM outputs, local control loops can be implemented within slave FPGAs too.

Furthermore, soft-processors can be instantiated in the FPGA (e.g. Xilinx MicroBlaze), which can be programmed and debugged just like a standard CPU, making things even easier!

Application EXAMPLES

Motor Direct Torque Control using Vivado HLS
Hysteresis current control of a 3-phase inverter
SPI communication IP for A/D converter
Motor Direct Torque Control
using Vivado HLS
Hysteresis current control
of a 3-phase inverter
SPI communication IP
for A/D converter

Want to know more?

For all questions related to our software, feel free to get in touch with our technical team. We're here to help! Online demos can also be organized upon request.

Alternatively, you can always download and install the software. As our licenses are hardware-related, our software is essentially unrestricted and all features can be tested free of charge.