SS-PWM - Multilevel PWM with Sort-&-Select balancing

The SS-PWM peripheral provides a specialized Pulse Width Modulation scheme (PWM) for multilevel converters, which directly integrates means for balancing series-connected submodules. Such an approach has received quick and widespread adoption, notably for Modular Multilevel Converters, Cascaded H-Bridges, and similar converter topologies.

The SS-PWM block generates gate driving signals, which are dynamically assigned to suitable submodules following a “Sort and select” algorithm. The corresponding operating principle is relatively simple:

1. At first, submodules are sorted according to their capacitor voltage.
2. Then, the submodules selected to contribute to the arm voltage are those with the highest charge level when the power is flowing out of the arm, respectively with the least charge level when the power is flowing into the arm. This way, some balancing is achieved over time so that all submodules converge toward the same charge level.

Multilevel PWM operation

The FPGA-based implementation of the SS-PWM is detailed in TN160. It is inspired by the original patent by R. Marquardt. The implemented multilevel modulator features the following key characteristics:

• All submodules are continuously sorted. In other words, all ranks are identified, as opposed to techniques that only identify the most and least charged submodules.
• By design, it is guaranteed that only one commutation can occur at once. This ensures that no ineffective modulation actions are made and that switching losses are minimized.
• Both half-bridge and full-bridge submodules are supported.
• Up to N=23 submodules per arm are supported.
• Both PWM and staircase modulation approaches are supported.

Similarly to other PWM modules, the following parameters of the multilevel PWM module can be configured:

• The sampling frequency is freely configurable (identical to the control interrupt frequency).
• The switching frequency is freely configurable.
• PWM update is possible once or twice per period (when the carrier reaches its minimum and/or maximum).
• Complementary High and Low signals offer a configurable dead-time generation.
• Multilevel PWM outputs can be activated or deactivated during the operation.

Simulink SS-PWM block

Signal specification

• The input m is the modulation signal. Its range is [0; N] in half-bridge mode and [-N; N] in full-bridge mode. N is the number of submodules per arm.
• The input signal sim V is a vector containing the submodules voltages. This input is only effective during simulation. Measurements are directly taken from the corresponding analog input channels during real-time operation.
• The input signal sim I corresponds to the arm current and is only used for simulation.
• The input signal > is the clock input and must be connected to the CONFIG block or to an independent CLK block. When connected to a variable-frequency clock, the switching frequency can be tuned during runtime (see PN121).
• The outputs are the generated PWM signals, according to the block configuration. The outputs are only used for simulation.

Parameters

• Device ID selects which B-Box/B-Board to address when used in a multi-device configuration.
• Output mode selects between complementary signals with a deadtime, a single PWM with a global active signal or a single PWM.
• Start channel and Number of channels defines the number of submodules per modulator, with a maximum of 23 modules, by specifying the analog input channels. Each analog input channel correspond to one submodule. The PWM outputs are automatically assigned to each analog input.
  B-Box 3: The maximum number of submodules and the corresponding input channels are limited to 8.
• Submodules topology defines if the modules are half-bridge or full-bridge modules.
• Current input channel selects the analog input channel of the arm current measurement.
  B-Box 3: The current input channel must be between 8 and 15.
• Invert sorting logic inverts the sorting logic of the SS-PWM sorting algorithm. As described by the schematic below, if a positive/negative measured current results in an increase/decrease of measured voltage, respectively, then the logic is non-inverted. On the other hand, the sorting logic must be inverted if a positive/negative measured current results in a decrease/increase in measured voltage, respectively. Also, this parameter being purely defined by the hardware, it is only used for code generation and has no effect in simulation mode.
• Show "activate" input makes the A (active) signal input visible. If not checked, the SS-PWM block is always active by default (once the controller outputs are enabled).
• Activation mode specifies if the activate input is global or per submodule. In the global mode, the activate signal is one-dimensional and applied to all submodules. In the per submodule mode, the activate signal is an array with one signal per submodule.
  B-Box 3: Only the global mode is supported and the option is therefore not shown.
• Carrier type sets the carrier to TRIANGLE, INVTRIANGLE, or No Carrier (Staircase modulation). This option can be used to either generate N+1 or 2N+1 level output waveforms.
• PWM parameters update rate selects when the duty-cycle and phase parameters are applied.
  • Single-rate: they are applied at the end of the carrier period.
  • Double-rate: they are applied twice per carrier period: when the carrier reaches its lowest point and when it reaches its highest point. (for TRIANGLE and INVTRIANGLE carriers only)
• Deadtime duration: configures the dead-time duration.

PLECS SS-PWM block

Signal specification

• The input m is the modulation signal. Its range is [0; N] in half-bridge mode and [-N; N] in full-bridge mode. N is the number of submodules per arm.
• The input signal sim V is a vector containing the submodules voltages. This input is only effective during simulation. Measurements are directly taken from the corresponding analog input channels during real-time operation.
• The input signal sim I corresponds to the arm current and is only used for simulation.
• The input signal > is the clock input and must be connected to the CONFIG block or to an independent CLK block. When connected to a variable-frequency clock, the switching frequency can be tuned during runtime (see PN121).
• The outputs are the generated PWM signals, according to the block configuration. The outputs are only used for simulation.

Parameters

• Device ID selects which B-Box/B-Board to address when used in a multi-device configuration.
• Output mode selects between complementary signals with a deadtime, a single PWM with a global active signal or a single PWM.
• Start channel and Number of channels defines the number of submodules per modulator, with a maximum of 23 modules, by specifying the analog input channels. Each analog input channel correspond to one submodule. The PWM outputs are automatically assigned to each analog input.
  B-Box 3: The maximum number of submodules and the corresponding input channels are limited to 8.
• Submodules topology defines if the modules are half-bridge or full-bridge modules.
• Current input channel selects the analog input channel of the arm current measurement.
  B-Box 3: The current input channel must be between 8 and 15.
• Invert sorting logic inverts the sorting logic of the SS-PWM sorting algorithm. As described by the schematic below, if a positive/negative measured current results in an increase/decrease of measured voltage, respectively, then the logic is non-inverted. On the other hand, the sorting logic must be inverted if a positive/negative measured current results in a decrease/increase in measured voltage, respectively. Also, this parameter being purely defined by the hardware, it is only used for code generation and has no effect in simulation mode.
• Carrier type sets the carrier to TRIANGLE, INVTRIANGLE or No Carrier (Staircase modulation). This option can be used to either generate N+1 or 2N+1 level output waveforms.
• PWM activation makes the A (active) signal input visible. By default, the SS-PWM block is always active (once the controller’s outputs are enabled).
• Activation mode specifies if the activate input is global or per submodule. In the global mode, the activate signal is one-dimensional and applied to all submodules. In the per submodule mode, the activate signal is an array with one signal per submodule.
  B-Box 3: Only the global mode is supported and the option is therefore not shown.
• PWM parameters update rate selects when the duty-cycle and phase parameters are applied.
  • Once per PWM period: they are applied at the end of the carrier period.
  • Twice per PWM period: they are applied twice per carrier period: when the carrier reaches its lowest point and when it reaches its highest point. (for TRIANGLE and INVTRIANGLE carriers only)
• Deadtime duration: configures the dead-time duration.

C++ functions

Specific to SS-PWM

In the B-Box 3, the SS-PWM modulator id is limited to SS_MODULATOR_0 and SS_MODULATOR_1, while SS_MODULATOR_2 is also available in the B-Box 4.

void SsPwm_ConfigureOutputMode(unsigned int modulator, tPwmOutMode outMode, unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureSubmodules(unsigned int modulator, unsigned int sm_mask,
unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureSubmodulesTopology(unsigned int modulator,
tSmTopology topology, unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureCurrentInput(unsigned int modulator, unsigned int input,
unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureInvertedSorting(unsigned int modulator,
bool invert_sorting, unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureCarrier(unsigned int modulator, tPwmCarrier carrier,
bool enabled, unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureClock(unsigned int modulator, tClock clock,
unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureUpdateRate(unsigned int modulator, tPwmRate rate,
unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureActivateAsRealTime(unsigned int modulator,
unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureActivatePerSubMode(unsigned int modulator, unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ConfigureActivateOutput(unsigned int modulator, tPwmOutput output, unsigned int device=0);Code language: C++ (cpp)

void SsPwm_SetModulationIndex(unsigned int modulator, float m,
unsigned int device=0);Code language: C++ (cpp)

void SsPwm_ActivateSubmodule(unsigned int modulator, unsigned int mask,
unsigned int startCh, unsigned int device);Code language: C++ (cpp)

Functions common to all PWM drivers

These functions are common to all PWM blocks. Further documentation is available on the PWM page.

void SsPwm_ConfigureDeadTime(tSsModulator modulator, float deadTime, unsigned int device=0);Code language: C++ (cpp)

void SsPwm_Activate(tSsModulator modulator, unsigned int device=0);
Code language: C++ (cpp)

void SsPwm_Deactivate(tSsModulator modulator, unsigned int device=0);Code language: C++ (cpp)