CONFIG - Control task configuration

This page is based on SDK 2025.2.

The CONFIG block is mandatory and serves to configure the main clock CLK0, the sampling clock SCLK and the CPU task frequency.

This block also configures various model parameters for simulation. More information regarding the simulation is available in the following notes:

• Simulation essentials with Simulink (PN135)
• Simulation essentials with PLECS (PN137)

Simulink block

Signal specification

• The first output is the PWM clock signal and can be connected to the > input of the PWM blocks to set their frequency to the CLK0 frequency.
• The second output is the sampling clock signal SCLK and must be connected to the > input signal of all the ADC blocks of the model.

The simulation behavior of these signals is described in Simulation essentials with Simulink (PN135).

Timings tab parameters

• The CLK0 frequency parameter sets the main clock frequency F_CLK0, which provides the time base for generating the ADC sampling strobe SCLK, the CPU task execution and the switching frequency of the connected PWM blocks.
• The sampling phase sets the phase-shift of the ADC sampling strobe SCLK relative to CLK0. The sampling frequency F_SCLK is equal to F_CLK0. The CPU control task is executed right after the sampled values are available.
• The postscaler is used to decimate the CPU task execution rate relative to SCLK such as
  F_CPU = F_CLK0 / postscaler.

Advanced sampling parameters

• The oversampling parameter allows setting a multiplier such as F_SCLK = F_CLK0 x multiplier.
  This parameter will become legacy, to obtain a sampling frequency higher than the CPU execution frequency, it is recommended to increase F_CLK0 in combination with the postscaler instead.
• The ADC acquisition delay corresponds to the acquisition and conversion process time of the ADC chip. This parameter can take multiples values because the B-Box analog frontend ADC chips are not the same as the ones embedded into B-Board PRO.
  It can be set to:
  • 2000 ns (compatible with the B-Box RCP, B-Box Micro, B-Board PRO or TPI)
  • 500 ns (compatible with the B-Box Micro, B-Board PRO or TPI)

Simulation parameters

• In the computation delay tab, the cycle delay is used in simulation mode only and serves to accurately model the time at which the PWM parameters are actually updated. It represents the total control execution time. As such, this sums up the delays involved in the control dynamics (ADC acquisition, data read, control task execution, data write). This is part of the total actuation delay, whose modeling is required in order to accurately simulate control dynamics.
  As the cycle delay cannot be anticipated before the control code is run on the target, this parameter must be measured during run time. To this end, Cockpit timings tab provides the necessary information.
• The Power library tab parameters are documented in the Getting started with Imperix Power library page.

PLECS block

• The Task output must be connected to the Control Task Trigger block. The Control Task Trigger nominal base sample time must be equal to postscaler/CLOCK_0 frequency.
• The PWM clock signal must be connected to the > input of the PWM blocks to set their frequency to the CLK0 frequency.
• The ADC clock output is the sampling signal SCLK. It must be connected to the > input signal of all the ADC blocks of the model.

The simulation behavior of these signals is described in Simulation essentials with PLECS (PN137)

Control task parameters

• The CLK0 frequency parameter sets the main clock frequency F_CLK0, which provides the time base for generating the ADC sampling strobe SCLK, the CPU task execution and the switching frequency of the connected PWM blocks.
• The sampling phase sets the phase-shift of the ADC sampling strobe SCLK relative to CLK0. The sampling frequency F_SCLK is equal to F_CLK0. The CPU control task is executed right after the sampled values are available.
• The postscaler is used to decimate the CPU task execution rate relative to SCLK such as
  F_CPU = F_CLK0 / postscaler.

Changing the postscaler in PLECS

In PLECS, the discretization step size must match the CPU control task period for the generated code to behavior properly. When using the postscaler, ensure that the discretization step size is set to postscaler/FCLK0. As illustrated below, a simulation variable can be used for convenience.

1. Create a postscaler variable in Simulation -> Simulation parameters (Ctrl+E).

2. Use the postscaler variable in the CONFIG block mask.

3. Update the discretization step size in Coder -> Coder options (Ctrl+Alt+B)

Advanced sampling parameters

• The oversampling parameter allows setting a multiplier such as F_SCLK =F_CLK0 x multiplier.
  This parameter will become legacy. To obtain a sampling frequency higher than the CPU execution frequency, it is recommended to increase F_CLK0 in combination with the postscaler instead.
• The ADC acquisition delay corresponds to the acquisition and conversion process time of the ADC chip. This parameter can take multiples values because the B-Box analog frontend ADC chips are not the same as the ones embedded into B-Board PRO.
  It can be set to:
  • 2000 ns (compatible with the B-Box RCP, B-Box Micro, B-Board PRO or TPI)
  • 500 ns (compatible with the B-Box Micro, B-Board PRO or TPI)

Simulation parameters

The cycle delay represents the total control execution time. As such, this sums up the delays involved in the control dynamics (ADC acquisition, data read, control task execution, data write). It is used in simulation mode only and serves to accurately model the time at which the PWM parameters are actually updated. This is part of the total actuation delay, whose modelling is required in order to accurately simulate control dynamics.

As the cycle delay cannot be anticipated before the control code is run on the target, this parameter must be measured during run time. To this end, Cockpit timings tab provides the necessary information.

C++ functions

void ConfigureMainInterrupt(tUserSafe (*userCallback)(void), tClock clock, float phase, unsigned int postscaler=0);Code language: C++ (cpp)