Most imperix controllers feature 36 bidirectional 3.3V I/O lines, commonly known as USR pins. Driven directly from the FPGA, these custom-application I/Os are ideal for…
This page describes how to upgrade the imperix IP in an existing sandbox project, whether to restore compatibility with a newer SDK version or to…
Beyond the built-in modulators accessible from the user application, the imperix sandbox enables PWM generation directly within the FPGA, allowing for the implementation of custom…
Imperix provides direct access to ADC measurements within the FPGA which allows for reduced delay between the sampling and the processing, but also helps supporting…
On imperix controllers, the CPU exchanges data with the FPGA via the SBIO bus. This memory-mapped bus allows the CPU user app to read and…
This page presents a practical example of Aurora communication with Typhoon HIL simulators, specifically the HIL101, HIL404, HIL506, and HIL606. It provides a ready-to-use user…
Conventional model-based control in power electronics relies heavily on deriving precise mathematical models of the physical system. In contrast, data-driven control shifts this paradigm by…
This page outlines the configuration methods for analog I/O channels on imperix controllers. While digital I/Os are configured exclusively via software and remain consistent across…
This article describes how to use the XY plot module of imperix Cockpit to interact with the user code running on imperix controllers, namely the…
This page presents a practical example of Aurora communication with OPAL-RT simulators, specifically the OP4510 and OP4512. It provides a ready-to-use user application, along with…
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