These notes are specifically related to imperix products. They address both control or power hardware, as well as software solutions. Their aim is to document what users should understand to properly use imperix products. Product notes, therefore, provide complementary information with respect notably to product datasheets.
While highly intuitive to use, imperix controllers in fact rely on an internal architecture and operation that sometimes differs significantly from traditional DSPs, MCUs, and…
Imperix controllers possess protection mechanisms that operate fully independently from all software, i.e., independently from the user app CPU, the supervisor CPU, and the FPGA….
This note provides practical guidelines and code snippets for programming imperix controllers with the CPP SDK. It follows up on the getting started guide and…
This article provides instructions to get started with the CPP SDK, focusing on the workflow associated with the development of C++ control algorithms for imperix…
Most imperix controllers feature 36 bidirectional 3.3V I/O lines, commonly known as USR pins. Driven directly from the FPGA, these custom-application I/Os are ideal for…
This page describes how to upgrade the imperix IP in an existing sandbox project, whether to restore compatibility with a newer SDK version or to…
Debugging an FPGA design can be difficult without clear visibility into the high-speed logic fabric, where signals change at nanosecond scales. Xilinx Integrated Logic Analyzer…
Beyond the built-in modulators accessible from the user application, the imperix sandbox enables PWM generation directly within the FPGA, allowing for the implementation of custom…
Imperix provides direct access to ADC measurements within the FPGA which allows for reduced delay between the sampling and the processing, but also helps supporting…
On imperix controllers, the CPU exchanges data with the FPGA via the SBIO bus. This memory-mapped bus allows the CPU user app to read and…
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