Most imperix controllers feature 36 bidirectional 3.3V I/O lines, commonly known as USR pins. Driven directly from the FPGA, these custom-application I/Os are ideal for…
This page describes how to upgrade the imperix IP in an existing sandbox project, whether to restore compatibility with a newer SDK version or to…
Beyond the built-in modulators accessible from the user application, the imperix sandbox enables PWM generation directly within the FPGA, allowing for the implementation of custom…
Imperix provides direct access to ADC measurements within the FPGA which allows for reduced delay between the sampling and the processing, but also helps supporting…
On imperix controllers, the CPU exchanges data with the FPGA via the SBIO bus. This memory-mapped bus allows the CPU user app to read and…
This page presents a practical example of Aurora communication with Typhoon HIL simulators, specifically the HIL101, HIL404, HIL506, and HIL606. It provides a ready-to-use user…
This page presents a practical example of Aurora communication with OPAL-RT simulators, specifically the OP4510 and OP4512. It provides a ready-to-use user application, along with…
While imperix controllers are typically programmed with applications built in Simulink or PLECS, imperix also provides direct access to FPGA resources through its FPGA development…
This page presents a practical example of Aurora communication with with Plexim simulators, namely the RT-Box 1, RT-Box 2 and RT-Box 3. It provides a…
The EnDat block instantiates an EnDat master to communicate with compatible digital encoders and similar digital sensors, typically in motor drive applications. This block is…
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