Imperix controllers typically have their CPU programmed from Simulink or PLECS. Additionally, the controllers also offer user-programmable FPGA resources in a dedicated area called Sandbox….
This page presents a practical example of Aurora communication with Plexim simulators, namely the RT-Box 1, RT-Box 2 and RT-Box 3. It provides a ready-to-use…
The EnDat block instantiates an EnDat master to communicate with compatible digital encoders and similar digital sensors, typically in motor drive applications. This block is…
The BiSS-C block instantiates a Bidirectional Synchronous Serial – Communication (BiSS-C) master to communicate with BiSS-C-compatible digital encoders and similar digital sensors, typically in motor…
The SSI block instantiates a Synchronous Serial Interface (SSI) master to communicate with SSI-compatible digital encoders and similar digital sensors, typically in motor drive applications….
As introduced in PN109, SFP communication constitutes a convenient way to interconnect devices. Widely used, it offers an efficient layer on which protocols such as…
The SFP ports on imperix controllers are primarily intended for interconnecting controllers within a RealSync network. However, these SFP+ ports can also be repurposed for…
This page provides the imperix sources files required to start programming the FPGA on imperix controllers. The provided archive contains the imperix firmware IP and…
This page presents a first HIL example to get started with a B-Box RCP and an OPAL-RT OP4510. Although validated with an OP4510, the provided…
This article introduces an example of Finite Control Set Model Predictive Control (FCS-MPC) for an LCL-filtered voltage-controlled inverter. The proposed control implementation is derived from…
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