Download and update imperix IP for FPGA sandbox

This page provides the source files, namely the imperix firmware IP and project template creation script, to start programming the FPGA on imperix devices. After a description of the archives content, step-by-step procedures explain how to generate a working Vivado project from the source files or from project-specific scripts provided in the Knowledge Base, and how to update the firmware for existing sandbox projects.

To learn how to use the imperix IP, please refer to the getting started with FPGA page and the imperix IP user guide page.

To find all FPGA-related notes, you can visit FPGA development homepage.

Downloads

Change logs

New in 3.10 Rev. 0

• Repurposing the SFP ports
  One or multiple SPF ports can now be detached from RealSync and the corresponding GTX transceivers accessed via additional ports on the imperix firmware IP. The SFP ports can therefore be used for custom communication, using Aurora 8B10B for instance.
• Saving of FPGA resource
  Unused modulators can bow be disabled in the imperix firmware IP, significantly reducing the resource consumption of the IP in the FPGA. Users with large custom FPGA designs might take advantage of it to extend their design even further.

New in 3.10 Rev. 1

• Improved configurability of the RES block
  The resolution and excitation frequency of the resolver can now be changed. The default values are 12-bit and 10 kHz, as set in the previous firmware versions.

New in 3.10 Rev. 2

Internal version.

New in 3.10 Rev. 3

• Support for remote debugging over the network
  Thanks to the support of Xilinx Virtual Cable (XVC), it is now possible to instantiate and connect to on-chip Integrated Logic Analyzer (ILA) cores via Ethernet. This provides access to the internal FPGA signals without any physical JTAG cable, greatly facilitating the debug of FPGA logic.
• Propagation of Ethernet between devices at full gigabit speed
  An upgrade of the Ethernet-over-RealSync protocol – from Mbps to Gbps – allows inter-device traffic to reach the Gigabit speed in master-slave and multi-master setups.

Archives content

Content structure

The content of the archives follows the following structure.

VHDL helper modules

Creating a new project

The creation of a new project can be achieved either manually, or through the provided generation scripts. Please refer to the desired creation procedure in the two following subsections.

Step-by-step project creation

To create the template manually, please extend the box below and follow the detailed procedure.

How to manually create the imperix Vivado project template

Create a project with the imperix firmware IP

1. Open Vivado.
2. Once open, click on Create Project.
3. Chose a name and a location.
4. Select project type RTL Project and check the box Do not specify sources at this time.
5. Select the part named xc7z030fbg676-3.
6. Hit Finish. The project should open.
7. Go to the IP Catalog, right-click on Vivado Repository, hit Add repository…
   Select <my_project>/ix_repo/
   The IMPERIX_FW IP, clock_gen, and user_regs interfaces should be found. Press OK.
8. Click on Create block design, name it “top” and click OK.
9. Open the freshly created block design, do a right-click in a blank area of the design, select Add IP… and search for “IMPERIX_FW” and hit ENTER.
10. Keep the [Ctrl] key pressed and select the IP pins flt, gpi, private_in, DDR, FIXED_IO, BBOS, USR, gpo, pwm and private_out. Hit [Ctrl+T] to create top-level ports.
11. By default Vivado adds “_0” after each port name. Remove the “_0” from every port. For that, click on each port and change the name property in the Block Pin Properties block (appearing on the left of the diagram by default). For instance, change “flt_0[15:0]” to “flt[15:0]“.
12. The user_fw_id input may be used to identify the firmware version. We recommend instantiating a Constant IP (Right-click, Add IP…, search for Constant) to give an identification number to the design. To change the constant width, double-click on the Constant block and set the Const Width to 16.
13. Go to the Sources tab, right-click on the block design file (top.bd) and select Create HDL Wrapper…
    In the dialog box choose Let Vivado manage wrapper and auto-update and hit OK.
14. Right-click on the Design Sources folder. Choose Add Sources… and check Add or create constraints. Click on Add Files. Select <my_project>/sandbox_pins.xdc. Uncheck Copy constraints files into project. Hit Finish.

From this point the project is synthesizable.

Adding the AXI4-Stream interface

Adding the AXI4-Stream interface is optional. It is useful if the FPGA control design uses AXI4-Stream interfaces.

1. Right-click on Design Sources
   Choose Add Sources….
   Check Add or create design sources.
2. Press Add Files. Go to your repository and select <my_project>/AXIS_interface.vhd.
   We recommend unchecking “Copy sources into project” and working directly from the files in the folder <my_project>/hdl/ so the sources can be shared across multiple projects. Press Finish and wait for the update to finish.
3. Right-click somewhere in the block design and choose Add module… and select the ix_axis_interface module. Alternatively, the file listed in the Design Sources can be drag and dropped it on the block diagram.
4. Connect the pins as follows (to get a clear layout, change “Default View” to “No Loops” in the top bar of the Diagram block, then right-click somewhere in the block design and press Regenerate Layout).

Project creation using the generation scripts

To automatically generate the template project via the provided generation scripts, please follow the detailed procedure below.

1. Download the sources files FPGA_Sandbox_template_*.zip archive.
2. Unzip it and save the content somewhere on the PC.
3. Rename the folder to something more explicit.

4. Open scripts/create_project.bat using a text editor.
5. Set the vivado_path variable to match the Vivado version installed on the PC.

6. Double click on scripts/create_project.bat. Windows Defender SmartScreen may display a warning pop-up. Simply click More info then Run anyway.
7. Enter a project name and click Enter.

The Vivado sandbox project will be created and configured, its block design is shown below.

Starting from generation scripts

This section describes how to proceed when starting with a project-specific script downloaded on our Knowledge Base.

1. Download the source files FPGA_Sandbox_template_*.zip archive.
2. Unzip it and save the content somewhere on the PC.
3. Rename the folder to something more explicit.

4. Download the project-specific generation scripts on the page of interest in the Knowledge Base (e.g., aurora_ix_plexim_gen_scripts.zip in Aurora link with Plexim via SFP).
5. Unzip it and open it.
6. Copy-paste the content of each subfolder into the corresponding subfolder of the source files (e.g., content of <scripts folder>/hdl/ into <source files>/hdl/, etc.). If any, the scripts in the top-level of the scripts folder must be placed in <source files>/scripts/.

7. Double-click on the newly copied <source files>/scripts/<script_name>.bat file. Windows Defender SmartScreen may display a warning pop-up. Simply click More info then Run anyway.
8. Enter a project name and click Enter.

9. Once the Vivado is created, click on Generate Bitstream. Vivado will proceed to the synthesis and implementation of the bitstream.
10. Once generated, click on File > Export > Export Bitstream File and store the bitstream somewhere on the PC.
11. Load the bitstream on the target with Cockpit.
12. The FPGA is now ready to go.
13. Next steps are generally to connect the physical setup, and download, build and load the Simulink (or PLECS) model for the CPU.

Upgrade procedure

This section describes how to upgrade the imperix IP from an existing Vivado project.

1. Download the FPGA_Sandbox_template zip file for the targeted SDK version and unzip it.
2. In the <project_dir>/ix_repo/ directory, replaces the interfaces and ips folders with the ones from the freshly downloaded sandbox template.

4. Copy the new constraint file to <project_dir>/constraints/.
   ⚠️If modifications were made to the constraint file (e.g. to use USR pins), these modifications need to be reported to the new constraint file.

5. Open the Vivado project. Remove the old constraint file and add the new one.

6. Upgrade the imperix sandbox IP. It may generate warnings, which is expected.

7. Follow the expandable sections in the accordion below depending on the used imperix IP version.

Upgrading to 3.9 Rev. 4

When upgrading the imperix IP to version 3.9 Rev. 4 or later, the following changes must be made:

1. The interface BBOX was added, make sure to connect it to the top-level interface

2. private_in and private_out size changed, make sure to update the top-level ports accordingly

3. After these changes, re-generate the top-level HDL wrapper. To make sure Vivado apply the change properly, we recommend deleting the top_wrapper.vhd and re-create the HDL wrapper.

In SDK 2024.1, a new feature called the synchronous averaging has been introduced. ADC channels with synchronous averaging enabled only output a new value once per CLOCK_0 period, regardless of the oversampling ratio set in the CONFIG block. When using an oversampling ratio, we recommend disabling the synchronous averaging option in the ADC blocks.

Upgrading to 3.9 Rev. 5 and 3.10

If upgrading from an older version, do not miss the upgrading to 3.9 Rev.4 section above.

The imperix IP version 3.9 Rev. 5 brings the following changes. Additional information are provided after the procedure.

• The SBI and SBO interfaces were replaced by the memory-mapped SBIO_BUS.
  The provided VHDL module sbio_registers.vhd makes the bridge between the SBIO_BUS and the traditional SBI and SBO interfaces that were present in the imperix IP 3.9 Rev. 4 and earlier
• The sbio_interconnect .vhd was added for convenience

Upgrade procedure

1. In <project_dir>/ix_repo/
   – replace AXIS_interface.vhd
   – add sbio_interconnect.vhd and sbio_registers.vhd

2. If using the AXI-Stream interface (AXIS_interface.vhd)
   
   In Vivado, click Refresh Changed Modules then reconnect the SBIO_BUS interface.

3. If using SBI and SBO registers
   The provided VHDL module sbio_registers.vhd makes the bridge between the SBIO_BUS and the traditional SBI and SBO interfaces that were present in the imperix IP 3.9 Rev. 4 and earlier.

Legacy IPs for older SDKs