SFP communication with an RTDS MMC simulator
PN122Table of Contents
As introduced in PN118, SFP communication constitutes a convenient way to interconnect devices. Widely used, it offers an efficient layer on which protocols such as Aurora can be implemented to exchange data.
In this example, the SFP communication connects a B-Box RCP (or B-Board PRO) to a GTSOC V2 from RTDS. It makes the bridge between the control – executed in the B-Box RCP (or B-Board PRO) – and the MMC simulation model running on the GTSOC board.
Following the configuration of our MMC bundle, the simulated MMC contains 6 arms and 4 submodules per arm, as shown in Fig. 1. The closed-loop model provided to show proper communication and control of the MMC is also directly adapted from the AN009.
Communication chain
The control and communication chain is depicted in Fig. 2. The closed-loop control running in the CPU produces duty cycles, which are converted to PWM signals by the carrier-based modulator (CB-PWM). These PWM signals are directly available in the FPGA, where they are packed into frames by the RTDS MMC driver and transferred to the MMC simulation model via Aurora 8B/10B.
The simulation model outputs computed voltages and currents, as well as additional real-time data, and sends them back as Aurora frames to the B-Board. Once received, the frames are decoded by the driver and their content is made available to the CPU through SBI registers.
Required software
- Xilinx Vivado 2022.1 or later (previous versions may work but have not been tested).
Installation guide available here. - FPGA sandbox template 3.10 or later.
Available on the FPGA download page. - C++ or ACG SDK version 2024.3 or later.
Available on the SDK download page.
Downloads
The Simulink model running in the CPU and the Vivado project to generate the FPGA bitstream are available below.
Results
As shown in Fig. 3, the closed-loop control generates a three-phase output current, while controlling the bus current and the submodule voltages. The submodule voltages are limited to 63.5A (or kA) in the RTDS, explaining why the bus voltage has been intentionally reduced to 100V.
All submodule voltages, arm voltages and currents, as well as real-time data are available to the user in the CPU and the FPGA. The section Simulink model describes through which SBI the received quantities can be accessed. In the FPGA, dedicated registers can be directly accessed at the output of the RTDS MMC driver.
Provided files
Simulink model
In order to validate the proper communication between the MMC model running on the RTDS GTSOC V2, a simple closed-loop model – depicted in Fig. 4 – is provided. This model is largely inspired by the AN009, where more information about the operation principles of the MMC converter and controller is available.
Data received from the RTDS GTSOC V2 through the SFP communication can be accessed via the following SBI registers. The mapping of the SBI to the received quantities is available here below:
Note that most of the received quantities are 32-bit wide, explaining why they extend over two 16-bit registers. In particular, voltages and currents are assumed to be encoded as fixed-point 16.16 data. Status are 16-bit words, so each 16-bit SBI register corresponds to one SM status.
Vivado project
The Vivado block design of the current example is provided below, in Fig. 5. A detailed description of the driver ports can be found in the driver source file (cf. RTDS_MMC_SFP_gen_script.zip > usr_repo/RTDS_MMC.vhd).
Click here to open as a PDF.
How to generate the design and bitstream
To generate the design using the script, download the RTDS_MMC_SFP_gen_script.zip file provided in the Downloads section above and follow the steps described in PN118/Vivado project. Before executing the .bat file, additionally copy the usr_repo folder within the project directory, as shown below:
Once the project is ready, click on ‘Generate Bitstream’ to launch the bitstream generation. The warning about the signal size mismatchs can be ignored.
How to change the SFP port
The provided Vivado project uses the port SFP2 (DOWN 1). If you want to use SFP0 (UP) or SFP1 (DOWN 0) for the SFP communication:
- In the Vivado block design, double-click on the IX IP.
- In the IX IP configuration panel, select options to reflect the desired configuration, as depicted in Fig. 7. Click ‘OK’ to apply the changes. As unconnected tx{p,n} and rx{p,n} IX IP ports could lead to Vivado warnings or issues, note that only the required SFP port(s) must be checked.
- Connect the tx{p,n} and rx{p,n} IX IP port to the corresponding ports of the Aurora IP.
Fig. 7 – IX IP configuration panel with RealSync disabled on SFP0 (UP).
How to change the number of submodules
The RTDS MMC driver provided in the Vivado project is meant to be easily extendable. It however requires minimal experience in FPGA design, typically with Vivado and VHDL basics.
If you want to increase the number of submodules per arm, e.g. to N=12, the following steps are recommended.
- Make sure that your modulator(s) can produce the Nx6 PWM signals.
- In the listed VHDL files, set the N generic to the desired value: RTDS_MMC.vhd, RTDS_rtds_firing_words.vhd, RTDS_emitter.vhd, gen_complementary.vhd. The latter can be discarded if your modulator already outputs the complementary signals.
- Route the PWM signals produced by your modulator to the ‘pwm’ input of the RTDS MMC driver.
If the capacitor voltages and submodule status must be accessed, the following steps are recommended. Note that the VHDL files for the reception logic are ready to admit up to 20 submodules.
- In RTDS_MMC.vhd, add the missing outputs to the RTDS MMC driver (typically, add B_cap_v_sm_XX_leg_X and C_sm_XX_XX_leg_X outputs). Make sure that they are connected to the right serial-to-parallel module.
- In reg_32b_to_16b_66.vhd, extend the module inputs and outputs to match the desired number.
- If necessary, use an SBIO interconnect to instantiate up to 4 SBIO registers blocks and therefore increase the number of available SBIO registers to 1024. The sbio_interconnect.vhd is available in the hdl folder. Add it to the project sources to be able to insert it in the design.
- Do not forget to add the corresponding SBI blocks in the CPU model accordingly.
