The operation of a grid-tied power converter (such as the 3-phases PV inverter) requires that the control software implements a grid synchronization technique. One well-known approach consists in using a three-phase PLL to project the AC grid quantities into a synchronous rotating reference frame. The PLL algorithm is usually executed on the CPU of the…
This technical note provides an example of how a fast hysteresis current controller can be implemented, leveraging the possibility of editing the FPGA firmware for rapid control prototyping applications. This example implements the direct current control of a three-phase passive load. It relies on manually-generated VHDL code. The automated generation of VHDL code is presented…
This note provides step-by-step guidance to create a Xilinx Vivado project, add customized logic, generate a bitstream, and load it into the B-Box/B-Board. The required software and sources files are: Vivado HL Design Suite (available for free as the WebPACK edition) Sandbox sources Software resources Installing Vivado SDK A Xilinx account is needed to download…
This page documents the imperix firmware IP for Xilinx Vivado, which contains the imperix FPGA logic of the imperix controllers (B-Board PRO and B-Box RCP). The imperix firmware IP enables the user to: Exchange data between the application control code running in the CPU (PS) and the logic in the FPGA (PL); Drive the PWM…
Model Composer is a Simulink add-on software developed by Xilinx. It is a high-level synthesis (HLS) tool that allows the user to program an FPGA-based algorithm without the need to write code. Thanks to this approach, behavioral simulations can be run prior to code generation, enabling engineers to validate the correctness of their FPGA design…
This page documents the imperix firmware IP for Xilinx Vivado, which contains the imperix FPGA logic of the imperix controllers, namely the B-Box RCP, the B-Board PRO, the B-Box Micro and the TPI. The imperix firmware IP enables the user to: Exchange data between the application control code running in the CPU (PS) and the logic in…
Xilinx System Generator for DSP (SysGen) is a MATLAB Simulink add-on that enables the development of architecture-level FPGA designs using graphical blocks programming. Users can validate their designs through simulation in Simulink and the design can be packaged into a Vivado IP and easily imported into a Vivado project. Alternatives to Xilinx System Generator An…
MATLAB HDL Coder is a MATLAB add-on that can generate VHDL and Verilog code from MATLAB functions or Simulink models. This approach can greatly accelerate rapid prototyping as the design is performed from a higher level of abstraction. The second benefit is the possibility to simulate the FPGA logic directly from within Simulink. A typical…
This page provides step-by-step guidance to install Xilinx Vivado Design Suite, the tools used to program the FPGA of imperix controllers.
Xilinx Vitis HLS (formerly Xilinx Vivado HLS) is a High-Level Synthesis (HLS) tool developed by Xilinx and available at no cost. Vitis HLS allows the user to easily create complex FPGA-based algorithms using C/C++ code. It supports complex data types (floating-points, fixed-points,…) and math functions (sine, arctan, sqrt,…). It also supports AXI4-Stream to easily exchange…
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