Getting started with FPGA programming
PN159While the standard imperix workflow utilises the ACG SDK (for Simulink or PLECS ) or the CPP SDK (for C/C++) to program the controller’s CPU,…
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Introduction to HDL Coder
PN162
HDL Coder is a MATLAB add-on that can generate VHDL and Verilog code from MATLAB functions or Simulink models. This approach can greatly accelerate rapid…
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Xilinx Vitis HLS introduction
Xilinx Vitis HLS (formerly Xilinx Vivado HLS) is a High-Level Synthesis (HLS) tool developed by Xilinx and available at no cost. Vitis HLS allows the…
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Xilinx System Generator introduction
Xilinx System Generator for DSP (SysGen) is a MATLAB Simulink add-on that enables the development of architecture-level FPGA designs using graphical blocks programming. Users can…
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Xilinx Model Composer introduction
Model Composer is a Simulink add-on software developed by Xilinx. It is a high-level synthesis (HLS) tool that allows the user to program an FPGA-based…
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Synchronous reference frame (SRF) PLL
TN103
This note provides insights into the operating principle of a synchronous reference frame PLL (SRF PLL), also known as DQ-type PLL. An implementation of an…
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CAN in – CAN input mailbox
SD016
The CAN_in block implements an input mailbox that supports receiving messages using the CAN bus protocol. To send messages, the CAN out block should be…
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Tunable parameter
The tunable parameter block creates a variable that can be altered in real-time using imperix Cockpit. It supports the int32, uint32, and float data types. Simultaneously, the tunable parameter…
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Probe
The probe variable block creates a variable that can be watched and logged in real-time using using imperix Cockpit. It supports the int32, uint32, and…
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Core state
The Core state block returns the state of the target: The block also provides a second signal called “reset” that can be wired to the…
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