# Multi-converter system for micro-grid

Table of Contents

This application presents a multi-converter system with three DC/AC converters connected to a micro-grid. This could typically represent three photovoltaic inverters sharing a single PCC (point of common coupling).

The note is focused on the implementation on B-Box RCP, notably how to develop the control for all three converters from a single Simulink file. The note also addressed the implementation of interleaved operation, providing improved harmonic performance at the PCC.

## Software resources

## Control implementation of the multi-converter system

Different approaches are possible for implementing multi-converter systems using B-Box RCP / B-Board PRO. They are summarized in Inter-devices communication (PN114).

– Parallel mode (independent controllers)

– I/O extension mode (master-slave)

More information on the possible multi-controller configurations is given on the page: distributed control.

The possible approaches can be compared in the following manner

**Parallel mode**

In this case, it is assumed that three B-Boxes are used, one for each converter system. Also, a Simulink/PLECS control file is flashed in each B-Box.

**Pros**

- Best available computing power.
- More intuitive approach.

**Cons**

- PWM operation cannot be synchronized among all three converters
- Grid-level operation cannot be simulated very easily with Simulink (multiple files). Thatās however better with PLECS.

**I/O extension mode**

In this case, the control for all three converters is implemented in one single Simulink/PLECS file, using one master and two slaves. As such, only one CPU is operating (inside the master).

**Pros**

- All three converters are very well synchronized.
- Grid-level operation is easy to simulate.

**Cons**

- Complex control algorithms may be too demanding for one single CPU.
- Less intuitive approach.

As this example aims to focus on the converter interleaving, the I/O extension mode is chosen. The corresponding implementation is shown below.

For each converter system, the control is similar to that presented in Central PV inverter (AN006). It implements the following features:

- Grid synchronization is achieved using a SOGI-PLL (see TN104).
- The grid-tied inverter uses vector control for the grid current (see TN106).
- DC bus voltage control is using a conventional cascaded control strategy (see TN108).
- The boost is current-controlled using a basic PI controller (see TN105).
- The maximum power point tracking (MPPT) is implemented using a Perturb&Observe approach, executed at a slower rate (see TN117).

### Interleaving in multi-converter system

Similar to the operation of multi-phase DC/DC converters, the operation of several grid-tied inverters can be interleaved. This allows reducing the total current ripple, thereby improving the harmonic performance at the point of common coupling (PCC), notably on the measured voltage.

As presented in [1], the optimal phase-shift angle *K _{i}* for each converter

*Inv*depends on the modulation depth. For high modulation indices, such as in grid-tied inverters, the best THD reduction is achieved with:

_{i}$$\displaystyle K_i = i\cdot\frac{2\pi}{2n}$$

where \(i\) is the inverter index and *n* the total number of interleaved converters.

In this case, the phase-shifts are therefore selected as \(K_0=0.0\), \(K_1=\pi/3\), and \(K_2=2\pi/3\).

### References

[1] D. Zhang, F. Wang, R. Burgos, R. Lai and D. Boroyevich, “Impact of Interleaving on AC Passive Components of Paralleled Three-Phase Voltage-Source Converters,” in *IEEE Transactions on Industry Applications*, vol. 46, May-june 2010.

## Simulation results

The provided Simulink file was used to generate the following simulation results. Various reference steps are included:

- At 52ms, inverter 1 produces a step change of reactive power (quadrature current
*I*)_{q1_ref} - At 76ms, inverter 2 produces a step change of reactive power (quadrature current
*I*)_{q2_ref} - At 103ms, inverter 3 produces a step change of reactive power (quadrature current
*I*)_{q3_ref} - At 150ms, all inverters undergo a DC bus voltage reference step (
*U*)._{dc_ref}

The following results compare the achieved results, with and without interleaved modulation.