SOGI PLL
TN104Table of Contents
This note covers the operating principles of a Second-Order Generalized Integrators (SOGI) PLL and presents a possible implementation for numerical power electronics controllers.
What is a SOGI PLL?
Second-order Generalized Integrators (SOGI) have recently been proposed for use as phase detectors [2], namely within PLL structures in grid-tie power inverters.
Numerous grid synchronization techniques exist, featuring various performances, objectives, and complexity. An extensive review of possible implementations is proposed in [1]. Among them, many rely on a phase detector that offers some immunity to voltage waveform distortions (harmonics and/or unbalances). This immunity, related to the employed filtering techniques, is often a difficult trade-off with other expectations in terms of dynamic performance (phase and/or amplitude tracking).
SOGI structures are essentially notch filters (band-pass) that can be easily tuned to the grid frequency. In addition, these have the attractive benefit of providing simultaneous access to both the filtered output as well as a quadrature-shifted version of the same output (α and β axes). As such, they allow for an easy implementation that can fit that of conventional dq-type PLLs (using the Park transform as phase detector).
The general principle of the SOGI-based PLL is given below:
SOGI PLL digital implementation
The discrete-time implementation of a SOGI-based PLL is mostly dependent on the selected approach for the discretization of the two integrators comprised within the SOGI itself.
Reference [2] analyzes the impact of the selected discretization approach on each integrator (namely forward-Euler, backward-Euler, Tustin, ZOH, etc.) on the stability of the overall SOGI subsystem. The article concludes on the suitability of the backward-Euler integrators. Alternatively, reference [3] also compares various possible techniques, concluding on the superiority of the so-called Third-order Integrator method, thanks to a lower residual ripple on the frequency and amplitude signals. The corresponding integrator implementation is shown below:
Single-phase implementation
The structure of the proposed single-phase SOGI-type PLL is shown below:
Three-phase implementation
The somewhat equivalent of the above-presented structure for three-phase systems is given below. In this case, two SOGIs are used, not only to take benefit from their filtering characteristics, but also to combine their outputs as to detect the positive sequence exclusively. This approach, designated as DSOGI-PLL by their authors [4], provides excellent immunity against grid voltage unbalances.
Academic references
[1] M. Boyra and J. Thomas, “A review on synchronization methods for grid-connected three-phase VSC under unbalanced and distorted conditions,” in Proc. EPE Conf., Birmingham, 2011.
[2] M. Ciobotaru, R. Teodorescu and F. Blaabjerg, “A new single-phase PLL structure based on a second-order generalized integrator,” in Proc. PESC Conf., Rhodos, June 2006.
[3] F.J. Rodríguez, E. Bueno, M. Aredes, L.G.B. Rolim, F.A.S. Neves and M.C. Cavalcanti, “Discrete-time
implementation of second-order generalized integrators for grid converters,” in Proc. IECON Conf.,
Orlando, Nov. 2008.
[4] P. Rodríguez, R. Teodorescu, I. Candela, A. V. Timbus, M. Liserre and F. Blaabjerg, “New positive-sequence voltage detector for grid synchronization of power converters under faulty grid conditions,” in Proc. PESC Conf, Jeju, 2006.
Simulink implementation of a SOGI PLL
The implementations on Simulink of the above-presented PLLs are available in the model provided below:
These Simulink subsystems are masked, so that the corresponding tunable parameters can be easily accessed and modified.
This implementation can be easily integrated into control algorithms developed using imperix ACG SDK toolbox.
Experimental results of SOGI PLL
The following graph provides an experimental comparison between the DQ-PLL and the DSOGI-PLL. The DSOGI-PLL provides much better immunity against unbalanced and distorted grid voltages compared to the standard DQ-PLL:
