DC bus balancing of NPC converters

This technical note presents different techniques for the DC bus balancing of NPC converters. More generally, an introduction on Neutral Point Clamped (NPC) converter is given in TN135.

In multilevel converters, and therefore in NPC converters also, a possible imbalance between the internal DC busses may overstress – or even damage – the capacitors and semiconductors of the converter. Besides, the output voltage and phase current may also deteriorate. As such, maintaining adequate balancing is necessary at all times.

Therefore, this note introduces possible techniques for maintaining the proper balancing of NPC converters. A Simulink file with a suitable control example is also provided, for both Carrier-Based and Space-Vector modulations. Finally, experimental results obtained with the imperix products are also shown.

Software resources

The zip file contains two Simulink models with two different implementations of the presented DC bus balancing technique, using Carrier-Based and Space Vector PWM modulation.

Causes of unbalanced voltage

Generally, the overall voltage of the DC-link is controlled by a cascaded control. However, the voltage of each half bus is not controlled individually. This is why imbalances may occur, although the total DC bus voltage may remain constant.

During the converter operation, each phase can have one of three possible states:

• “P”, when the phase is clamped to \(V_{dc+}\),
• “O”, when the phase is clamped to the midpoint of the DC bus,
• “N”, when the phase is clamped to \(V_{dc-}\).

Consequently, a three-phase NPC converter has 27 possible states that can be represented as vectors in the Clarke referential, as presented in TN135 :

These vectors can be divided into 4 groups according to their magnitude:

• zero vectors: 0
• small vectors: \(V_{dc}/3\)
• medium vectors: \(V_{dc}/\sqrt{3}\)
• large vectors: \(2V_{dc}/3\)

The effect of each one of these vector groups on the balancing of the NPC converter is represented in the figure below. Zero and large vectors haven’t any unbalancing effect. For medium vectors, the sign of the voltage variation is undefined. The small vectors are the ones that have the largest impact [1].

The current path determines if the DC bus capacitors are charging or discharging.

Methods for the balancing of NPC converters

In this technical note, two different methods are presented in order to balance to DC bus voltage of an NPC converter: one for Carrier-Based modulation (CB-PWM), and the second for Space-Vector modulation (SV-PWM). Further details on modulation techniques are given in TN135.

Carrier-based PWM

For carrier-based modulation, each of the two carriers is related to its corresponding half DC bus voltage. Therefore, if the amplitude of the carriers is changed to reflect the effective voltage, the utilization of the DC-link is changed [2]. This is shown in the picture below:

In practice, it is often easier to achieve the balancing of NPC converters by altering the value of the duty cycle rather than the amplitude of the triangular carrier. Therefore, the same result can be observed using the following formula:

$$\begin{align} d_1′ &= \displaystyle\frac{d_1 + x}{1+x} = \frac{V_a + x}{1+x} \\ d_2′ &= \displaystyle\frac{d_2}{1-x} = \frac{V_a + 1}{1-x} \end{align}$$

With \(x\) dependent on the sign of the phase current and defined as:

$$x = \displaystyle\frac{V_{dc,high}-V_{dc,low}}{V_{dc}} \cdot \text{sgn}(I)$$

Space vector PWM

As presented in TN135, SV-PWM requires that the two active vectors \(V_{x}\) and \(V_{y}\) that are the closest to \(V_{ref}\) are found, as well as a zero vector \(V_{z}\). Then, the corresponding duty cycles \(d_{x}\), \(d_{y}\), and \(d_{z}\) can be determined.

These vectors are then organized following a specific pattern to reduce the number of commutations. Normally, the duty cycle \(d_{z}\) is equally distributed between two new zero vectors \(V_{0}\) and \(V_{7}\). However, as vectors \(V_{7}\) are always P-type small vectors, and vectors \(V_{0}\) are always N-type vectors, it is possible to adjust the share between \(V_{0}\) and \(V_{7}\) in order to influence the DC voltages balancing. This is the main principle governing the presented balancing algorithm.

Subsequently, the duty ratios are computed as:

$$\begin{aligned} &d_a=d_x+d_y+d_7\newline &d_b=d_y+d_7 \qquad &\text{with} \qquad &\begin{cases}d_7 = d_z/2 +x\\ x = \displaystyle\frac{V_{dc,high}-V_{dc,low}}{V_{dc}} \cdot \text{sgn}(I) \end{cases} \newline &d_c=d_7 \end{aligned}$$

Academic references about the balancing of NPC converters

[1] Kalpesh H. Bhalodi, Pramod Agrawal, “Space Vector Modulation with DC-Link Voltage Balancing Control for Three-Level Inverters”, in IEEE International Conference on Power Electronic, 2007.

[2] Wojciech Kołomyjski, “Modulation Strategies for Three-level PWM Converter-fed Induction Machine Drives”, thesis available on Warsaw University of Technology website, page 52, 2009.

B-Box / B-Board implementation

The two figures below show the proposed implementation in Simulink.

For the SV-PWM, the block provided in the imperix blockset takes the reference vector in the αβ0 coordinates and automatically computes the duty cycles for each phase. For the balancing of the DC bus, adding the same correction \(x\) to the duty cycles of each phase is equivalent to adding a homopolar component to the reference vector \(E_{\alpha\beta 0}^*\):

Experimental results

The balancing of NPC converters has been tested with a simple grid-connected operation. To this end, the DC bus is initially charged with unbalanced conditions(\(\Delta V \approx 30\,\text{V}\)), and then the converter starts switching.

The following graph shows the experimental result with the method for SV-PWM. Proper balancing of the NPC converter is achieved after approximately 1s.

Independently of the method used for the balancing of NPC converters, the time for balancing the DC bus depends on the current reference of the converter: the higher the current, the faster the DC bus balances.

The experimental result shown above is done with \(I_{d,ref}=2\,\text{A}\). With higher currents, the balancing lasts a few hundred milliseconds.