abc to dq0
SD029The “abc to dq0” block computes the coordinates of a three-phase (abc) signal in a rotating reference frame (dq0). The angle of the rotating reference…
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High-Level Synthesis for FPGA developments
TN142
High-level synthesis (HLS) tools greatly facilitate the implementation of complex power electronics controller algorithms in FPGA. Indeed HLS tools allow the user to work at…
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Custom PWM modulator implementation in FPGA
To implement power converter control algorithms in an FPGA, it is often required to develop an FPGA-based pulse-width modulation (PWM) module. Therefore, this note presents…
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Installing the Xilinx Blockset for Simulink
The Xilinx blockset for MATLAB & Simulink is a single toolbox that unifies Model Composer (HLS), System Generator for DSP (HDL) as well as the Xilinx AI…
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FPGA development on imperix controllers
Usually, the user programs the imperix controller’s CPU using imperix ACG SDK or C++ SDK, and uses the pre-implemented FPGA peripherals such as the ADC…
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AXI4-Stream IPs from Xilinx
TN140
This page presents some useful Xilinx IP cores for Vivado. These IPs use the widely used AXI4-Stream protocol to easily exchange data with other Xilinx…
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FPGA-based control of a grid-tied inverter
This note presents an FPGA control implementation of a grid-tied current-controlled inverter. It combines several control modules presented in different Technical Notes to form a…
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Getting started with FPGA programming
While the standard imperix workflow utilises the ACG SDK (for Simulink or PLECS ) or the CPP SDK (for C/C++) to program the controller’s CPU,…
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Introduction to HDL Coder
HDL Coder is a MATLAB add-on that can generate VHDL and Verilog code from MATLAB functions or Simulink models. This approach can greatly accelerate rapid…
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Xilinx Vitis HLS introduction
Xilinx Vitis HLS (formerly Xilinx Vivado HLS) is a High-Level Synthesis (HLS) tool developed by Xilinx and available at no cost. Vitis HLS allows the…
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