The BiSS-C block instantiates a Bidirectional Synchronous Serial – Communication (BiSS-C) master to communicate with BiSS-C-compatible digital encoders and similar digital sensors, typically in motor…
The SSI block instantiates a Synchronous Serial Interface (SSI) master to communicate with SSI-compatible digital encoders and similar digital sensors, typically in motor drive applications….
Most imperix controllers feature 36 bidirectional 3.3V I/O lines, commonly known as USR pins. Driven directly from the FPGA, these custom-application I/Os are ideal for…
Debugging an FPGA design can be difficult without clear visibility into the high-speed logic fabric, where signals change at nanosecond scales. Xilinx Integrated Logic Analyzer…
This page describes how to upgrade the imperix IP in an existing sandbox project, whether to restore compatibility with a newer SDK version or to…
On imperix controllers, the CPU exchanges data with the FPGA via the SBIO bus. This memory-mapped bus allows the CPU user app to read and…
Beyond the built-in modulators accessible from the user application, the imperix sandbox enables PWM generation directly within the FPGA, allowing for the implementation of custom…
Imperix provides direct access to ADC measurements within the FPGA which allows for reduced delay between the sampling and the processing, but also helps supporting…
Introduction Power electronic converters pose a specific sampling challenge: the signals of interest (currents and voltages) are low-frequency components, but they are combined with a…
This page is a quick-start guide to build an interleaved boost converter using imperix equipment. It is specifically made to accompany users who want to…
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