FLT – Fault inputs
The FLT block configures and reads the digital fault inputs. The fault input pin signals are tied to the fault manager and, using the FLT…
The FLT block configures and reads the digital fault inputs. The fault input pin signals are tied to the fault manager and, using the FLT…
The angle decoder (DEC) block decodes quadrature-encoded signals produced by incremental encoders for motor drive applications. The imperix controllers provide decoder inputs for quadrature-encoder speed/position…
The GPO block, or its equivalent C++ routines, is responsible for asserting the specific logic states of the General Purpose Outputs (GPO) pins. This interface…
The GPI block (or its C++ routines) is responsible for reading the the logic states of the General Purpose Inputs (GPI) pins. This function allows…
The DAC block, or its equivalent C++ routines, is used to apply a given value to one of the Digital-to-Analog Converter (DAC) channels of the…
The ADC block (or C++ routines) are used to access data from a given Analog-to-Digital Converter (ADC) channel. They also serve to configure how this…
Imperix controllers feature 4 clock generators, CLK0, CLK1, CLK2 and CLK3, running at 250 MHz. They provide time bases for FPGA resources such as the…
The CONFIG block primarily serves to configure the main clock (CLK0) as well as its derivatives. Together, these clocks define the frequency and phase of…
This note covers the rotor field-oriented control of an induction machine and its implementation on a user-configurable voltage-source inverter.
This technical note presents an FPGA-based Direct Torque Control (DTC) of a PMSM motor using Vivado HLS, coupled with the possibility to customize the FPGA…
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