Timing configuration on imperix controllers

This article details the timing configuration on imperix controllers, focusing on the four internal time bases (CLK0–CLK3) that govern ADC sampling, control-loop execution, and PWM modulation. The presented principles are common to all controllers and apply to both standalone systems and multi-controller networks.

As a background to this note, important information is provided in PN258, which addresses commonly used sampling techniques for power electronics. Related information can also be found in PN135 and PN137, which detail how these essential timings are modeled in Simulation (using Simulink and PLECS, respectively).

Timing architecture

Unlike microcontrollers that commonly implement a cascade of events and interrupts, imperix controllers manage peripheral timing centrally with predetermined phase shifts. This permits avoiding unnecessary latencies and enables the dissemination of common (syntonized) clocks across the control network. More information about the firmware architecture of imperix controllers is provided in PN253.

For each control system (single or multiple stacked controllers), four time bases are available, implemented through CLK0-CLK3:

Among these clocks:

• CLK0 plays a special role, as it sets the timing for both ADC sampling and CPU control execution. Its frequency is therefore forced to be constant to ensure regular sampling. Two important internal signals are derived from CLK0, namely :
  • SCLK, the physical sampling clock (frequency \(F_{\text{SCLK}}\)). It runs at the same rate as CLK0, but with a user-defined constant phase shift that sets the exact sampling instant.
  • A CPU interrupt clock (frequency \(F_{\text{CPU}}\)), which triggers the execution of the control task. When required, \(F_{\text{CPU}}\) can be obtained by decimating \(F_{\text{SCLK}}\) using a postscaler.
• Conversely, CLK1-CLK3 are optional clocks available for use within modulators. These can be of variable frequency.

Thanks to RealSync, all clocks within a network of imperix controllers are synchronized with a timing accuracy of ±2ns. This means that the phase coherence and synchronization inherent in local resources are maintained across the entire distributed network. More information about the operation of imperix controllers in a multi-device configuration is given in PNxxx.

Timing configuration

When using the ACG SDK, all four clocks can be configured through the CONFIG and CLK blocks. When using the CPP SDK, equivalent configuration routines are available.

The CONFIG block is mandatory inside every Simulink or PLECS model. Among its various functions, it handles configuring CLK0 and its associated signals. In contrast, CLK blocks (CLK1–3) are optional. These clocks are used only to drive modulation blocks (PWMs) when the PWM time base must differ from CLK0. Further details on simulating these blocks can be found on the PN135 and PN137 pages.

In practice, most control schemes rely solely on CLK0. This clock is configured in the CONFIG block, which sets the sampling and CPU interrupt frequencies. In many applications, CLK0 also defines the PWM switching frequency. This common arrangement is often referred to as single rate update. It is illustrated in Fig. 3.

Consequently, the clock configuration impacts three subsystems as follows:

• ADC resources are always referenced to CLK0, which defines the sampling instants according to the physical sampling clock SCLK at frequency \(F_{\text{SCLK}}\).
• CPU execution is always tied to CLK0 with a configurable postscaler. It is automatically phase-shifted so that the control algorithms start executing as soon as ADC data are available in the CPU cache.
• PWM blocks can be referenced to any of CLK0–CLK3. The selected PWM clock can be an integer multiple or submultiple of CLK0, or it may be non-integer related (including variable-frequency operation), depending on the modulation scheme and the chosen clock source.

Figure 4 shows the use of CLK1 in a configuration that executed the control twice as fast as the PWMs. This configuration is referred to here as double-rate update.

Basic timing configurations

On imperix controllers, the timing configurations arise from the relationship between CLK0 and the selected PWM time base. While CLK0 provides a fixed reference for ADC sampling and CPU execution, the PWM clocks determine the carrier frequency of the modulators and the specific instants at which the duty cycles are latched.

These update instants are not the same across all PWM carrier types. With a sawtooth (single-edge) carrier, there is only one effective update opportunity per PWM period, since a single intersection between the reference and the carrier determines the duty cycle. With a triangular (double-edge) carrier, two crossings occur per period, creating two distinct opportunities to update the duty cycle, as shown in Fig. 5.

Therefore, two fundamental timing configurations stem from these situations:

• Single rate update, in which case the control task is executed once per PWM period, and duty cycles are updated once per PWM period.
• Double rate update, in which case the control task is executed twice per PWM period, and duty cycles are updated twice per PWM period.

With the double-rate update configuration, the control performance is enhanced by doubling the execution frequency (\(F_{CPU}\)) relative to the PWM switching frequency (\(F_{SW}\)). By executing the control task twice per carrier period, the system achieves a higher effective sampling rate and more frequent duty cycle updates. This approach allows for a higher closed-loop bandwidth at a given switching frequency, improving the overall dynamic response without increasing switching losses.

Single rate update

Single rate update is the simplest timing configuration and remains the most widely used. In this configuration, ADC sampling, CPU control execution, and PWM duty-cycle updates all occur at the same fundamental frequency (which is also the switching frequency). Consequently, only CLK0 is required, as shown in Fig. 6.

The remaining degree of freedom is the sampling phase, which must be selected based on the desired sampling approach (e.g., synchronous sampling or synchronous averaging; see PN258). When relevant, the sampling phase must be adjusted to account for analog front-end delays. The practical selection of this sampling phase is discussed below.

Configuration of the sampling phase

On imperix controllers, configuring CLK0 (the sampling frequency) is only the first step. The sampling instant must also be defined by selecting an appropriate sampling phase of SCLK relative to CLK0. This is configured in the CONFIG block, as shown below:

In most applications, the required phase value depends largely on the sampling method:

• When synchronous averaging is used, the exact sampling instant within the PWM period is not critical, as the measurement represents a periodic average over a full switching period. In this scenario, the phase is typically adjusted to minimize the total control loop delay, i.e. as late as possible.
• When synchronous sampling is used, the sampling instant must be chosen to yield a representative ripple-averaged value. This generally leads to two phase options, 0 or 0.5, which often need to be adjusted to compensate for propagation delays inherent in the analog measurement chain, such as those arising from low sensor bandwidth.

Double rate update

In a double rate update control scheme on imperix controllers, ADC sampling and CPU execution remain tied to CLK0, while the PWM block(s) use a separate time base (CLK1 to CLK3). To obtain two duty cycle update opportunities within one PWM period, the PWM time base must be set to \(F_{\text{CLK1}} = 0.5\cdot F_{\text{CLK0}}\). This configuration is illustrated in Fig. 8.

As with single-rate configurations, the optimal sampling phase in double-rate update mode depends on the chosen acquisition technique :

• When synchronous averaging is used, the acquisition must be configured to average over two CLK0 periods (in the ADC block). Since CLK0 runs at twice the switching frequency in this configuration, this setting ensures that the average is calculated over one full PWM period.
• When synchronous sampling is used, the sampling phase is typically set to 0 to align the acquisition with representative ripple-averaged values. This value may be further adjusted to compensate for delays inherent in the analog measurement chain (such as limited sensor bandwidth).

From an implementation perspective, Fig. 9 summarizes the corresponding block-level structure and clock assignments for the closed-loop control of a buck converter using double-rate update. Reference Simulink and PLECS models implementing this configuration are provided below.

Advanced timing configurations

Postscaler

Imperix controllers permit running the CPU at a submultiple of CLK0 by adjusting the post-scaler in the CONFIG block. Then, the CPU’s execution frequency is defined as \(F_{\text{CPU}} = F_{\text{CLK0}}/Postscaler\).

In such a case, the CPU operates at this reduced rate and the sampling frequency remains synchronized with CLK0. This decoupling is particularly advantageous when controlling interleaved converters. In such topologies, the sampling phase must be specifically shifted for each converter leg to capture the current at the ideal moment. Consequently, the sampling frequency must be \(N\) times faster than the CPU execution rate, where \(N\) represents the number of legs.

Figure 10 illustrates the timing view within the Cockpit interface when a postscaler of 3 is applied. In this configuration, the CPU executes three times slower than both CLK0 and SCLK.

Data history

Imperix controllers also allow multiple samples to be retrieved at each CPU interrupt via the Data history function of the ADC block. This functionality is particularly advantageous when using a postscaler, as it enables the control algorithm to access the complete set of samples acquired during the preceding decimated interval. As illustrated in Fig.11, this ensures that all intermediate data points are available for processing, regardless of whether they were captured before the current CPU task was triggered.

Variable switching frequency

While most converters operate at a fixed frequency, some applications require dynamic frequency adjustment for regulation. A typical example is the LLC resonant converter, where the output voltage is controlled by modulating the switching frequency.

On imperix controllers, this is achieved by configuring the CLK1-3 blocks to enable real-time frequency updates, as shown in Fig. 12. See also PN121 on variable-frequency operation with imperix controllers.

When variable switching frequencies are used, the sampling frequency remains fixed and tied to CLK0. Consequently, any form of synchronous acquisition is not possible, as the sampling instants will no longer align with the varying PWM periods.

Multi-rate execution

Both Simulink and PLECS provide the flexibility to execute specific parts of a control algorithm at a lower frequency than the main execution rate (\(F_{\text{CPU}}\)). As this is managed via dedicated software blocks, it requires no modifications to the controller’s timing configurations. This function is described in more detail in PN256.

This feature may be useful for cascaded control strategies, where high-level outer loops, such as voltage or motor speed regulation, can run at a lower rate. In contrast, the inner loops continue to operate at the main execution rate to improve dynamic performance. An example of multi-rate execution can be found in Motor speed control or in MPPT algorithms.

Related topics

The following articles are indirectly related to timing configuration and provide useful additional information:

• (PN258) Sampling techniques for power electronics presents commonly used techniques and their associated delays. Imperix’s synchronous averaging approach is also explained in detail.
• (PN108) Analog I/O configuration for imperix controllers explains how to configure (via software) imperix controllers for implementing the desired sampling strategy.
• (PN135) Simulation essentials with Simulink explains how the timing configuration is modeled in simulation and how the model should be configured to guarantee the simulation’s accuracy.
• (PN137) Simulation essentials with PLECS addresses the same content as PN135, but with PLECS.
• (PN253) Architecture of imperix controllers presents their firmware, including a section about clock generation.
• (PN261) Operating principles of imperix controllers notably explains what constraints the maximum achievable closed-loop control rate.