This note presents an FPGA control implementation of a grid-tied current-controlled inverter. It combines several control modules presented in different Technical Notes to form a…
This note explains how to get started with the implementation of power converter control algorithms in the FPGA of imperix power electronic controllers. The benefit…
Xilinx Vitis HLS (formerly Xilinx Vivado HLS) is a High-Level Synthesis (HLS) tool developed by Xilinx and available at no cost. Vitis HLS allows the…
Xilinx System Generator for DSP (SysGen) is a MATLAB Simulink add-on that enables the development of architecture-level FPGA designs using graphical blocks programming. Users can…
This note provides insights into the operating principle of a synchronous reference frame PLL (SRF PLL), also known as DQ-type PLL. An implementation of an…
The tunable parameter block creates a variable that can be altered in real-time using imperix Cockpit. It supports the int32, uint32, and float data types. Simultaneously, the tunable parameter…
The probe variable block creates a variable that can be watched and logged in real-time using using imperix Cockpit. It supports the int32, uint32, and…
The Core state block returns the state of the target: The block also provides a second signal called “reset” that can be wired to the…
The external reset block provides a signal that can be wired to the external reset input of PID controllers to keep the integrator at reset…
This block issues a request to enable or disable the PWM outputs, similar to the “Enable outputs” button of BB Control utility software. It issues…
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