CLK – Clock generators
This page is based on SDK 2025.2. Imperix controllers feature 4 clock generators, CLK0, CLK1, CLK2 and CLK3, running at 250 MHz. They provide time bases…
This page is based on SDK 2025.2. Imperix controllers feature 4 clock generators, CLK0, CLK1, CLK2 and CLK3, running at 250 MHz. They provide time bases…
This page is based on SDK 2025.2. The CONFIG block is mandatory and serves to configure the main clock CLK0, the sampling clock SCLK and…
This technical note presents an FPGA-based Direct Torque Control (DTC) of a PMSM motor using Vivado HLS, coupled with the possibility to customize the FPGA…
This technical note shows how the implementation of an FPGA-based hysteresis controller can be conducted, starting from the modeling stage, following with automated VHDL code…
This technical note provides an example of how a fast hysteresis current controller can be implemented, leveraging the possibility of editing the FPGA firmware for…
This technical note presents various techniques for the DC bus balancing of NPC converters. These techniques are notably used in TN135, which implements a grid-tied…
This note focuses on the multi-master feature which allows executing control codes on multiple imperix power converter controllers interconnected using optical fiber (SFP). The imperix in-house…
The BB Control Timing info tab provides a graphical representation of the various computation and communication delays involved in the B-Board PRO and B-Box RCP…
In a standard configuration, the control algorithm is executed just after each sampling event. The oversampling feature enables the possibility to set up multiple sampling…
This product note explains how to compute the discrete control delay of a control algorithm running on an imperix controller. Context The execution of a…
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