ADC – Analog data acquisition
SD003The ADC block (or C++ routines) are used to access data from a given Analog-to-Digital Converter (ADC) channel. They also serve to configure how this…
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CLK – Clock generators
Imperix controllers feature 4 clock generators, CLK0, CLK1, CLK2 and CLK3, running at 250 MHz. They provide time bases for FPGA resources such as the…
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CONFIG – Control task configuration
SD001
The CONFIG block primarily serves to configure the main clock (CLK0) as well as its derivatives. Together, these clocks define the frequency and phase of…
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FPGA-based Direct Torque Control using Vivado HLS
This technical note presents an FPGA-based Direct Torque Control (DTC) of a PMSM motor using Vivado HLS, coupled with the possibility to customize the FPGA…
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FPGA-based hysteresis controller for three-phase inverter using HDL Coder
This technical note shows how the implementation of an FPGA-based hysteresis controller can be conducted, starting from the modeling stage, following with automated VHDL code…
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FPGA-based hysteresis current controller for three-phase inverter
This technical note provides an example of how a fast hysteresis current controller can be implemented, leveraging the possibility of editing the FPGA firmware for…
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Multi-converter system for micro-grid
AN008
This application showcases a multi-converter system consisting of three DC/AC converters connected to a microgrid, representing a typical scenario such as three photovoltaic inverters sharing…
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Three-phase Voltage Source Inverter (VSI)
This example generates three phase alternating currents from a voltage source inverter in an open loop manner. It can be used in a grid-forming application.
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Multi-master feature for distributed networked control systems
This note focuses on the multi-master feature which allows executing control codes on multiple imperix power converter controllers interconnected using optical fiber (SFP). The imperix in-house…
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SCLK multiplier configuration and utilization
In a standard configuration, the control algorithm executes immediately following each sampling event. The SCLK multiplier modifies this behavior by allowing multiple sampling events to…
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