GPO – General purpose outputs
The GPO block, or its equivalent C++ routines, is responsible for asserting the specific logic states of the General Purpose Outputs (GPO) pins. This interface…
The GPO block, or its equivalent C++ routines, is responsible for asserting the specific logic states of the General Purpose Outputs (GPO) pins. This interface…
The GPI block (or its C++ routines) is responsible for reading the the logic states of the General Purpose Inputs (GPI) pins. This function allows…
The DAC block, or its equivalent C++ routines, is used to apply a given value to one of the Digital-to-Analog Converter (DAC) channels of the…
The ADC block (or C++ routines) are used to access data from a given Analog-to-Digital Converter (ADC) channel. They also serve to configure how this…
Imperix controllers feature 4 clock generators, CLK0, CLK1, CLK2, and CLK3, which can be freely configured as derivatives of the 250 MHz base clock. These…
This technical note presents an FPGA-based Direct Torque Control (DTC) of a PMSM motor using Vivado HLS, coupled with the possibility to customize the FPGA…
This technical note shows how an SPI communication link can be established between an FPGA and an external Analog-to-Digital Converter (ADC). The development setup will…
This technical note shows how the implementation of an FPGA-based hysteresis controller can be conducted, starting from the modeling stage, following with automated VHDL code…
This technical note provides an example of how a fast hysteresis current controller can be implemented, leveraging the possibility of editing the FPGA firmware for…
This note focuses on the multi-master feature which allows executing control codes on multiple imperix power converter controllers interconnected using optical fiber (SFP). The imperix in-house…
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