PEB – Half-bridge module

The PEB block is a simulation model included in the Imperix Power library. It models the imperix half-bridge module PEB8038, PEB8024, and PEB4050 in Simulink and PLECS simulation.

For more information regarding the Imperix Power library, please read Getting started with Imperix Power library.

Modeling of PEB

The schematic of the PEB model is depicted on the right. It has two modeling levels:

• (A) Simple
• (B) Detailed

For more detailed model parameters and measurement results, please contact [email protected].

DC bus

The schematic of the equivalent DC bus is shown below.

The simulation model is relevant within a given frequency range. The frequency validity range is 0-4 kHz for the (A) Simple level and 0-100 kHz for the (B) Detailed level. In that range, the impedance and transfer function of the model are reasonably close to the modeled system, which can be seen along with the plots of the proposed models. The model parameters are also displayed below.

	C_1 [uF]	ESR_1 [mΩ]
(A)	500*2	0
(B)	500*2	60/2

	C_1 [uF]	ESR_1 [mΩ]
(A)	235*2	0
(B)	235*2	110/2

	C_1 [uF]	ESR_1 [mΩ]
(A)	1100*2	0
(B)	1100*2	15/2

Embedded sensors

A generic sensor can be approximately modeled by an ideal sensor in series with an optional first-order Low-Pass Filter (LPF). The relationship between sensor’s bandwidth \(f_{BW}\) and the time constant \(\tau\) of the LPF follows \(\tau = \frac{1}{2\pi f_{BW}}\).

A sensor is modeled as a first-order LPF only if its bandwidth lies within the frequency range of a given modeling level. Otherwise, it is modeled as an ideal sensor. The following table summarizes the information on all the sensors in the PEB.

Power transistors

The PEB block offers two options for modeling the power transistors:

• Switched The transistors are modeled by individual power semiconductors. The control inputs are instantaneous logical gate signals.
• Averaged The transistors are modeled by controlled voltage and current sources. The control inputs are the relative on-times of the semiconductors with values between 0 and 1. The gate signals can be either instantaneous (using only values 0 and 1) or time-averaged.

Although the functionality is practically the same, these options are named differently in PLECS and Simulink Simscape to be consistent with their naming conventions.

Simulink PEB block

Port specification

• The input g is the gate signal. It has a width of 2, representing the signals for the high and low gates.
  • For Switching devices (switched) model, g is the 0/1 PWM signal.
  • For Switching Function (averaged) model, g can be either the 0/1 PWM signal or the duty cycle between 0 and 1.
• The output V is the measured voltage across the DC bus.
• The output I is the measured output current.
• The connection port DC+ is the electrical port connected to the positive pole of the DC bus.
• The connection port DC- is the electrical port connected to the negative pole of the DC bus.
• The connection port N is the electrical port connected to the midpoint of the DC bus.
• The connection port AC is the electrical port connected to the AC output.

Parameters

• Use global configurations is ticked when the block receives global configurations from the Config block.
• Modeling level selects the modeling level of the peripheral circuits.
• Transistor model type selects the model of the power transistors.
• Half-bridge module selects the type of PEB products to be simulated.
• Initial DC bus voltage [V] defines the initial voltage across the DC bus when the simulation starts.

PLECS PEB block

Port specification

• The input g is the gate signal with a width of 2, representing the signals for the high and low gates.
  • For Switched model, g is the 0/1 PWM signal.
  • For Sub-cycle average model, g can be either the 0/1 PWM signal or the duty cycle between 0 and 1.
• The output V is the measured voltage across the DC bus.
• The output I is the measured output current.
• The connection port DC+ is the electrical port connected to the positive pole of the DC bus.
• The connection port DC- is the electrical port connected to the negative pole of the DC bus.
• The connection port N is the electrical port connected to the midpoint of the DC bus.
• The connection port AC is the electrical port connected to the AC output.

Parameters

• Modeling level selects the modeling level of the peripheral circuits.
• Transistor model type selects the model of the power transistors.
• Half-bridge module selects the type of PEB products to be simulated.
• DC Bus midpoint terminal visible shows or hides the port N.
• Initial DC bus voltage [V] defines the initial voltage across the DC bus when the simulation starts.

Probe signals

The following signals can be monitored by a Probe block in PLECS.

• Gate signals monitors the gate signals present at the input g.
• DC Bus voltage true value [V] monitors the true value of the DC bus voltage in Volt.
• DC Bus voltage sensor output [V] monitors the physical output of the DC bus voltage sensor in Volt.
• Output current true value [A] monitors the true value of the output current in Amp.
• Output current sensor output [V] monitors the physical output of the output current sensor in Volt.