CB-PWM – Carrier-based PWM
The carrier-based PWM block supports generating PWM signals using common digital carriers. The following configuration options are available: With sawtooth carriers, the duty-cycle and phase-shift…
These notes provide documentation for all the blocks and functions packed with ACG SDK and CPP SDK. Each page covers the configuration parameters and the use of a specific peripheral block within the Simulink, PLECS, and C++ environments.
The carrier-based PWM block supports generating PWM signals using common digital carriers. The following configuration options are available: With sawtooth carriers, the duty-cycle and phase-shift…
The Pulse Width Modulators (PWM) share the dead-time generation and the activate/deactivate features, configured through the output mode, deadtime, and activate parameters. The said PWM…
At the hardware level, FLT inputs are special-purpose digital inputs that can be configured to generate a “hardware fault” in order to instantly disable all PWM outputs…
Imperix controllers provide angle decoder (DEC) resources to decode quadrature-encoded signals produced by incremental encoders, which are widely used in motor drive applications. At the…
At the hardware level, GPO outputs are general-purpose digital outputs that can be configured for various purposes. This block and the associated C/C++ routines provide means to…
At the hardware level, GPI inputs are general-purpose digital inputs that can be configured for various purposes. This block and the associated C/C++ routines provide means to…
The DAC block, or its equivalent C++ routines, is used to apply a given value to one of the Digital-to-Analog Converter (DAC) channels of the…
The ADC block (or C++ routines) is used to access data from a given Analog-to-Digital Converter (ADC) channel. It also configures how this data is…
Imperix controllers feature 4 clock generators, CLK0, CLK1, CLK2, and CLK3, which can be freely configured as derivatives of the 250 MHz base clock. These…
The CONFIG block primarily configures the main clock (CLK0) and its derivatives. Together, these clocks define the frequency and phase of the sampling events, as…
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