Setting up the FPGA development toolchain
This note provides step-by-step guidance to create a Xilinx Vivado project, add customized logic, generate a bitstream, and load it into the B-Box/B-Board. The required…
This note provides step-by-step guidance to create a Xilinx Vivado project, add customized logic, generate a bitstream, and load it into the B-Box/B-Board. The required…
This page documents the imperix firmware IP for Xilinx Vivado, which contains the imperix FPGA logic of the imperix controllers, namely the B-Box RCP, the B-Board PRO,…
This document provides instructions on how to interface an incremental encoder with a B-Box RCP or a B-Board PRO and how to read the motor…
This note covers the configuration and implementation of variable frequency operation with imperix controllers (B-Box RCP and B-BoardPRO). Changing the modulation frequency during the control…
This product note explains how to compute the discrete control delay of a control algorithm running on an imperix controller. Context The execution of a…
In a standard configuration, the control algorithm is executed just after each sampling event. The oversampling feature enables the possibility to set up multiple sampling…
The BB Control Timing info tab provides a graphical representation of the various computation and communication delays involved in the B-Board PRO and B-Box RCP…
Closed-loop current control for a grid-tied Neutral Point Clamped (NPC) inverter. The considered setup is a three-phase three-wire NPC inverter supplied by a DC source and connected to the grid.
This technical note presents various techniques for the DC bus balancing of NPC converters. These techniques are notably used in TN135, which implements a grid-tied…
This technical note provides an example of how a fast hysteresis current controller can be implemented, leveraging the possibility of editing the FPGA firmware for…
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